amd64_edac: Improve error injection

When injecting DRAM ECC errors over the F3xB[8,C] interface, the machine
does this by injecting the error in the next non-cached access. This
takes relatively long time on a normal system so that in order for us to
expedite it, we disable the caches around the injection.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

1 files changed, 17 insertions, 1 deletions

diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c
index 8977e2fa61da..8c171fa1cb9b 100644
--- a/drivers/edac/amd64_edac_inj.c
+++ b/drivers/edac/amd64_edac_inj.c
@@ -153,8 +153,8 @@ static ssize_t amd64_inject_write_store(struct device *dev,
 {
         struct mem_ctl_info *mci = to_mci(dev);
         struct amd64_pvt *pvt = mci->pvt_info;
+        u32 section, word_bits, tmp;
         unsigned long value;
-        u32 section, word_bits;
         int ret;
 
         ret = strict_strtoul(data, 10, &value);
@@ -168,9 +168,25 @@ static ssize_t amd64_inject_write_store(struct device *dev,
 
         word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
 
+        pr_notice_once("Don't forget to decrease MCE polling interval in\n"
+                        "/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
+                        "so that you can get the error report faster.\n");
+
+        on_each_cpu(disable_caches, NULL, 1);
+
         /* Issue 'word' and 'bit' along with the READ request */
         amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
 
+ retry:
+        /* wait until injection happens */
+        amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
+        if (tmp & F10_NB_ARR_ECC_WR_REQ) {
+                cpu_relax();
+                goto retry;
+        }
+
+        on_each_cpu(enable_caches, NULL, 1);
+
         edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
 
         return count;