clk: tegra: Model oscillator as clock

Currently the Tegra clock driver simplifies the clock tree somewhat by
taking advantage of the fact that clk_m runs at the same frequency as
the oscillator. While that's true on all currently supported SoCs, it
does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
divided down from the oscillator frequency. To support that setup, add
a separate clock for the oscillator that both clk_m and pll_ref derive
from.

Modify the tegra_osc_clk_init() function to take an additional divider
parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
will read the divider from a register in the clock & reset controller.

Signed-off-by: Thierry Reding <treding@nvidia.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 48cb1c13ede5..d6ac00647faf 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -615,10 +615,10 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
 
 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
-int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks,
-                                unsigned long *input_freqs, int num,
-                                unsigned long *osc_freq,
-                                unsigned long *pll_ref_freq);
+int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
+                       unsigned long *input_freqs, unsigned int num,
+                       unsigned int clk_m_div, unsigned long *osc_freq,
+                       unsigned long *pll_ref_freq);
 void tegra_super_clk_gen4_init(void __iomem *clk_base,
                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
                         struct tegra_clk_pll_params *pll_params);