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authorArnd Bergmann <arnd@arndb.de>2012-12-02 11:59:57 -0500
committerArnd Bergmann <arnd@arndb.de>2013-03-12 12:39:58 -0400
commitd9909ebe650f028459b9be5a2321fee520b446b0 (patch)
tree09736f1e19ed89396841a2654e4d8b901ac73334 /drivers/clk/spear
parent2b9c613c4ee1756664fcbf6fc4926fee3e7139c3 (diff)
ARM: spear: make clock driver independent of headers
Device drivers should not access MMIO registers through hardcoded platform specific address constants. Instead, we can pass the MMIO token to the spear clock driver in the initialization routine to contain that knowledge in the platform code itself. Ideally, the clock driver would use of_iomap() or similar to get the address, and that can be used later, but for now, this is the minimal change. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'drivers/clk/spear')
-rw-r--r--drivers/clk/spear/spear1310_clock.c64
-rw-r--r--drivers/clk/spear/spear1340_clock.c63
-rw-r--r--drivers/clk/spear/spear3xx_clock.c60
-rw-r--r--drivers/clk/spear/spear6xx_clock.c31
4 files changed, 112 insertions, 106 deletions
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index ed9af4278619..aedbbe12f321 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -17,12 +17,10 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/of_platform.h> 18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h> 19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h" 20#include "clk.h"
22 21
23#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
24/* PLL related registers and bit values */ 22/* PLL related registers and bit values */
25#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210) 23#define SPEAR1310_PLL_CFG (misc_base + 0x210)
26 /* PLL_CFG bit values */ 24 /* PLL_CFG bit values */
27 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 25 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
28 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 26 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
@@ -35,15 +33,15 @@
35 #define SPEAR1310_PLL2_CLK_SHIFT 22 33 #define SPEAR1310_PLL2_CLK_SHIFT 22
36 #define SPEAR1310_PLL1_CLK_SHIFT 20 34 #define SPEAR1310_PLL1_CLK_SHIFT 20
37 35
38#define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214) 36#define SPEAR1310_PLL1_CTR (misc_base + 0x214)
39#define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218) 37#define SPEAR1310_PLL1_FRQ (misc_base + 0x218)
40#define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220) 38#define SPEAR1310_PLL2_CTR (misc_base + 0x220)
41#define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224) 39#define SPEAR1310_PLL2_FRQ (misc_base + 0x224)
42#define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C) 40#define SPEAR1310_PLL3_CTR (misc_base + 0x22C)
43#define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230) 41#define SPEAR1310_PLL3_FRQ (misc_base + 0x230)
44#define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238) 42#define SPEAR1310_PLL4_CTR (misc_base + 0x238)
45#define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C) 43#define SPEAR1310_PLL4_FRQ (misc_base + 0x23C)
46#define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244) 44#define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244)
47 /* PERIP_CLK_CFG bit values */ 45 /* PERIP_CLK_CFG bit values */
48 #define SPEAR1310_GPT_OSC24_VAL 0 46 #define SPEAR1310_GPT_OSC24_VAL 0
49 #define SPEAR1310_GPT_APB_VAL 1 47 #define SPEAR1310_GPT_APB_VAL 1
@@ -65,7 +63,7 @@
65 #define SPEAR1310_C3_CLK_MASK 1 63 #define SPEAR1310_C3_CLK_MASK 1
66 #define SPEAR1310_C3_CLK_SHIFT 1 64 #define SPEAR1310_C3_CLK_SHIFT 1
67 65
68#define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248) 66#define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248)
69 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 67 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
70 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 68 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
71 #define SPEAR1310_GMAC_PHY_CLK_MASK 1 69 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
@@ -73,7 +71,7 @@
73 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 71 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
74 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
75 73
76#define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C) 74#define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C)
77 /* I2S_CLK_CFG register mask */ 75 /* I2S_CLK_CFG register mask */
78 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F 76 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F
79 #define SPEAR1310_I2S_SCLK_X_SHIFT 27 77 #define SPEAR1310_I2S_SCLK_X_SHIFT 27
@@ -91,21 +89,21 @@
91 #define SPEAR1310_I2S_SRC_CLK_MASK 2 89 #define SPEAR1310_I2S_SRC_CLK_MASK 2
92 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 90 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0
93 91
94#define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250) 92#define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250)
95#define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254) 93#define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254)
96#define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258) 94#define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258)
97#define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C) 95#define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C)
98#define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260) 96#define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260)
99#define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264) 97#define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264)
100#define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268) 98#define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268)
101#define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270) 99#define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270)
102#define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280) 100#define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280)
103#define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288) 101#define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288)
104#define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290) 102#define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290)
105#define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298) 103#define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298)
106 /* Check Fractional synthesizer reg masks */ 104 /* Check Fractional synthesizer reg masks */
107 105
108#define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300) 106#define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300)
109 /* PERIP1_CLK_ENB register masks */ 107 /* PERIP1_CLK_ENB register masks */
110 #define SPEAR1310_RTC_CLK_ENB 31 108 #define SPEAR1310_RTC_CLK_ENB 31
111 #define SPEAR1310_ADC_CLK_ENB 30 109 #define SPEAR1310_ADC_CLK_ENB 30
@@ -138,7 +136,7 @@
138 #define SPEAR1310_SYSROM_CLK_ENB 1 136 #define SPEAR1310_SYSROM_CLK_ENB 1
139 #define SPEAR1310_BUS_CLK_ENB 0 137 #define SPEAR1310_BUS_CLK_ENB 0
140 138
141#define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304) 139#define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304)
142 /* PERIP2_CLK_ENB register masks */ 140 /* PERIP2_CLK_ENB register masks */
143 #define SPEAR1310_THSENS_CLK_ENB 8 141 #define SPEAR1310_THSENS_CLK_ENB 8
144 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 142 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
@@ -150,7 +148,7 @@
150 #define SPEAR1310_DDR_CORE_CLK_ENB 1 148 #define SPEAR1310_DDR_CORE_CLK_ENB 1
151 #define SPEAR1310_DDR_CTRL_CLK_ENB 0 149 #define SPEAR1310_DDR_CTRL_CLK_ENB 0
152 150
153#define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310) 151#define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310)
154 /* RAS_CLK_ENB register masks */ 152 /* RAS_CLK_ENB register masks */
155 #define SPEAR1310_SYNT3_CLK_ENB 17 153 #define SPEAR1310_SYNT3_CLK_ENB 17
156 #define SPEAR1310_SYNT2_CLK_ENB 16 154 #define SPEAR1310_SYNT2_CLK_ENB 16
@@ -172,7 +170,7 @@
172 #define SPEAR1310_ACLK_CLK_ENB 0 170 #define SPEAR1310_ACLK_CLK_ENB 0
173 171
174/* RAS Area Control Register */ 172/* RAS Area Control Register */
175#define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000) 173#define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000)
176 #define SPEAR1310_SSP1_CLK_MASK 3 174 #define SPEAR1310_SSP1_CLK_MASK 3
177 #define SPEAR1310_SSP1_CLK_SHIFT 26 175 #define SPEAR1310_SSP1_CLK_SHIFT 26
178 #define SPEAR1310_TDM_CLK_MASK 1 176 #define SPEAR1310_TDM_CLK_MASK 1
@@ -197,12 +195,12 @@
197 #define SPEAR1310_PCI_CLK_MASK 1 195 #define SPEAR1310_PCI_CLK_MASK 1
198 #define SPEAR1310_PCI_CLK_SHIFT 0 196 #define SPEAR1310_PCI_CLK_SHIFT 0
199 197
200#define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004) 198#define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004)
201 #define SPEAR1310_PHY_CLK_MASK 0x3 199 #define SPEAR1310_PHY_CLK_MASK 0x3
202 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 200 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0
203 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 201 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
204 202
205#define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148) 203#define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148)
206 #define SPEAR1310_CAN1_CLK_ENB 25 204 #define SPEAR1310_CAN1_CLK_ENB 25
207 #define SPEAR1310_CAN0_CLK_ENB 24 205 #define SPEAR1310_CAN0_CLK_ENB 24
208 #define SPEAR1310_GPT64_CLK_ENB 23 206 #define SPEAR1310_GPT64_CLK_ENB 23
@@ -385,7 +383,7 @@ static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
385static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; 383static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
386static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; 384static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
387 385
388void __init spear1310_clk_init(void) 386void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
389{ 387{
390 struct clk *clk, *clk1; 388 struct clk *clk, *clk1;
391 389
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 82abea366b78..3ceb4507e95f 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -17,18 +17,17 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/of_platform.h> 18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h> 19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h" 20#include "clk.h"
22 21
23/* Clock Configuration Registers */ 22/* Clock Configuration Registers */
24#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200) 23#define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
25 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27 24 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
26 #define SPEAR1340_HCLK_SRC_SEL_MASK 1 25 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
27 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23 26 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
28 #define SPEAR1340_SCLK_SRC_SEL_MASK 3 27 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
29 28
30/* PLL related registers and bit values */ 29/* PLL related registers and bit values */
31#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210) 30#define SPEAR1340_PLL_CFG (misc_base + 0x210)
32 /* PLL_CFG bit values */ 31 /* PLL_CFG bit values */
33 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1 32 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
34 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31 33 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
@@ -40,15 +39,15 @@
40 #define SPEAR1340_PLL2_CLK_SHIFT 22 39 #define SPEAR1340_PLL2_CLK_SHIFT 22
41 #define SPEAR1340_PLL1_CLK_SHIFT 20 40 #define SPEAR1340_PLL1_CLK_SHIFT 20
42 41
43#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214) 42#define SPEAR1340_PLL1_CTR (misc_base + 0x214)
44#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218) 43#define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
45#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220) 44#define SPEAR1340_PLL2_CTR (misc_base + 0x220)
46#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224) 45#define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
47#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C) 46#define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
48#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230) 47#define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
49#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238) 48#define SPEAR1340_PLL4_CTR (misc_base + 0x238)
50#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C) 49#define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
51#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244) 50#define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244)
52 /* PERIP_CLK_CFG bit values */ 51 /* PERIP_CLK_CFG bit values */
53 #define SPEAR1340_SPDIF_CLK_MASK 1 52 #define SPEAR1340_SPDIF_CLK_MASK 1
54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15 53 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
@@ -66,13 +65,13 @@
66 #define SPEAR1340_C3_CLK_MASK 1 65 #define SPEAR1340_C3_CLK_MASK 1
67 #define SPEAR1340_C3_CLK_SHIFT 1 66 #define SPEAR1340_C3_CLK_SHIFT 1
68 67
69#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248) 68#define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248)
70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1 69 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2 70 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2 71 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0 72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
74 73
75#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C) 74#define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C)
76 /* I2S_CLK_CFG register mask */ 75 /* I2S_CLK_CFG register mask */
77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F 76 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27 77 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
@@ -90,21 +89,21 @@
90 #define SPEAR1340_I2S_SRC_CLK_MASK 2 89 #define SPEAR1340_I2S_SRC_CLK_MASK 2
91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0 90 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
92 91
93#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250) 92#define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250)
94#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254) 93#define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254)
95#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258) 94#define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258)
96#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C) 95#define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C)
97#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260) 96#define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260)
98#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264) 97#define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264)
99#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270) 98#define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270)
100#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274) 99#define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274)
101#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C) 100#define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C)
102#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284) 101#define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284)
103#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C) 102#define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C)
104#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294) 103#define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294)
105#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C) 104#define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C)
106#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304) 105#define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304)
107#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C) 106#define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C)
108 #define SPEAR1340_RTC_CLK_ENB 31 107 #define SPEAR1340_RTC_CLK_ENB 31
109 #define SPEAR1340_ADC_CLK_ENB 30 108 #define SPEAR1340_ADC_CLK_ENB 30
110 #define SPEAR1340_C3_CLK_ENB 29 109 #define SPEAR1340_C3_CLK_ENB 29
@@ -133,7 +132,7 @@
133 #define SPEAR1340_SYSROM_CLK_ENB 1 132 #define SPEAR1340_SYSROM_CLK_ENB 1
134 #define SPEAR1340_BUS_CLK_ENB 0 133 #define SPEAR1340_BUS_CLK_ENB 0
135 134
136#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310) 135#define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310)
137 #define SPEAR1340_THSENS_CLK_ENB 8 136 #define SPEAR1340_THSENS_CLK_ENB 8
138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7 137 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
139 #define SPEAR1340_ACP_CLK_ENB 6 138 #define SPEAR1340_ACP_CLK_ENB 6
@@ -144,7 +143,7 @@
144 #define SPEAR1340_DDR_CORE_CLK_ENB 1 143 #define SPEAR1340_DDR_CORE_CLK_ENB 1
145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0 144 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
146 145
147#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314) 146#define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314)
148 #define SPEAR1340_PLGPIO_CLK_ENB 18 147 #define SPEAR1340_PLGPIO_CLK_ENB 18
149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16 148 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15 149 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
@@ -441,7 +440,7 @@ static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
441static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", 440static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
442 "pll2_clk", }; 441 "pll2_clk", };
443 442
444void __init spear1340_clk_init(void) 443void __init spear1340_clk_init(void __iomem *misc_base)
445{ 444{
446 struct clk *clk, *clk1; 445 struct clk *clk, *clk1;
447 446
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 33d3ac588da7..f9ec43fd1320 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -15,21 +15,20 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/of_platform.h> 16#include <linux/of_platform.h>
17#include <linux/spinlock_types.h> 17#include <linux/spinlock_types.h>
18#include <mach/misc_regs.h>
19#include "clk.h" 18#include "clk.h"
20 19
21static DEFINE_SPINLOCK(_lock); 20static DEFINE_SPINLOCK(_lock);
22 21
23#define PLL1_CTR (MISC_BASE + 0x008) 22#define PLL1_CTR (misc_base + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C) 23#define PLL1_FRQ (misc_base + 0x00C)
25#define PLL2_CTR (MISC_BASE + 0x014) 24#define PLL2_CTR (misc_base + 0x014)
26#define PLL2_FRQ (MISC_BASE + 0x018) 25#define PLL2_FRQ (misc_base + 0x018)
27#define PLL_CLK_CFG (MISC_BASE + 0x020) 26#define PLL_CLK_CFG (misc_base + 0x020)
28 /* PLL_CLK_CFG register masks */ 27 /* PLL_CLK_CFG register masks */
29 #define MCTR_CLK_SHIFT 28 28 #define MCTR_CLK_SHIFT 28
30 #define MCTR_CLK_MASK 3 29 #define MCTR_CLK_MASK 3
31 30
32#define CORE_CLK_CFG (MISC_BASE + 0x024) 31#define CORE_CLK_CFG (misc_base + 0x024)
33 /* CORE CLK CFG register masks */ 32 /* CORE CLK CFG register masks */
34 #define GEN_SYNTH2_3_CLK_SHIFT 18 33 #define GEN_SYNTH2_3_CLK_SHIFT 18
35 #define GEN_SYNTH2_3_CLK_MASK 1 34 #define GEN_SYNTH2_3_CLK_MASK 1
@@ -39,7 +38,7 @@ static DEFINE_SPINLOCK(_lock);
39 #define PCLK_RATIO_SHIFT 8 38 #define PCLK_RATIO_SHIFT 8
40 #define PCLK_RATIO_MASK 2 39 #define PCLK_RATIO_MASK 2
41 40
42#define PERIP_CLK_CFG (MISC_BASE + 0x028) 41#define PERIP_CLK_CFG (misc_base + 0x028)
43 /* PERIP_CLK_CFG register masks */ 42 /* PERIP_CLK_CFG register masks */
44 #define UART_CLK_SHIFT 4 43 #define UART_CLK_SHIFT 4
45 #define UART_CLK_MASK 1 44 #define UART_CLK_MASK 1
@@ -50,7 +49,7 @@ static DEFINE_SPINLOCK(_lock);
50 #define GPT2_CLK_SHIFT 12 49 #define GPT2_CLK_SHIFT 12
51 #define GPT_CLK_MASK 1 50 #define GPT_CLK_MASK 1
52 51
53#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) 52#define PERIP1_CLK_ENB (misc_base + 0x02C)
54 /* PERIP1_CLK_ENB register masks */ 53 /* PERIP1_CLK_ENB register masks */
55 #define UART_CLK_ENB 3 54 #define UART_CLK_ENB 3
56 #define SSP_CLK_ENB 5 55 #define SSP_CLK_ENB 5
@@ -69,7 +68,7 @@ static DEFINE_SPINLOCK(_lock);
69 #define USBH_CLK_ENB 25 68 #define USBH_CLK_ENB 25
70 #define C3_CLK_ENB 31 69 #define C3_CLK_ENB 31
71 70
72#define RAS_CLK_ENB (MISC_BASE + 0x034) 71#define RAS_CLK_ENB (misc_base + 0x034)
73 #define RAS_AHB_CLK_ENB 0 72 #define RAS_AHB_CLK_ENB 0
74 #define RAS_PLL1_CLK_ENB 1 73 #define RAS_PLL1_CLK_ENB 1
75 #define RAS_APB_CLK_ENB 2 74 #define RAS_APB_CLK_ENB 2
@@ -82,20 +81,20 @@ static DEFINE_SPINLOCK(_lock);
82 #define RAS_SYNT2_CLK_ENB 10 81 #define RAS_SYNT2_CLK_ENB 10
83 #define RAS_SYNT3_CLK_ENB 11 82 #define RAS_SYNT3_CLK_ENB 11
84 83
85#define PRSC0_CLK_CFG (MISC_BASE + 0x044) 84#define PRSC0_CLK_CFG (misc_base + 0x044)
86#define PRSC1_CLK_CFG (MISC_BASE + 0x048) 85#define PRSC1_CLK_CFG (misc_base + 0x048)
87#define PRSC2_CLK_CFG (MISC_BASE + 0x04C) 86#define PRSC2_CLK_CFG (misc_base + 0x04C)
88#define AMEM_CLK_CFG (MISC_BASE + 0x050) 87#define AMEM_CLK_CFG (misc_base + 0x050)
89 #define AMEM_CLK_ENB 0 88 #define AMEM_CLK_ENB 0
90 89
91#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) 90#define CLCD_CLK_SYNT (misc_base + 0x05C)
92#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) 91#define FIRDA_CLK_SYNT (misc_base + 0x060)
93#define UART_CLK_SYNT (MISC_BASE + 0x064) 92#define UART_CLK_SYNT (misc_base + 0x064)
94#define GMAC_CLK_SYNT (MISC_BASE + 0x068) 93#define GMAC_CLK_SYNT (misc_base + 0x068)
95#define GEN0_CLK_SYNT (MISC_BASE + 0x06C) 94#define GEN0_CLK_SYNT (misc_base + 0x06C)
96#define GEN1_CLK_SYNT (MISC_BASE + 0x070) 95#define GEN1_CLK_SYNT (misc_base + 0x070)
97#define GEN2_CLK_SYNT (MISC_BASE + 0x074) 96#define GEN2_CLK_SYNT (misc_base + 0x074)
98#define GEN3_CLK_SYNT (MISC_BASE + 0x078) 97#define GEN3_CLK_SYNT (misc_base + 0x078)
99 98
100/* pll rate configuration table, in ascending order of rates */ 99/* pll rate configuration table, in ascending order of rates */
101static struct pll_rate_tbl pll_rtbl[] = { 100static struct pll_rate_tbl pll_rtbl[] = {
@@ -211,6 +210,17 @@ static inline void spear310_clk_init(void) { }
211 210
212/* array of all spear 320 clock lookups */ 211/* array of all spear 320 clock lookups */
213#ifdef CONFIG_MACH_SPEAR320 212#ifdef CONFIG_MACH_SPEAR320
213
214#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
215#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
216
217 #define SPEAR320_UARTX_PCLK_MASK 0x1
218 #define SPEAR320_UART2_PCLK_SHIFT 8
219 #define SPEAR320_UART3_PCLK_SHIFT 9
220 #define SPEAR320_UART4_PCLK_SHIFT 10
221 #define SPEAR320_UART5_PCLK_SHIFT 11
222 #define SPEAR320_UART6_PCLK_SHIFT 12
223 #define SPEAR320_RS485_PCLK_SHIFT 13
214 #define SMII_PCLK_SHIFT 18 224 #define SMII_PCLK_SHIFT 18
215 #define SMII_PCLK_MASK 2 225 #define SMII_PCLK_MASK 2
216 #define SMII_PCLK_VAL_PAD 0x0 226 #define SMII_PCLK_VAL_PAD 0x0
@@ -235,7 +245,7 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
235 "ras_syn0_gclk", }; 245 "ras_syn0_gclk", };
236static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; 246static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
237 247
238static void __init spear320_clk_init(void) 248static void __init spear320_clk_init(void __iomem *soc_config_base)
239{ 249{
240 struct clk *clk; 250 struct clk *clk;
241 251
@@ -362,7 +372,7 @@ static void __init spear320_clk_init(void)
362static inline void spear320_clk_init(void) { } 372static inline void spear320_clk_init(void) { }
363#endif 373#endif
364 374
365void __init spear3xx_clk_init(void) 375void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
366{ 376{
367 struct clk *clk, *clk1; 377 struct clk *clk, *clk1;
368 378
@@ -634,5 +644,5 @@ void __init spear3xx_clk_init(void)
634 else if (of_machine_is_compatible("st,spear310")) 644 else if (of_machine_is_compatible("st,spear310"))
635 spear310_clk_init(); 645 spear310_clk_init();
636 else if (of_machine_is_compatible("st,spear320")) 646 else if (of_machine_is_compatible("st,spear320"))
637 spear320_clk_init(); 647 spear320_clk_init(soc_config_base);
638} 648}
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index e862a333ad30..9406f2426d64 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -13,28 +13,27 @@
13#include <linux/clkdev.h> 13#include <linux/clkdev.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/spinlock_types.h> 15#include <linux/spinlock_types.h>
16#include <mach/misc_regs.h>
17#include "clk.h" 16#include "clk.h"
18 17
19static DEFINE_SPINLOCK(_lock); 18static DEFINE_SPINLOCK(_lock);
20 19
21#define PLL1_CTR (MISC_BASE + 0x008) 20#define PLL1_CTR (misc_base + 0x008)
22#define PLL1_FRQ (MISC_BASE + 0x00C) 21#define PLL1_FRQ (misc_base + 0x00C)
23#define PLL2_CTR (MISC_BASE + 0x014) 22#define PLL2_CTR (misc_base + 0x014)
24#define PLL2_FRQ (MISC_BASE + 0x018) 23#define PLL2_FRQ (misc_base + 0x018)
25#define PLL_CLK_CFG (MISC_BASE + 0x020) 24#define PLL_CLK_CFG (misc_base + 0x020)
26 /* PLL_CLK_CFG register masks */ 25 /* PLL_CLK_CFG register masks */
27 #define MCTR_CLK_SHIFT 28 26 #define MCTR_CLK_SHIFT 28
28 #define MCTR_CLK_MASK 3 27 #define MCTR_CLK_MASK 3
29 28
30#define CORE_CLK_CFG (MISC_BASE + 0x024) 29#define CORE_CLK_CFG (misc_base + 0x024)
31 /* CORE CLK CFG register masks */ 30 /* CORE CLK CFG register masks */
32 #define HCLK_RATIO_SHIFT 10 31 #define HCLK_RATIO_SHIFT 10
33 #define HCLK_RATIO_MASK 2 32 #define HCLK_RATIO_MASK 2
34 #define PCLK_RATIO_SHIFT 8 33 #define PCLK_RATIO_SHIFT 8
35 #define PCLK_RATIO_MASK 2 34 #define PCLK_RATIO_MASK 2
36 35
37#define PERIP_CLK_CFG (MISC_BASE + 0x028) 36#define PERIP_CLK_CFG (misc_base + 0x028)
38 /* PERIP_CLK_CFG register masks */ 37 /* PERIP_CLK_CFG register masks */
39 #define CLCD_CLK_SHIFT 2 38 #define CLCD_CLK_SHIFT 2
40 #define CLCD_CLK_MASK 2 39 #define CLCD_CLK_MASK 2
@@ -48,7 +47,7 @@ static DEFINE_SPINLOCK(_lock);
48 #define GPT3_CLK_SHIFT 12 47 #define GPT3_CLK_SHIFT 12
49 #define GPT_CLK_MASK 1 48 #define GPT_CLK_MASK 1
50 49
51#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) 50#define PERIP1_CLK_ENB (misc_base + 0x02C)
52 /* PERIP1_CLK_ENB register masks */ 51 /* PERIP1_CLK_ENB register masks */
53 #define UART0_CLK_ENB 3 52 #define UART0_CLK_ENB 3
54 #define UART1_CLK_ENB 4 53 #define UART1_CLK_ENB 4
@@ -74,13 +73,13 @@ static DEFINE_SPINLOCK(_lock);
74 #define USBH0_CLK_ENB 25 73 #define USBH0_CLK_ENB 25
75 #define USBH1_CLK_ENB 26 74 #define USBH1_CLK_ENB 26
76 75
77#define PRSC0_CLK_CFG (MISC_BASE + 0x044) 76#define PRSC0_CLK_CFG (misc_base + 0x044)
78#define PRSC1_CLK_CFG (MISC_BASE + 0x048) 77#define PRSC1_CLK_CFG (misc_base + 0x048)
79#define PRSC2_CLK_CFG (MISC_BASE + 0x04C) 78#define PRSC2_CLK_CFG (misc_base + 0x04C)
80 79
81#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) 80#define CLCD_CLK_SYNT (misc_base + 0x05C)
82#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) 81#define FIRDA_CLK_SYNT (misc_base + 0x060)
83#define UART_CLK_SYNT (MISC_BASE + 0x064) 82#define UART_CLK_SYNT (misc_base + 0x064)
84 83
85/* vco rate configuration table, in ascending order of rates */ 84/* vco rate configuration table, in ascending order of rates */
86static struct pll_rate_tbl pll_rtbl[] = { 85static struct pll_rate_tbl pll_rtbl[] = {
@@ -115,7 +114,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = {
115 {.mscale = 1, .nscale = 0}, /* 83 MHz */ 114 {.mscale = 1, .nscale = 0}, /* 83 MHz */
116}; 115};
117 116
118void __init spear6xx_clk_init(void) 117void __init spear6xx_clk_init(void __iomem *misc_base)
119{ 118{
120 struct clk *clk, *clk1; 119 struct clk *clk, *clk1;
121 120
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 03:32:14 -0500