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authorSylwester Nawrocki <s.nawrocki@samsung.com>2015-05-27 09:04:43 -0400
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-02-25 06:09:42 -0500
commita665d30f1f2575df864e706dc8209458b8f4cf88 (patch)
tree074c49afcbaa57622eb9791dd0cd77841e745ba8 /drivers/clk/samsung
parent3c30e382ae55f6e124f6b3d9701e200dd33fdc84 (diff)
clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
This corrects assignment of bit offsets of the MUX_SEL_CAM04 register to the respective mux clocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 982abb765110..cf096f932ae7 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -4753,21 +4753,21 @@ static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
4753 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", 4753 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4754 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), 4754 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4755 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", 4755 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4756 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1), 4756 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4757 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", 4757 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4758 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1), 4758 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4759 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", 4759 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4760 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1), 4760 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4761 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", 4761 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4762 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1), 4762 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4763 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, 4763 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4764 "mout_sclk_pixelasync_lite_c_init_b", 4764 "mout_sclk_pixelasync_lite_c_init_b",
4765 mout_sclk_pixelasync_lite_c_init_b_p, 4765 mout_sclk_pixelasync_lite_c_init_b_p,
4766 MUX_SEL_CAM04, 24, 1), 4766 MUX_SEL_CAM04, 4, 1),
4767 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, 4767 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4768 "mout_sclk_pixelasync_lite_c_init_a", 4768 "mout_sclk_pixelasync_lite_c_init_a",
4769 mout_sclk_pixelasync_lite_c_init_a_p, 4769 mout_sclk_pixelasync_lite_c_init_a_p,
4770 MUX_SEL_CAM04, 24, 1), 4770 MUX_SEL_CAM04, 0, 1),
4771}; 4771};
4772 4772
4773static struct samsung_div_clock cam0_div_clks[] __initdata = { 4773static struct samsung_div_clock cam0_div_clks[] __initdata = {