diff options
author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2014-02-14 15:15:00 -0500 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2014-02-16 21:33:54 -0500 |
commit | 5d836c58f2e690517ee6fbea4b19f1ad3677c1a5 (patch) | |
tree | 98572c2a6f6f792b7dfc0d0b9ba8b8d01c626a6c /drivers/clk/mvebu | |
parent | 38dbfb59d1175ef458d006556061adeaa8751b72 (diff) |
clk: mvebu: do not copy the contents of clk_corediv_desc
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'drivers/clk/mvebu')
-rw-r--r-- | drivers/clk/mvebu/clk-corediv.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 7162615bcdcd..fb79375a535e 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c | |||
@@ -31,13 +31,13 @@ struct clk_corediv_desc { | |||
31 | struct clk_corediv { | 31 | struct clk_corediv { |
32 | struct clk_hw hw; | 32 | struct clk_hw hw; |
33 | void __iomem *reg; | 33 | void __iomem *reg; |
34 | struct clk_corediv_desc desc; | 34 | const struct clk_corediv_desc *desc; |
35 | spinlock_t lock; | 35 | spinlock_t lock; |
36 | }; | 36 | }; |
37 | 37 | ||
38 | static struct clk_onecell_data clk_data; | 38 | static struct clk_onecell_data clk_data; |
39 | 39 | ||
40 | static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = { | 40 | static const struct clk_corediv_desc mvebu_corediv_desc[] = { |
41 | { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */ | 41 | { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */ |
42 | }; | 42 | }; |
43 | 43 | ||
@@ -46,7 +46,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = { | |||
46 | static int clk_corediv_is_enabled(struct clk_hw *hwclk) | 46 | static int clk_corediv_is_enabled(struct clk_hw *hwclk) |
47 | { | 47 | { |
48 | struct clk_corediv *corediv = to_corediv_clk(hwclk); | 48 | struct clk_corediv *corediv = to_corediv_clk(hwclk); |
49 | struct clk_corediv_desc *desc = &corediv->desc; | 49 | const struct clk_corediv_desc *desc = corediv->desc; |
50 | u32 enable_mask = BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET; | 50 | u32 enable_mask = BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET; |
51 | 51 | ||
52 | return !!(readl(corediv->reg) & enable_mask); | 52 | return !!(readl(corediv->reg) & enable_mask); |
@@ -55,7 +55,7 @@ static int clk_corediv_is_enabled(struct clk_hw *hwclk) | |||
55 | static int clk_corediv_enable(struct clk_hw *hwclk) | 55 | static int clk_corediv_enable(struct clk_hw *hwclk) |
56 | { | 56 | { |
57 | struct clk_corediv *corediv = to_corediv_clk(hwclk); | 57 | struct clk_corediv *corediv = to_corediv_clk(hwclk); |
58 | struct clk_corediv_desc *desc = &corediv->desc; | 58 | const struct clk_corediv_desc *desc = corediv->desc; |
59 | unsigned long flags = 0; | 59 | unsigned long flags = 0; |
60 | u32 reg; | 60 | u32 reg; |
61 | 61 | ||
@@ -73,7 +73,7 @@ static int clk_corediv_enable(struct clk_hw *hwclk) | |||
73 | static void clk_corediv_disable(struct clk_hw *hwclk) | 73 | static void clk_corediv_disable(struct clk_hw *hwclk) |
74 | { | 74 | { |
75 | struct clk_corediv *corediv = to_corediv_clk(hwclk); | 75 | struct clk_corediv *corediv = to_corediv_clk(hwclk); |
76 | struct clk_corediv_desc *desc = &corediv->desc; | 76 | const struct clk_corediv_desc *desc = corediv->desc; |
77 | unsigned long flags = 0; | 77 | unsigned long flags = 0; |
78 | u32 reg; | 78 | u32 reg; |
79 | 79 | ||
@@ -90,7 +90,7 @@ static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk, | |||
90 | unsigned long parent_rate) | 90 | unsigned long parent_rate) |
91 | { | 91 | { |
92 | struct clk_corediv *corediv = to_corediv_clk(hwclk); | 92 | struct clk_corediv *corediv = to_corediv_clk(hwclk); |
93 | struct clk_corediv_desc *desc = &corediv->desc; | 93 | const struct clk_corediv_desc *desc = corediv->desc; |
94 | u32 reg, div; | 94 | u32 reg, div; |
95 | 95 | ||
96 | reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); | 96 | reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); |
@@ -117,7 +117,7 @@ static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate, | |||
117 | unsigned long parent_rate) | 117 | unsigned long parent_rate) |
118 | { | 118 | { |
119 | struct clk_corediv *corediv = to_corediv_clk(hwclk); | 119 | struct clk_corediv *corediv = to_corediv_clk(hwclk); |
120 | struct clk_corediv_desc *desc = &corediv->desc; | 120 | const struct clk_corediv_desc *desc = corediv->desc; |
121 | unsigned long flags = 0; | 121 | unsigned long flags = 0; |
122 | u32 reg, div; | 122 | u32 reg, div; |
123 | 123 | ||
@@ -202,7 +202,7 @@ static void __init mvebu_corediv_clk_init(struct device_node *node) | |||
202 | init.ops = &corediv_ops; | 202 | init.ops = &corediv_ops; |
203 | init.flags = 0; | 203 | init.flags = 0; |
204 | 204 | ||
205 | corediv[i].desc = mvebu_corediv_desc[i]; | 205 | corediv[i].desc = mvebu_corediv_desc + i; |
206 | corediv[i].reg = base; | 206 | corediv[i].reg = base; |
207 | corediv[i].hw.init = &init; | 207 | corediv[i].hw.init = &init; |
208 | 208 | ||