clk: mvebu: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

2 files changed, 6 insertions, 8 deletions

diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index daa6ebdac131..66be2e0c82b4 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -137,8 +137,8 @@ void __init mvebu_coreclk_setup(struct device_node *np,
         of_property_read_string_index(np, "clock-output-names", 0,
                                       &tclk_name);
         rate = desc->get_tclk_freq(base);
-        clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
-                                                   CLK_IS_ROOT, rate);
+        clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 0,
+                                                   rate);
         WARN_ON(IS_ERR(clk_data.clks[0]));
 
         /* Register CPU clock */
@@ -150,8 +150,8 @@ void __init mvebu_coreclk_setup(struct device_node *np,
                 && desc->is_sscg_enabled(base))
                 rate = desc->fix_sscg_deviation(rate);
 
-        clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
-                                                   CLK_IS_ROOT, rate);
+        clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 0,
+                                                   rate);
         WARN_ON(IS_ERR(clk_data.clks[1]));
 
         /* Register fixed-factor clocks derived from CPU clock */
@@ -174,8 +174,7 @@ void __init mvebu_coreclk_setup(struct device_node *np,
                                               2 + desc->num_ratios, &name);
                 rate = desc->get_refclk_freq(base);
                 clk_data.clks[2 + desc->num_ratios] =
-                        clk_register_fixed_rate(NULL, name, NULL,
-                                                CLK_IS_ROOT, rate);
+                        clk_register_fixed_rate(NULL, name, NULL, 0, rate);
                 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
         }
 
diff --git a/drivers/clk/mvebu/dove-divider.c b/drivers/clk/mvebu/dove-divider.c
index 3e0b52daa35f..4091f3cfee19 100644
--- a/drivers/clk/mvebu/dove-divider.c
+++ b/drivers/clk/mvebu/dove-divider.c
@@ -225,8 +225,7 @@ static int dove_divider_init(struct device *dev, void __iomem *base,
          * Create the core PLL clock.  We treat this as a fixed rate
          * clock as we don't know any better, and documentation is sparse.
          */
-        clk = clk_register_fixed_rate(dev, core_pll[0], NULL, CLK_IS_ROOT,
-                                      2000000000UL);
+        clk = clk_register_fixed_rate(dev, core_pll[0], NULL, 0, 2000000000UL);
         if (IS_ERR(clk))
                 return PTR_ERR(clk);