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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2013-07-26 09:17:51 -0400
committerJason Cooper <jason@lakedaemon.net>2013-08-06 10:10:49 -0400
commited843a7d62b99cf4f853c8f9cdee06ada4ba3630 (patch)
tree280e03c4da8bfe05779c88db7af4578444356f8e /drivers/bus/mvebu-mbus.c
parent124e5427f59877cd9dde5fa2ea90c413765e77ef (diff)
bus: mvebu-mbus: Remove name -> target, attribute mapping tables
This tables were used together with the name-based MBus window creation API. Since that's has been removed, we can also remove the tables. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'drivers/bus/mvebu-mbus.c')
-rw-r--r--drivers/bus/mvebu-mbus.c150
1 files changed, 7 insertions, 143 deletions
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index b4a738236987..c182ef571c35 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -97,33 +97,6 @@
97 97
98#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4) 98#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
99 99
100struct mvebu_mbus_mapping {
101 const char *name;
102 u8 target;
103 u8 attr;
104 u8 attrmask;
105};
106
107/*
108 * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
109 * allow to get the real attribute value, discarding the special bits
110 * used to select a PCI MEM region or a PCI WA region. This allows the
111 * debugfs code to reverse-match the name of a device from its
112 * target/attr values.
113 *
114 * For all devices except PCI, all bits of 'attr' must be
115 * considered. For most SoCs, only bit 3 should be ignored (it allows
116 * to select between PCI MEM and PCI I/O). On Orion5x however, there
117 * is the special bit 5 to select a PCI WA region.
118 */
119#define MAPDEF_NOMASK 0xff
120#define MAPDEF_PCIMASK 0xf7
121#define MAPDEF_ORIONPCIMASK 0xd7
122
123/* Macro used to define one mvebu_mbus_mapping entry */
124#define MAPDEF(__n, __t, __a, __m) \
125 { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
126
127struct mvebu_mbus_state; 100struct mvebu_mbus_state;
128 101
129struct mvebu_mbus_soc_data { 102struct mvebu_mbus_soc_data {
@@ -133,7 +106,6 @@ struct mvebu_mbus_soc_data {
133 void (*setup_cpu_target)(struct mvebu_mbus_state *s); 106 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
134 int (*show_cpu_target)(struct mvebu_mbus_state *s, 107 int (*show_cpu_target)(struct mvebu_mbus_state *s,
135 struct seq_file *seq, void *v); 108 struct seq_file *seq, void *v);
136 const struct mvebu_mbus_mapping *map;
137}; 109};
138 110
139struct mvebu_mbus_state { 111struct mvebu_mbus_state {
@@ -430,8 +402,7 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
430 u64 wbase, wremap; 402 u64 wbase, wremap;
431 u32 wsize; 403 u32 wsize;
432 u8 wtarget, wattr; 404 u8 wtarget, wattr;
433 int enabled, i; 405 int enabled;
434 const char *name;
435 406
436 mvebu_mbus_read_window(mbus, win, 407 mvebu_mbus_read_window(mbus, win,
437 &enabled, &wbase, &wsize, 408 &enabled, &wbase, &wsize,
@@ -442,18 +413,9 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
442 continue; 413 continue;
443 } 414 }
444 415
445 416 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
446 for (i = 0; mbus->soc->map[i].name; i++)
447 if (mbus->soc->map[i].target == wtarget &&
448 mbus->soc->map[i].attr ==
449 (wattr & mbus->soc->map[i].attrmask))
450 break;
451
452 name = mbus->soc->map[i].name ?: "unknown";
453
454 seq_printf(seq, "[%02d] %016llx - %016llx : %s",
455 win, (unsigned long long)wbase, 417 win, (unsigned long long)wbase,
456 (unsigned long long)(wbase + wsize), name); 418 (unsigned long long)(wbase + wsize), wtarget, wattr);
457 419
458 if (win < mbus->soc->num_remappable_wins) { 420 if (win < mbus->soc->num_remappable_wins) {
459 seq_printf(seq, " (remap %016llx)\n", 421 seq_printf(seq, " (remap %016llx)\n",
@@ -578,45 +540,12 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
578 mvebu_mbus_dram_info.num_cs = cs; 540 mvebu_mbus_dram_info.num_cs = cs;
579} 541}
580 542
581static const struct mvebu_mbus_mapping armada_370_map[] = {
582 MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
583 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
584 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
585 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
586 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
587 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
588 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
589 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
590 {},
591};
592
593static const struct mvebu_mbus_soc_data armada_370_mbus_data = { 543static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
594 .num_wins = 20, 544 .num_wins = 20,
595 .num_remappable_wins = 8, 545 .num_remappable_wins = 8,
596 .win_cfg_offset = armada_370_xp_mbus_win_offset, 546 .win_cfg_offset = armada_370_xp_mbus_win_offset,
597 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 547 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
598 .show_cpu_target = mvebu_sdram_debug_show_orion, 548 .show_cpu_target = mvebu_sdram_debug_show_orion,
599 .map = armada_370_map,
600};
601
602static const struct mvebu_mbus_mapping armada_xp_map[] = {
603 MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
604 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
605 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
606 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
607 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
608 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
609 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
610 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
611 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
612 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
613 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
614 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
615 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
616 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
617 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
618 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
619 {},
620}; 549};
621 550
622static const struct mvebu_mbus_soc_data armada_xp_mbus_data = { 551static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
@@ -625,15 +554,6 @@ static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
625 .win_cfg_offset = armada_370_xp_mbus_win_offset, 554 .win_cfg_offset = armada_370_xp_mbus_win_offset,
626 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 555 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
627 .show_cpu_target = mvebu_sdram_debug_show_orion, 556 .show_cpu_target = mvebu_sdram_debug_show_orion,
628 .map = armada_xp_map,
629};
630
631static const struct mvebu_mbus_mapping kirkwood_map[] = {
632 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
633 MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
634 MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
635 MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
636 {},
637}; 557};
638 558
639static const struct mvebu_mbus_soc_data kirkwood_mbus_data = { 559static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
@@ -642,16 +562,6 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
642 .win_cfg_offset = orion_mbus_win_offset, 562 .win_cfg_offset = orion_mbus_win_offset,
643 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 563 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
644 .show_cpu_target = mvebu_sdram_debug_show_orion, 564 .show_cpu_target = mvebu_sdram_debug_show_orion,
645 .map = kirkwood_map,
646};
647
648static const struct mvebu_mbus_mapping dove_map[] = {
649 MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
650 MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
651 MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
652 MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
653 MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
654 {},
655}; 565};
656 566
657static const struct mvebu_mbus_soc_data dove_mbus_data = { 567static const struct mvebu_mbus_soc_data dove_mbus_data = {
@@ -660,18 +570,6 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
660 .win_cfg_offset = orion_mbus_win_offset, 570 .win_cfg_offset = orion_mbus_win_offset,
661 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target, 571 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
662 .show_cpu_target = mvebu_sdram_debug_show_dove, 572 .show_cpu_target = mvebu_sdram_debug_show_dove,
663 .map = dove_map,
664};
665
666static const struct mvebu_mbus_mapping orion5x_map[] = {
667 MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
668 MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
669 MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
670 MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
671 MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
672 MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
673 MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
674 {},
675}; 573};
676 574
677/* 575/*
@@ -684,7 +582,6 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
684 .win_cfg_offset = orion_mbus_win_offset, 582 .win_cfg_offset = orion_mbus_win_offset,
685 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 583 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
686 .show_cpu_target = mvebu_sdram_debug_show_orion, 584 .show_cpu_target = mvebu_sdram_debug_show_orion,
687 .map = orion5x_map,
688}; 585};
689 586
690static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = { 587static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
@@ -693,21 +590,6 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
693 .win_cfg_offset = orion_mbus_win_offset, 590 .win_cfg_offset = orion_mbus_win_offset,
694 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 591 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
695 .show_cpu_target = mvebu_sdram_debug_show_orion, 592 .show_cpu_target = mvebu_sdram_debug_show_orion,
696 .map = orion5x_map,
697};
698
699static const struct mvebu_mbus_mapping mv78xx0_map[] = {
700 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
701 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
702 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
703 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
704 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
705 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
706 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
707 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
708 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
709 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
710 {},
711}; 593};
712 594
713static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = { 595static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
@@ -716,7 +598,6 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
716 .win_cfg_offset = mv78xx0_mbus_win_offset, 598 .win_cfg_offset = mv78xx0_mbus_win_offset,
717 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 599 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
718 .show_cpu_target = mvebu_sdram_debug_show_orion, 600 .show_cpu_target = mvebu_sdram_debug_show_orion,
719 .map = mv78xx0_map,
720}; 601};
721 602
722/* 603/*
@@ -895,33 +776,16 @@ static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
895 u32 base, u32 size, 776 u32 base, u32 size,
896 u8 target, u8 attr) 777 u8 target, u8 attr)
897{ 778{
898 const struct mvebu_mbus_mapping *map = mbus->soc->map;
899 const char *name;
900 int i;
901
902 /* Search for a suitable window in the existing mappings */
903 for (i = 0; map[i].name; i++)
904 if (map[i].target == target &&
905 map[i].attr == (attr & map[i].attrmask))
906 break;
907
908 name = map[i].name;
909 if (!name) {
910 pr_err("window 0x%x:0x%x is unknown, skipping\n",
911 target, attr);
912 return -EINVAL;
913 }
914
915 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) { 779 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
916 pr_err("cannot add window '%s', conflicts with another window\n", 780 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
917 name); 781 target, attr);
918 return -EBUSY; 782 return -EBUSY;
919 } 783 }
920 784
921 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP, 785 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
922 target, attr)) { 786 target, attr)) {
923 pr_err("cannot add window '%s', too many windows\n", 787 pr_err("cannot add window '%04x:%04x', too many windows\n",
924 name); 788 target, attr);
925 return -ENOMEM; 789 return -ENOMEM;
926 } 790 }
927 return 0; 791 return 0;