aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2015-05-09 19:13:38 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-05-09 19:13:38 -0400
commit8f59ae0643b2057ad996ab23488e9be1ba2564f4 (patch)
treec5bc7c71d551455cd3f5d22726ab7ffcef8aff5e /arch
parent51dfcb076d1e1ce7006aa272cb7c4514740c7e47 (diff)
parentc9d862c48c48883a4327ae82f4a6de1eef928d60 (diff)
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann: "A few patches have come up since the merge window. The largest one is a rewrite of the PXA lubbock/mainstone IRQ handling. This was already broken in 2011 by a change to the GPIO code and only noticed now. The other changes contained here are: MAINTAINERS file updates: - Ray Jui and Scott Branden are now co-maintainers for some of the mach-bcm chips, while Christian Daudt and Marc Carino have stepped down. - Andrew Victor is no longer maintaining at91. Instead, Alexandre Belloni now becomes an official maintainer, after having done a bulk of the work for a while. - Baruch Siach, who added the mach-digicolor platform in 4.1 is now listed as maintainer - The git URL for mach-socfpga has changed Bug fixes: - Three bug fixes for new rockchip rk3288 code - A regression fix to make SD card support work on certain ux500 boards - multiple smaller dts fixes for imx, omap, mvebu, and shmobile - a regression fiix for omap3 power consumption - a fix for regression in the ARM CCI bus driver Configuration changes: - more imx platforms are now enabled in multi_v7_defconfig" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) MAINTAINERS: add Conexant Digicolor machines entry MAINTAINERS: socfpga: update the git repo for SoCFPGA ARM: multi_v7_defconfig: Select more FSL SoCs MAINTAINERS: replace an AT91 maintainer drivers: CCI: fix used_mask init in validate_group() bus: omap_l3_noc: Fix master id address decoding for OMAP5 bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instance ARM: dts: dra7: Fix efuse register size for ABB ARM: dts: am57xx-beagle-x15: Switch GPIO fan number ARM: dts: am57xx-beagle-x15: Switch UART mux pins ARM: dts: am437x-sk: reduce col-scan-delay-us ARM: dts: am437x-sk: fix for new newhaven display module revision ARM: dts: am57xx-beagle-x15: Fix RTC aliases ARM: dts: am57xx-beagle-x15: Fix IRQ type for mcp7941x ARM: dts: omap3: Add #iommu-cells to isp and iva iommu ARM: omap2plus_defconfig: Enable EXTCON_USB_GPIO ARM: dts: OMAP3-N900: Add microphone bias voltages ARM: OMAP2+: Fix omap off idle power consumption creeping up MAINTAINERS: Update brcmstb entry MAINTAINERS: Remove Christian Daudt for mach-bcm ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts4
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts11
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts4
-rw-r--r--arch/arm/boot/dts/dra7.dtsi10
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts4
-rw-r--r--arch/arm/boot/dts/imx25.dtsi1
-rw-r--r--arch/arm/boot/dts/imx28.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts4
-rw-r--r--arch/arm/boot/dts/omap3.dtsi2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi2
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts2
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi17
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi15
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts13
-rw-r--r--arch/arm/configs/multi_v7_defconfig3
-rw-r--r--arch/arm/configs/omap2plus_defconfig2
-rw-r--r--arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c2
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h1
-rw-r--r--arch/arm/mach-omap2/prm-regbits-44xx.h1
-rw-r--r--arch/arm/mach-omap2/vc.c12
-rw-r--r--arch/arm/mach-omap2/vc.h2
-rw-r--r--arch/arm/mach-omap2/vc3xxx_data.c1
-rw-r--r--arch/arm/mach-omap2/vc44xx_data.c1
-rw-r--r--arch/arm/mach-pxa/Kconfig9
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/include/mach/lubbock.h7
-rw-r--r--arch/arm/mach-pxa/include/mach/mainstone.h6
-rw-r--r--arch/arm/mach-pxa/lubbock.c108
-rw-r--r--arch/arm/mach-pxa/mainstone.c115
-rw-r--r--arch/arm/mach-pxa/pxa_cplds_irqs.c200
-rw-r--r--arch/arm/mach-rockchip/pm.c33
-rw-r--r--arch/arm/mach-rockchip/pm.h8
-rw-r--r--arch/arm/mach-rockchip/rockchip.c19
35 files changed, 415 insertions, 210 deletions
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 8ae29c955c11..c17097d2c167 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -49,7 +49,7 @@
49 pinctrl-0 = <&matrix_keypad_pins>; 49 pinctrl-0 = <&matrix_keypad_pins>;
50 50
51 debounce-delay-ms = <5>; 51 debounce-delay-ms = <5>;
52 col-scan-delay-us = <1500>; 52 col-scan-delay-us = <5>;
53 53
54 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ 54 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
55 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ 55 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
@@ -473,7 +473,7 @@
473 interrupt-parent = <&gpio0>; 473 interrupt-parent = <&gpio0>;
474 interrupts = <31 0>; 474 interrupts = <31 0>;
475 475
476 wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 476 reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
477 477
478 touchscreen-size-x = <480>; 478 touchscreen-size-x = <480>;
479 touchscreen-size-y = <272>; 479 touchscreen-size-y = <272>;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 15f198e4864d..7128fad991ac 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -18,6 +18,7 @@
18 aliases { 18 aliases {
19 rtc0 = &mcp_rtc; 19 rtc0 = &mcp_rtc;
20 rtc1 = &tps659038_rtc; 20 rtc1 = &tps659038_rtc;
21 rtc2 = &rtc;
21 }; 22 };
22 23
23 memory { 24 memory {
@@ -83,7 +84,7 @@
83 gpio_fan: gpio_fan { 84 gpio_fan: gpio_fan {
84 /* Based on 5v 500mA AFB02505HHB */ 85 /* Based on 5v 500mA AFB02505HHB */
85 compatible = "gpio-fan"; 86 compatible = "gpio-fan";
86 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>; 87 gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
87 gpio-fan,speed-map = <0 0>, 88 gpio-fan,speed-map = <0 0>,
88 <13000 1>; 89 <13000 1>;
89 #cooling-cells = <2>; 90 #cooling-cells = <2>;
@@ -130,8 +131,8 @@
130 131
131 uart3_pins_default: uart3_pins_default { 132 uart3_pins_default: uart3_pins_default {
132 pinctrl-single,pins = < 133 pinctrl-single,pins = <
133 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ 134 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
134 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ 135 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
135 >; 136 >;
136 }; 137 };
137 138
@@ -455,7 +456,7 @@
455 mcp_rtc: rtc@6f { 456 mcp_rtc: rtc@6f {
456 compatible = "microchip,mcp7941x"; 457 compatible = "microchip,mcp7941x";
457 reg = <0x6f>; 458 reg = <0x6f>;
458 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */ 459 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
459 460
460 pinctrl-names = "default"; 461 pinctrl-names = "default";
461 pinctrl-0 = <&mcp79410_pins_default>; 462 pinctrl-0 = <&mcp79410_pins_default>;
@@ -478,7 +479,7 @@
478&uart3 { 479&uart3 {
479 status = "okay"; 480 status = "okay";
480 interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 481 interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
481 <&dra7_pmx_core 0x248>; 482 <&dra7_pmx_core 0x3f8>;
482 483
483 pinctrl-names = "default"; 484 pinctrl-names = "default";
484 pinctrl-0 = <&uart3_pins_default>; 485 pinctrl-0 = <&uart3_pins_default>;
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index e3b08fb959e5..990e8a2100f0 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -105,6 +105,10 @@
105 }; 105 };
106 106
107 internal-regs { 107 internal-regs {
108 rtc@10300 {
109 /* No crystal connected to the internal RTC */
110 status = "disabled";
111 };
108 serial@12000 { 112 serial@12000 {
109 status = "okay"; 113 status = "okay";
110 }; 114 };
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5332b57b4950..f03a091cd076 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -911,7 +911,7 @@
911 ti,clock-cycles = <16>; 911 ti,clock-cycles = <16>;
912 912
913 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 913 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
914 <0x4ae06014 0x4>, <0x4a003b20 0x8>, 914 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
915 <0x4ae0c158 0x4>; 915 <0x4ae0c158 0x4>;
916 reg-names = "setup-address", "control-address", 916 reg-names = "setup-address", "control-address",
917 "int-address", "efuse-address", 917 "int-address", "efuse-address",
@@ -944,7 +944,7 @@
944 ti,clock-cycles = <16>; 944 ti,clock-cycles = <16>;
945 945
946 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 946 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
947 <0x4ae06010 0x4>, <0x4a0025cc 0x8>, 947 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
948 <0x4a002470 0x4>; 948 <0x4a002470 0x4>;
949 reg-names = "setup-address", "control-address", 949 reg-names = "setup-address", "control-address",
950 "int-address", "efuse-address", 950 "int-address", "efuse-address",
@@ -977,7 +977,7 @@
977 ti,clock-cycles = <16>; 977 ti,clock-cycles = <16>;
978 978
979 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 979 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
980 <0x4ae06010 0x4>, <0x4a0025e0 0x8>, 980 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
981 <0x4a00246c 0x4>; 981 <0x4a00246c 0x4>;
982 reg-names = "setup-address", "control-address", 982 reg-names = "setup-address", "control-address",
983 "int-address", "efuse-address", 983 "int-address", "efuse-address",
@@ -1010,7 +1010,7 @@
1010 ti,clock-cycles = <16>; 1010 ti,clock-cycles = <16>;
1011 1011
1012 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1012 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1013 <0x4ae06010 0x4>, <0x4a003b08 0x8>, 1013 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1014 <0x4ae0c154 0x4>; 1014 <0x4ae0c154 0x4>;
1015 reg-names = "setup-address", "control-address", 1015 reg-names = "setup-address", "control-address",
1016 "int-address", "efuse-address", 1016 "int-address", "efuse-address",
@@ -1203,7 +1203,7 @@
1203 status = "disabled"; 1203 status = "disabled";
1204 }; 1204 };
1205 1205
1206 rtc@48838000 { 1206 rtc: rtc@48838000 {
1207 compatible = "ti,am3352-rtc"; 1207 compatible = "ti,am3352-rtc";
1208 reg = <0x48838000 0x100>; 1208 reg = <0x48838000 0x100>;
1209 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1209 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 7e6eef2488e8..82045398bf1f 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15#include <dt-bindings/gpio/gpio.h>
15#include "imx23.dtsi" 16#include "imx23.dtsi"
16 17
17/ { 18/ {
@@ -93,6 +94,7 @@
93 94
94 ahb@80080000 { 95 ahb@80080000 {
95 usb0: usb@80080000 { 96 usb0: usb@80080000 {
97 dr_mode = "host";
96 vbus-supply = <&reg_usb0_vbus>; 98 vbus-supply = <&reg_usb0_vbus>;
97 status = "okay"; 99 status = "okay";
98 }; 100 };
@@ -122,7 +124,7 @@
122 124
123 user { 125 user {
124 label = "green"; 126 label = "green";
125 gpios = <&gpio2 1 1>; 127 gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
126 }; 128 };
127 }; 129 };
128}; 130};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index e4d3aecc4ed2..677f81d9dcd5 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -428,6 +428,7 @@
428 428
429 pwm4: pwm@53fc8000 { 429 pwm4: pwm@53fc8000 {
430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; 430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
431 #pwm-cells = <2>;
431 reg = <0x53fc8000 0x4000>; 432 reg = <0x53fc8000 0x4000>;
432 clocks = <&clks 108>, <&clks 52>; 433 clocks = <&clks 108>, <&clks 52>;
433 clock-names = "ipg", "per"; 434 clock-names = "ipg", "per";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 25e25f82fbae..4e073e854742 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -913,7 +913,7 @@
913 80 81 68 69 913 80 81 68 69
914 70 71 72 73 914 70 71 72 73
915 74 75 76 77>; 915 74 75 76 77>;
916 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", 916 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
917 "saif0", "saif1", "i2c0", "i2c1", 917 "saif0", "saif1", "i2c0", "i2c1",
918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", 918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; 919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 19cc269a08d4..1ce6133b67f5 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -31,6 +31,7 @@
31 regulator-min-microvolt = <5000000>; 31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>; 32 regulator-max-microvolt = <5000000>;
33 gpio = <&gpio4 15 0>; 33 gpio = <&gpio4 15 0>;
34 enable-active-high;
34 }; 35 };
35 36
36 reg_usb_h1_vbus: regulator@1 { 37 reg_usb_h1_vbus: regulator@1 {
@@ -40,6 +41,7 @@
40 regulator-min-microvolt = <5000000>; 41 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>; 42 regulator-max-microvolt = <5000000>;
42 gpio = <&gpio1 0 0>; 43 gpio = <&gpio1 0 0>;
44 enable-active-high;
43 }; 45 };
44 }; 46 };
45 47
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 46b2fed7c319..3b24b12651b2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -185,7 +185,6 @@
185&i2c3 { 185&i2c3 {
186 pinctrl-names = "default"; 186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_i2c3>; 187 pinctrl-0 = <&pinctrl_i2c3>;
188 pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
189 status = "okay"; 188 status = "okay";
190 189
191 max7310_a: gpio@30 { 190 max7310_a: gpio@30 {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index a29315833ecd..5c16145920ea 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -498,6 +498,8 @@
498 DRVDD-supply = <&vmmc2>; 498 DRVDD-supply = <&vmmc2>;
499 IOVDD-supply = <&vio>; 499 IOVDD-supply = <&vio>;
500 DVDD-supply = <&vio>; 500 DVDD-supply = <&vio>;
501
502 ai3x-micbias-vg = <1>;
501 }; 503 };
502 504
503 tlv320aic3x_aux: tlv320aic3x@19 { 505 tlv320aic3x_aux: tlv320aic3x@19 {
@@ -509,6 +511,8 @@
509 DRVDD-supply = <&vmmc2>; 511 DRVDD-supply = <&vmmc2>;
510 IOVDD-supply = <&vio>; 512 IOVDD-supply = <&vio>;
511 DVDD-supply = <&vio>; 513 DVDD-supply = <&vio>;
514
515 ai3x-micbias-vg = <2>;
512 }; 516 };
513 517
514 tsl2563: tsl2563@29 { 518 tsl2563: tsl2563@29 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d18a90f5eca3..69a40cfc1f29 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -456,6 +456,7 @@
456 }; 456 };
457 457
458 mmu_isp: mmu@480bd400 { 458 mmu_isp: mmu@480bd400 {
459 #iommu-cells = <0>;
459 compatible = "ti,omap2-iommu"; 460 compatible = "ti,omap2-iommu";
460 reg = <0x480bd400 0x80>; 461 reg = <0x480bd400 0x80>;
461 interrupts = <24>; 462 interrupts = <24>;
@@ -464,6 +465,7 @@
464 }; 465 };
465 466
466 mmu_iva: mmu@5d000000 { 467 mmu_iva: mmu@5d000000 {
468 #iommu-cells = <0>;
467 compatible = "ti,omap2-iommu"; 469 compatible = "ti,omap2-iommu";
468 reg = <0x5d000000 0x80>; 470 reg = <0x5d000000 0x80>;
469 interrupts = <28>; 471 interrupts = <28>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index efe5f737f39b..7d24ae0306b5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -128,7 +128,7 @@
128 * hierarchy. 128 * hierarchy.
129 */ 129 */
130 ocp { 130 ocp {
131 compatible = "ti,omap4-l3-noc", "simple-bus"; 131 compatible = "ti,omap5-l3-noc", "simple-bus";
132 #address-cells = <1>; 132 #address-cells = <1>;
133 #size-cells = <1>; 133 #size-cells = <1>;
134 ranges; 134 ranges;
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 74c3212f1f11..824ddab9c3ad 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -545,7 +545,7 @@
545 compatible = "adi,adv7511w"; 545 compatible = "adi,adv7511w";
546 reg = <0x39>; 546 reg = <0x39>;
547 interrupt-parent = <&gpio3>; 547 interrupt-parent = <&gpio3>;
548 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 548 interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
549 549
550 adi,input-depth = <8>; 550 adi,input-depth = <8>;
551 adi,input-colorspace = "rgb"; 551 adi,input-colorspace = "rgb";
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index bfd3f1c734b8..2201cd5da3bb 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -1017,23 +1017,6 @@
1017 status = "disabled"; 1017 status = "disabled";
1018 }; 1018 };
1019 1019
1020 vmmci: regulator-gpio {
1021 compatible = "regulator-gpio";
1022
1023 regulator-min-microvolt = <1800000>;
1024 regulator-max-microvolt = <2900000>;
1025 regulator-name = "mmci-reg";
1026 regulator-type = "voltage";
1027
1028 startup-delay-us = <100>;
1029 enable-active-high;
1030
1031 states = <1800000 0x1
1032 2900000 0x0>;
1033
1034 status = "disabled";
1035 };
1036
1037 mcde@a0350000 { 1020 mcde@a0350000 {
1038 compatible = "stericsson,mcde"; 1021 compatible = "stericsson,mcde";
1039 reg = <0xa0350000 0x1000>, /* MCDE */ 1022 reg = <0xa0350000 0x1000>, /* MCDE */
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index bf8f0eddc2c0..744c1e3a744d 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -111,6 +111,21 @@
111 pinctrl-1 = <&i2c3_sleep_mode>; 111 pinctrl-1 = <&i2c3_sleep_mode>;
112 }; 112 };
113 113
114 vmmci: regulator-gpio {
115 compatible = "regulator-gpio";
116
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <2900000>;
119 regulator-name = "mmci-reg";
120 regulator-type = "voltage";
121
122 startup-delay-us = <100>;
123 enable-active-high;
124
125 states = <1800000 0x1
126 2900000 0x0>;
127 };
128
114 // External Micro SD slot 129 // External Micro SD slot
115 sdi0_per1@80126000 { 130 sdi0_per1@80126000 {
116 arm,primecell-periphid = <0x10480180>; 131 arm,primecell-periphid = <0x10480180>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 206826a855c0..1bc84ebdccaa 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -146,8 +146,21 @@
146 }; 146 };
147 147
148 vmmci: regulator-gpio { 148 vmmci: regulator-gpio {
149 compatible = "regulator-gpio";
150
149 gpios = <&gpio7 4 0x4>; 151 gpios = <&gpio7 4 0x4>;
150 enable-gpio = <&gpio6 25 0x4>; 152 enable-gpio = <&gpio6 25 0x4>;
153
154 regulator-min-microvolt = <1800000>;
155 regulator-max-microvolt = <2900000>;
156 regulator-name = "mmci-reg";
157 regulator-type = "voltage";
158
159 startup-delay-us = <100>;
160 enable-active-high;
161
162 states = <1800000 0x1
163 2900000 0x0>;
151 }; 164 };
152 165
153 // External Micro SD slot 166 // External Micro SD slot
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index ab86655c1f4b..0ca4a3eaf65d 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -39,11 +39,14 @@ CONFIG_ARCH_HIP04=y
39CONFIG_ARCH_KEYSTONE=y 39CONFIG_ARCH_KEYSTONE=y
40CONFIG_ARCH_MESON=y 40CONFIG_ARCH_MESON=y
41CONFIG_ARCH_MXC=y 41CONFIG_ARCH_MXC=y
42CONFIG_SOC_IMX50=y
42CONFIG_SOC_IMX51=y 43CONFIG_SOC_IMX51=y
43CONFIG_SOC_IMX53=y 44CONFIG_SOC_IMX53=y
44CONFIG_SOC_IMX6Q=y 45CONFIG_SOC_IMX6Q=y
45CONFIG_SOC_IMX6SL=y 46CONFIG_SOC_IMX6SL=y
47CONFIG_SOC_IMX6SX=y
46CONFIG_SOC_VF610=y 48CONFIG_SOC_VF610=y
49CONFIG_SOC_LS1021A=y
47CONFIG_ARCH_OMAP3=y 50CONFIG_ARCH_OMAP3=y
48CONFIG_ARCH_OMAP4=y 51CONFIG_ARCH_OMAP4=y
49CONFIG_SOC_OMAP5=y 52CONFIG_SOC_OMAP5=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 9ff7b54b2a83..3743ca221d40 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -393,7 +393,7 @@ CONFIG_TI_EDMA=y
393CONFIG_DMA_OMAP=y 393CONFIG_DMA_OMAP=y
394# CONFIG_IOMMU_SUPPORT is not set 394# CONFIG_IOMMU_SUPPORT is not set
395CONFIG_EXTCON=m 395CONFIG_EXTCON=m
396CONFIG_EXTCON_GPIO=m 396CONFIG_EXTCON_USB_GPIO=m
397CONFIG_EXTCON_PALMAS=m 397CONFIG_EXTCON_PALMAS=m
398CONFIG_TI_EMIF=m 398CONFIG_TI_EMIF=m
399CONFIG_PWM=y 399CONFIG_PWM=y
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
index fb8d4a2ad48c..a5edd7d60266 100644
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> 2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <kernel@pengutronix.de>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it under 4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the 5 * the terms of the GNU General Public License version 2 as published by the
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index cbefbd7cfdb5..661d753df584 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -112,6 +112,7 @@
112#define OMAP3430_VC_CMD_ONLP_SHIFT 16 112#define OMAP3430_VC_CMD_ONLP_SHIFT 16
113#define OMAP3430_VC_CMD_RET_SHIFT 8 113#define OMAP3430_VC_CMD_RET_SHIFT 8
114#define OMAP3430_VC_CMD_OFF_SHIFT 0 114#define OMAP3430_VC_CMD_OFF_SHIFT 0
115#define OMAP3430_SREN_MASK (1 << 4)
115#define OMAP3430_HSEN_MASK (1 << 3) 116#define OMAP3430_HSEN_MASK (1 << 3)
116#define OMAP3430_MCODE_MASK (0x7 << 0) 117#define OMAP3430_MCODE_MASK (0x7 << 0)
117#define OMAP3430_VALID_MASK (1 << 24) 118#define OMAP3430_VALID_MASK (1 << 24)
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index b1c7a33e00e7..e794828dee55 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -35,6 +35,7 @@
35#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 35#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
36#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 36#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
37#define OMAP4430_HSMCODE_MASK (0x7 << 0) 37#define OMAP4430_HSMCODE_MASK (0x7 << 0)
38#define OMAP4430_SRMODEEN_MASK (1 << 4)
38#define OMAP4430_HSMODEEN_MASK (1 << 3) 39#define OMAP4430_HSMODEEN_MASK (1 << 3)
39#define OMAP4430_HSSCLL_SHIFT 24 40#define OMAP4430_HSSCLL_SHIFT 24
40#define OMAP4430_ICEPICK_RST_SHIFT 9 41#define OMAP4430_ICEPICK_RST_SHIFT 9
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index be9ef834fa81..076fd20d7e5a 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -316,7 +316,8 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
316 * idle. And we can also scale voltages to zero for off-idle. 316 * idle. And we can also scale voltages to zero for off-idle.
317 * Note that no actual voltage scaling during off-idle will 317 * Note that no actual voltage scaling during off-idle will
318 * happen unless the board specific twl4030 PMIC scripts are 318 * happen unless the board specific twl4030 PMIC scripts are
319 * loaded. 319 * loaded. See also omap_vc_i2c_init for comments regarding
320 * erratum i531.
320 */ 321 */
321 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); 322 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
322 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { 323 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
@@ -704,9 +705,16 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
704 return; 705 return;
705 } 706 }
706 707
708 /*
709 * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
710 * erratum i531 "Extra Power Consumed When Repeated Start Operation
711 * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
712 * Otherwise I2C4 eventually leads into about 23mW extra power being
713 * consumed even during off idle using VMODE.
714 */
707 i2c_high_speed = voltdm->pmic->i2c_high_speed; 715 i2c_high_speed = voltdm->pmic->i2c_high_speed;
708 if (i2c_high_speed) 716 if (i2c_high_speed)
709 voltdm->rmw(vc->common->i2c_cfg_hsen_mask, 717 voltdm->rmw(vc->common->i2c_cfg_clear_mask,
710 vc->common->i2c_cfg_hsen_mask, 718 vc->common->i2c_cfg_hsen_mask,
711 vc->common->i2c_cfg_reg); 719 vc->common->i2c_cfg_reg);
712 720
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index cdbdd78e755e..89b83b7ff3ec 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -34,6 +34,7 @@ struct voltagedomain;
34 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register 34 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
35 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register 35 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
36 * @i2c_cfg_reg: I2C configuration register offset 36 * @i2c_cfg_reg: I2C configuration register offset
37 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
37 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register 38 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
38 * @i2c_mcode_mask: MCODE field mask for I2C config register 39 * @i2c_mcode_mask: MCODE field mask for I2C config register
39 * 40 *
@@ -52,6 +53,7 @@ struct omap_vc_common {
52 u8 cmd_ret_shift; 53 u8 cmd_ret_shift;
53 u8 cmd_off_shift; 54 u8 cmd_off_shift;
54 u8 i2c_cfg_reg; 55 u8 i2c_cfg_reg;
56 u8 i2c_cfg_clear_mask;
55 u8 i2c_cfg_hsen_mask; 57 u8 i2c_cfg_hsen_mask;
56 u8 i2c_mcode_mask; 58 u8 i2c_mcode_mask;
57}; 59};
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index 75bc4aa22b3a..71d74c9172c1 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -40,6 +40,7 @@ static struct omap_vc_common omap3_vc_common = {
40 .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, 40 .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
41 .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, 41 .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
42 .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, 42 .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
43 .i2c_cfg_clear_mask = OMAP3430_SREN_MASK | OMAP3430_HSEN_MASK,
43 .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK, 44 .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
44 .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET, 45 .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET,
45 .i2c_mcode_mask = OMAP3430_MCODE_MASK, 46 .i2c_mcode_mask = OMAP3430_MCODE_MASK,
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
index 085e5d6a04fd..2abd5fa8a697 100644
--- a/arch/arm/mach-omap2/vc44xx_data.c
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -42,6 +42,7 @@ static const struct omap_vc_common omap4_vc_common = {
42 .cmd_ret_shift = OMAP4430_RET_SHIFT, 42 .cmd_ret_shift = OMAP4430_RET_SHIFT,
43 .cmd_off_shift = OMAP4430_OFF_SHIFT, 43 .cmd_off_shift = OMAP4430_OFF_SHIFT,
44 .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET, 44 .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
45 .i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK,
45 .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK, 46 .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
46 .i2c_mcode_mask = OMAP4430_HSMCODE_MASK, 47 .i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
47}; 48};
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 8896e71586f5..f09683687963 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -691,4 +691,13 @@ config SHARPSL_PM_MAX1111
691config PXA310_ULPI 691config PXA310_ULPI
692 bool 692 bool
693 693
694config PXA_SYSTEMS_CPLDS
695 tristate "Motherboard cplds"
696 default ARCH_LUBBOCK || MACH_MAINSTONE
697 help
698 This driver supports the Lubbock and Mainstone multifunction chip
699 found on the pxa25x development platform system (Lubbock) and pxa27x
700 development platform system (Mainstone). This IO board supports the
701 interrupts handling, ethernet controller, flash chips, etc ...
702
694endif 703endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index eb0bf7678a99..4087d334ecdf 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -90,4 +90,5 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o
90obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o 90obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o
91obj-$(CONFIG_MACH_ZIPIT2) += z2.o 91obj-$(CONFIG_MACH_ZIPIT2) += z2.o
92 92
93obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o
93obj-$(CONFIG_TOSA_BT) += tosa-bt.o 94obj-$(CONFIG_TOSA_BT) += tosa-bt.o
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index 958cd6af9384..1eecf794acd2 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -37,7 +37,9 @@
37#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) 37#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
38 38
39/* Board specific IRQs */ 39/* Board specific IRQs */
40#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) 40#define LUBBOCK_NR_IRQS IRQ_BOARD_START
41
42#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x))
41#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) 43#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
42#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) 44#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
43#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ 45#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
@@ -47,8 +49,7 @@
47#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ 49#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
48#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) 50#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
49 51
50#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16) 52#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32)
51#define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55)
52 53
53#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
54extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); 55extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
index 1bfc4e822a41..e82a7d31104e 100644
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -120,7 +120,9 @@
120#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ 120#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
121 121
122/* board specific IRQs */ 122/* board specific IRQs */
123#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) 123#define MAINSTONE_NR_IRQS IRQ_BOARD_START
124
125#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x))
124#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) 126#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
125#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) 127#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
126#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) 128#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
@@ -136,6 +138,4 @@
136#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) 138#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
137#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) 139#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
138 140
139#define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16)
140
141#endif 141#endif
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index d8a1be619f21..4ac9ab80d24b 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -12,6 +12,7 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14#include <linux/gpio.h> 14#include <linux/gpio.h>
15#include <linux/gpio/machine.h>
15#include <linux/module.h> 16#include <linux/module.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17#include <linux/init.h> 18#include <linux/init.h>
@@ -123,84 +124,6 @@ void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
123} 124}
124EXPORT_SYMBOL(lubbock_set_misc_wr); 125EXPORT_SYMBOL(lubbock_set_misc_wr);
125 126
126static unsigned long lubbock_irq_enabled;
127
128static void lubbock_mask_irq(struct irq_data *d)
129{
130 int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
131 LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq));
132}
133
134static void lubbock_unmask_irq(struct irq_data *d)
135{
136 int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
137 /* the irq can be acknowledged only if deasserted, so it's done here */
138 LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq);
139 LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq));
140}
141
142static struct irq_chip lubbock_irq_chip = {
143 .name = "FPGA",
144 .irq_ack = lubbock_mask_irq,
145 .irq_mask = lubbock_mask_irq,
146 .irq_unmask = lubbock_unmask_irq,
147};
148
149static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
150{
151 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
152 do {
153 /* clear our parent irq */
154 desc->irq_data.chip->irq_ack(&desc->irq_data);
155 if (likely(pending)) {
156 irq = LUBBOCK_IRQ(0) + __ffs(pending);
157 generic_handle_irq(irq);
158 }
159 pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
160 } while (pending);
161}
162
163static void __init lubbock_init_irq(void)
164{
165 int irq;
166
167 pxa25x_init_irq();
168
169 /* setup extra lubbock irqs */
170 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
171 irq_set_chip_and_handler(irq, &lubbock_irq_chip,
172 handle_level_irq);
173 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
174 }
175
176 irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler);
177 irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
178}
179
180#ifdef CONFIG_PM
181
182static void lubbock_irq_resume(void)
183{
184 LUB_IRQ_MASK_EN = lubbock_irq_enabled;
185}
186
187static struct syscore_ops lubbock_irq_syscore_ops = {
188 .resume = lubbock_irq_resume,
189};
190
191static int __init lubbock_irq_device_init(void)
192{
193 if (machine_is_lubbock()) {
194 register_syscore_ops(&lubbock_irq_syscore_ops);
195 return 0;
196 }
197 return -ENODEV;
198}
199
200device_initcall(lubbock_irq_device_init);
201
202#endif
203
204static int lubbock_udc_is_connected(void) 127static int lubbock_udc_is_connected(void)
205{ 128{
206 return (LUB_MISC_RD & (1 << 9)) == 0; 129 return (LUB_MISC_RD & (1 << 9)) == 0;
@@ -383,11 +306,38 @@ static struct platform_device lubbock_flash_device[2] = {
383 }, 306 },
384}; 307};
385 308
309static struct resource lubbock_cplds_resources[] = {
310 [0] = {
311 .start = LUBBOCK_FPGA_PHYS + 0xc0,
312 .end = LUBBOCK_FPGA_PHYS + 0xe0 - 1,
313 .flags = IORESOURCE_MEM,
314 },
315 [1] = {
316 .start = PXA_GPIO_TO_IRQ(0),
317 .end = PXA_GPIO_TO_IRQ(0),
318 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
319 },
320 [2] = {
321 .start = LUBBOCK_IRQ(0),
322 .end = LUBBOCK_IRQ(6),
323 .flags = IORESOURCE_IRQ,
324 },
325};
326
327static struct platform_device lubbock_cplds_device = {
328 .name = "pxa_cplds_irqs",
329 .id = -1,
330 .resource = &lubbock_cplds_resources[0],
331 .num_resources = 3,
332};
333
334
386static struct platform_device *devices[] __initdata = { 335static struct platform_device *devices[] __initdata = {
387 &sa1111_device, 336 &sa1111_device,
388 &smc91x_device, 337 &smc91x_device,
389 &lubbock_flash_device[0], 338 &lubbock_flash_device[0],
390 &lubbock_flash_device[1], 339 &lubbock_flash_device[1],
340 &lubbock_cplds_device,
391}; 341};
392 342
393static struct pxafb_mode_info sharp_lm8v31_mode = { 343static struct pxafb_mode_info sharp_lm8v31_mode = {
@@ -648,7 +598,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
648 /* Maintainer: MontaVista Software Inc. */ 598 /* Maintainer: MontaVista Software Inc. */
649 .map_io = lubbock_map_io, 599 .map_io = lubbock_map_io,
650 .nr_irqs = LUBBOCK_NR_IRQS, 600 .nr_irqs = LUBBOCK_NR_IRQS,
651 .init_irq = lubbock_init_irq, 601 .init_irq = pxa25x_init_irq,
652 .handle_irq = pxa25x_handle_irq, 602 .handle_irq = pxa25x_handle_irq,
653 .init_time = pxa_timer_init, 603 .init_time = pxa_timer_init,
654 .init_machine = lubbock_init, 604 .init_machine = lubbock_init,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 78b84c0dfc79..2c0658cf6be2 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -13,6 +13,7 @@
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/gpio/machine.h>
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/platform_device.h> 18#include <linux/platform_device.h>
18#include <linux/syscore_ops.h> 19#include <linux/syscore_ops.h>
@@ -122,92 +123,6 @@ static unsigned long mainstone_pin_config[] = {
122 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, 123 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
123}; 124};
124 125
125static unsigned long mainstone_irq_enabled;
126
127static void mainstone_mask_irq(struct irq_data *d)
128{
129 int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
130 MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
131}
132
133static void mainstone_unmask_irq(struct irq_data *d)
134{
135 int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
136 /* the irq can be acknowledged only if deasserted, so it's done here */
137 MST_INTSETCLR &= ~(1 << mainstone_irq);
138 MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
139}
140
141static struct irq_chip mainstone_irq_chip = {
142 .name = "FPGA",
143 .irq_ack = mainstone_mask_irq,
144 .irq_mask = mainstone_mask_irq,
145 .irq_unmask = mainstone_unmask_irq,
146};
147
148static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
149{
150 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
151 do {
152 /* clear useless edge notification */
153 desc->irq_data.chip->irq_ack(&desc->irq_data);
154 if (likely(pending)) {
155 irq = MAINSTONE_IRQ(0) + __ffs(pending);
156 generic_handle_irq(irq);
157 }
158 pending = MST_INTSETCLR & mainstone_irq_enabled;
159 } while (pending);
160}
161
162static void __init mainstone_init_irq(void)
163{
164 int irq;
165
166 pxa27x_init_irq();
167
168 /* setup extra Mainstone irqs */
169 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
170 irq_set_chip_and_handler(irq, &mainstone_irq_chip,
171 handle_level_irq);
172 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
173 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
174 else
175 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
176 }
177 set_irq_flags(MAINSTONE_IRQ(8), 0);
178 set_irq_flags(MAINSTONE_IRQ(12), 0);
179
180 MST_INTMSKENA = 0;
181 MST_INTSETCLR = 0;
182
183 irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler);
184 irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
185}
186
187#ifdef CONFIG_PM
188
189static void mainstone_irq_resume(void)
190{
191 MST_INTMSKENA = mainstone_irq_enabled;
192}
193
194static struct syscore_ops mainstone_irq_syscore_ops = {
195 .resume = mainstone_irq_resume,
196};
197
198static int __init mainstone_irq_device_init(void)
199{
200 if (machine_is_mainstone())
201 register_syscore_ops(&mainstone_irq_syscore_ops);
202
203 return 0;
204}
205
206device_initcall(mainstone_irq_device_init);
207
208#endif
209
210
211static struct resource smc91x_resources[] = { 126static struct resource smc91x_resources[] = {
212 [0] = { 127 [0] = {
213 .start = (MST_ETH_PHYS + 0x300), 128 .start = (MST_ETH_PHYS + 0x300),
@@ -487,11 +402,37 @@ static struct platform_device mst_gpio_keys_device = {
487 }, 402 },
488}; 403};
489 404
405static struct resource mst_cplds_resources[] = {
406 [0] = {
407 .start = MST_FPGA_PHYS + 0xc0,
408 .end = MST_FPGA_PHYS + 0xe0 - 1,
409 .flags = IORESOURCE_MEM,
410 },
411 [1] = {
412 .start = PXA_GPIO_TO_IRQ(0),
413 .end = PXA_GPIO_TO_IRQ(0),
414 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
415 },
416 [2] = {
417 .start = MAINSTONE_IRQ(0),
418 .end = MAINSTONE_IRQ(15),
419 .flags = IORESOURCE_IRQ,
420 },
421};
422
423static struct platform_device mst_cplds_device = {
424 .name = "pxa_cplds_irqs",
425 .id = -1,
426 .resource = &mst_cplds_resources[0],
427 .num_resources = 3,
428};
429
490static struct platform_device *platform_devices[] __initdata = { 430static struct platform_device *platform_devices[] __initdata = {
491 &smc91x_device, 431 &smc91x_device,
492 &mst_flash_device[0], 432 &mst_flash_device[0],
493 &mst_flash_device[1], 433 &mst_flash_device[1],
494 &mst_gpio_keys_device, 434 &mst_gpio_keys_device,
435 &mst_cplds_device,
495}; 436};
496 437
497static struct pxaohci_platform_data mainstone_ohci_platform_data = { 438static struct pxaohci_platform_data mainstone_ohci_platform_data = {
@@ -718,7 +659,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
718 .atag_offset = 0x100, /* BLOB boot parameter setting */ 659 .atag_offset = 0x100, /* BLOB boot parameter setting */
719 .map_io = mainstone_map_io, 660 .map_io = mainstone_map_io,
720 .nr_irqs = MAINSTONE_NR_IRQS, 661 .nr_irqs = MAINSTONE_NR_IRQS,
721 .init_irq = mainstone_init_irq, 662 .init_irq = pxa27x_init_irq,
722 .handle_irq = pxa27x_handle_irq, 663 .handle_irq = pxa27x_handle_irq,
723 .init_time = pxa_timer_init, 664 .init_time = pxa_timer_init,
724 .init_machine = mainstone_init, 665 .init_machine = mainstone_init,
diff --git a/arch/arm/mach-pxa/pxa_cplds_irqs.c b/arch/arm/mach-pxa/pxa_cplds_irqs.c
new file mode 100644
index 000000000000..f1aeb54fabe3
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa_cplds_irqs.c
@@ -0,0 +1,200 @@
1/*
2 * Intel Reference Systems cplds
3 *
4 * Copyright (C) 2014 Robert Jarzmik
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * Cplds motherboard driver, supporting lubbock and mainstone SoC board.
12 */
13
14#include <linux/bitops.h>
15#include <linux/gpio.h>
16#include <linux/gpio/consumer.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/mfd/core.h>
22#include <linux/module.h>
23#include <linux/of_platform.h>
24
25#define FPGA_IRQ_MASK_EN 0x0
26#define FPGA_IRQ_SET_CLR 0x10
27
28#define CPLDS_NB_IRQ 32
29
30struct cplds {
31 void __iomem *base;
32 int irq;
33 unsigned int irq_mask;
34 struct gpio_desc *gpio0;
35 struct irq_domain *irqdomain;
36};
37
38static irqreturn_t cplds_irq_handler(int in_irq, void *d)
39{
40 struct cplds *fpga = d;
41 unsigned long pending;
42 unsigned int bit;
43
44 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
45 for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
46 generic_handle_irq(irq_find_mapping(fpga->irqdomain, bit));
47
48 return IRQ_HANDLED;
49}
50
51static void cplds_irq_mask_ack(struct irq_data *d)
52{
53 struct cplds *fpga = irq_data_get_irq_chip_data(d);
54 unsigned int cplds_irq = irqd_to_hwirq(d);
55 unsigned int set, bit = BIT(cplds_irq);
56
57 fpga->irq_mask &= ~bit;
58 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
59 set = readl(fpga->base + FPGA_IRQ_SET_CLR);
60 writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
61}
62
63static void cplds_irq_unmask(struct irq_data *d)
64{
65 struct cplds *fpga = irq_data_get_irq_chip_data(d);
66 unsigned int cplds_irq = irqd_to_hwirq(d);
67 unsigned int bit = BIT(cplds_irq);
68
69 fpga->irq_mask |= bit;
70 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
71}
72
73static struct irq_chip cplds_irq_chip = {
74 .name = "pxa_cplds",
75 .irq_mask_ack = cplds_irq_mask_ack,
76 .irq_unmask = cplds_irq_unmask,
77 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
78};
79
80static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq,
81 irq_hw_number_t hwirq)
82{
83 struct cplds *fpga = d->host_data;
84
85 irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq);
86 irq_set_chip_data(irq, fpga);
87
88 return 0;
89}
90
91static const struct irq_domain_ops cplds_irq_domain_ops = {
92 .xlate = irq_domain_xlate_twocell,
93 .map = cplds_irq_domain_map,
94};
95
96static int cplds_resume(struct platform_device *pdev)
97{
98 struct cplds *fpga = platform_get_drvdata(pdev);
99
100 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
101
102 return 0;
103}
104
105static int cplds_probe(struct platform_device *pdev)
106{
107 struct resource *res;
108 struct cplds *fpga;
109 int ret;
110 unsigned int base_irq = 0;
111 unsigned long irqflags = 0;
112
113 fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
114 if (!fpga)
115 return -ENOMEM;
116
117 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
118 if (res) {
119 fpga->irq = (unsigned int)res->start;
120 irqflags = res->flags;
121 }
122 if (!fpga->irq)
123 return -ENODEV;
124
125 base_irq = platform_get_irq(pdev, 1);
126 if (base_irq < 0)
127 base_irq = 0;
128
129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130 fpga->base = devm_ioremap_resource(&pdev->dev, res);
131 if (IS_ERR(fpga->base))
132 return PTR_ERR(fpga->base);
133
134 platform_set_drvdata(pdev, fpga);
135
136 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
137 writel(0, fpga->base + FPGA_IRQ_SET_CLR);
138
139 ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
140 irqflags, dev_name(&pdev->dev), fpga);
141 if (ret == -ENOSYS)
142 return -EPROBE_DEFER;
143
144 if (ret) {
145 dev_err(&pdev->dev, "couldn't request main irq%d: %d\n",
146 fpga->irq, ret);
147 return ret;
148 }
149
150 irq_set_irq_wake(fpga->irq, 1);
151 fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
152 CPLDS_NB_IRQ,
153 &cplds_irq_domain_ops, fpga);
154 if (!fpga->irqdomain)
155 return -ENODEV;
156
157 if (base_irq) {
158 ret = irq_create_strict_mappings(fpga->irqdomain, base_irq, 0,
159 CPLDS_NB_IRQ);
160 if (ret) {
161 dev_err(&pdev->dev, "couldn't create the irq mapping %d..%d\n",
162 base_irq, base_irq + CPLDS_NB_IRQ);
163 return ret;
164 }
165 }
166
167 return 0;
168}
169
170static int cplds_remove(struct platform_device *pdev)
171{
172 struct cplds *fpga = platform_get_drvdata(pdev);
173
174 irq_set_chip_and_handler(fpga->irq, NULL, NULL);
175
176 return 0;
177}
178
179static const struct of_device_id cplds_id_table[] = {
180 { .compatible = "intel,lubbock-cplds-irqs", },
181 { .compatible = "intel,mainstone-cplds-irqs", },
182 { }
183};
184MODULE_DEVICE_TABLE(of, cplds_id_table);
185
186static struct platform_driver cplds_driver = {
187 .driver = {
188 .name = "pxa_cplds_irqs",
189 .of_match_table = of_match_ptr(cplds_id_table),
190 },
191 .probe = cplds_probe,
192 .remove = cplds_remove,
193 .resume = cplds_resume,
194};
195
196module_platform_driver(cplds_driver);
197
198MODULE_DESCRIPTION("PXA Cplds interrupts driver");
199MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
200MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index b07d88602073..22812fe06460 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -44,9 +44,11 @@ static void __iomem *rk3288_bootram_base;
44static phys_addr_t rk3288_bootram_phy; 44static phys_addr_t rk3288_bootram_phy;
45 45
46static struct regmap *pmu_regmap; 46static struct regmap *pmu_regmap;
47static struct regmap *grf_regmap;
47static struct regmap *sgrf_regmap; 48static struct regmap *sgrf_regmap;
48 49
49static u32 rk3288_pmu_pwr_mode_con; 50static u32 rk3288_pmu_pwr_mode_con;
51static u32 rk3288_grf_soc_con0;
50static u32 rk3288_sgrf_soc_con0; 52static u32 rk3288_sgrf_soc_con0;
51 53
52static inline u32 rk3288_l2_config(void) 54static inline u32 rk3288_l2_config(void)
@@ -70,12 +72,26 @@ static void rk3288_slp_mode_set(int level)
70{ 72{
71 u32 mode_set, mode_set1; 73 u32 mode_set, mode_set1;
72 74
75 regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0);
76
73 regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); 77 regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
74 78
75 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, 79 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
76 &rk3288_pmu_pwr_mode_con); 80 &rk3288_pmu_pwr_mode_con);
77 81
78 /* 82 /*
83 * We need set this bit GRF_FORCE_JTAG here, for the debug module,
84 * otherwise, it may become inaccessible after resume.
85 * This creates a potential security issue, as the sdmmc pins may
86 * accept jtag data for a short time during resume if no card is
87 * inserted.
88 * But this is of course also true for the regular boot, before we
89 * turn of the jtag/sdmmc autodetect.
90 */
91 regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG |
92 GRF_FORCE_JTAG_WRITE);
93
94 /*
79 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR 95 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
80 * PCLK_WDT_GATE - disable WDT during suspend. 96 * PCLK_WDT_GATE - disable WDT during suspend.
81 */ 97 */
@@ -83,6 +99,13 @@ static void rk3288_slp_mode_set(int level)
83 SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN 99 SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
84 | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); 100 | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
85 101
102 /*
103 * The dapswjdp can not auto reset before resume, that cause it may
104 * access some illegal address during resume. Let's disable it before
105 * suspend, and the MASKROM will enable it back.
106 */
107 regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
108
86 /* booting address of resuming system is from this register value */ 109 /* booting address of resuming system is from this register value */
87 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, 110 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
88 rk3288_bootram_phy); 111 rk3288_bootram_phy);
@@ -128,6 +151,9 @@ static void rk3288_slp_mode_set_resume(void)
128 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 151 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
129 rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE 152 rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
130 | SGRF_FAST_BOOT_EN_WRITE); 153 | SGRF_FAST_BOOT_EN_WRITE);
154
155 regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 |
156 GRF_FORCE_JTAG_WRITE);
131} 157}
132 158
133static int rockchip_lpmode_enter(unsigned long arg) 159static int rockchip_lpmode_enter(unsigned long arg)
@@ -186,6 +212,13 @@ static int rk3288_suspend_init(struct device_node *np)
186 return PTR_ERR(pmu_regmap); 212 return PTR_ERR(pmu_regmap);
187 } 213 }
188 214
215 grf_regmap = syscon_regmap_lookup_by_compatible(
216 "rockchip,rk3288-grf");
217 if (IS_ERR(grf_regmap)) {
218 pr_err("%s: could not find grf regmap\n", __func__);
219 return PTR_ERR(pmu_regmap);
220 }
221
189 sram_np = of_find_compatible_node(NULL, NULL, 222 sram_np = of_find_compatible_node(NULL, NULL,
190 "rockchip,rk3288-pmu-sram"); 223 "rockchip,rk3288-pmu-sram");
191 if (!sram_np) { 224 if (!sram_np) {
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index 03ff31d8282d..f8a747bc1437 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -48,6 +48,10 @@ static inline void rockchip_suspend_init(void)
48#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 48#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
49#define RK3288_PMU_PWRMODE_CON1 0x90 49#define RK3288_PMU_PWRMODE_CON1 0x90
50 50
51#define RK3288_GRF_SOC_CON0 0x244
52#define GRF_FORCE_JTAG BIT(12)
53#define GRF_FORCE_JTAG_WRITE BIT(28)
54
51#define RK3288_SGRF_SOC_CON0 (0x0000) 55#define RK3288_SGRF_SOC_CON0 (0x0000)
52#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) 56#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
53#define SGRF_PCLK_WDT_GATE BIT(6) 57#define SGRF_PCLK_WDT_GATE BIT(6)
@@ -55,6 +59,10 @@ static inline void rockchip_suspend_init(void)
55#define SGRF_FAST_BOOT_EN BIT(8) 59#define SGRF_FAST_BOOT_EN BIT(8)
56#define SGRF_FAST_BOOT_EN_WRITE BIT(24) 60#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
57 61
62#define RK3288_SGRF_CPU_CON0 (0x40)
63#define SGRF_DAPDEVICEEN BIT(0)
64#define SGRF_DAPDEVICEEN_WRITE BIT(16)
65
58#define RK3288_CRU_MODE_CON 0x50 66#define RK3288_CRU_MODE_CON 0x50
59#define RK3288_CRU_SEL0_CON 0x60 67#define RK3288_CRU_SEL0_CON 0x60
60#define RK3288_CRU_SEL1_CON 0x64 68#define RK3288_CRU_SEL1_CON 0x64
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index d360ec044b66..b6cf3b449428 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -30,11 +30,30 @@
30#include "pm.h" 30#include "pm.h"
31 31
32#define RK3288_GRF_SOC_CON0 0x244 32#define RK3288_GRF_SOC_CON0 0x244
33#define RK3288_TIMER6_7_PHYS 0xff810000
33 34
34static void __init rockchip_timer_init(void) 35static void __init rockchip_timer_init(void)
35{ 36{
36 if (of_machine_is_compatible("rockchip,rk3288")) { 37 if (of_machine_is_compatible("rockchip,rk3288")) {
37 struct regmap *grf; 38 struct regmap *grf;
39 void __iomem *reg_base;
40
41 /*
42 * Most/all uboot versions for rk3288 don't enable timer7
43 * which is needed for the architected timer to work.
44 * So make sure it is running during early boot.
45 */
46 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
47 if (reg_base) {
48 writel(0, reg_base + 0x30);
49 writel(0xffffffff, reg_base + 0x20);
50 writel(0xffffffff, reg_base + 0x24);
51 writel(1, reg_base + 0x30);
52 dsb();
53 iounmap(reg_base);
54 } else {
55 pr_err("rockchip: could not map timer7 registers\n");
56 }
38 57
39 /* 58 /*
40 * Disable auto jtag/sdmmc switching that causes issues 59 * Disable auto jtag/sdmmc switching that causes issues
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-30 03:13:16 -0400