ACPI / CPPC: Add support for functional fixed hardware address

The CPPC registers can also be accessed via functional fixed hardware
addresse(FFH) in X86. Add support by modifying cpc_read and cpc_write to
be able to read/write MSRs on x86 platform on per cpu basis.
Also with this change, acpi_cppc_processor_probe doesn't bail out if
address space id is not equal to PCC or memory address space and FFH
is supported on the system.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

2 files changed, 59 insertions, 0 deletions

diff --git a/arch/x86/kernel/acpi/Makefile b/arch/x86/kernel/acpi/Makefile
index 3242e591fa82..26b78d86f25a 100644
--- a/arch/x86/kernel/acpi/Makefile
+++ b/arch/x86/kernel/acpi/Makefile
@@ -1,6 +1,7 @@
 obj-$(CONFIG_ACPI)              += boot.o
 obj-$(CONFIG_ACPI_SLEEP)        += sleep.o wakeup_$(BITS).o
 obj-$(CONFIG_ACPI_APEI)         += apei.o
+obj-$(CONFIG_ACPI_CPPC_LIB)     += cppc_msr.o
 
 ifneq ($(CONFIG_ACPI_PROCESSOR),)
 obj-y                           += cstate.o
diff --git a/arch/x86/kernel/acpi/cppc_msr.c b/arch/x86/kernel/acpi/cppc_msr.c
new file mode 100644
index 000000000000..6fb478bf82fd
--- /dev/null
+++ b/arch/x86/kernel/acpi/cppc_msr.c
@@ -0,0 +1,58 @@
+/*
+ * cppc_msr.c:  MSR Interface for CPPC
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <acpi/cppc_acpi.h>
+#include <asm/msr.h>
+
+/* Refer to drivers/acpi/cppc_acpi.c for the description of functions */
+
+bool cpc_ffh_supported(void)
+{
+        return true;
+}
+
+int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
+{
+        int err;
+
+        err = rdmsrl_safe_on_cpu(cpunum, reg->address, val);
+        if (!err) {
+                u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
+                                       reg->bit_offset);
+
+                *val &= mask;
+                *val >>= reg->bit_offset;
+        }
+        return err;
+}
+
+int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
+{
+        u64 rd_val;
+        int err;
+
+        err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val);
+        if (!err) {
+                u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
+                                       reg->bit_offset);
+
+                val <<= reg->bit_offset;
+                val &= mask;
+                rd_val &= ~mask;
+                rd_val |= val;
+                err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val);
+        }
+        return err;
+}