Merge branch 'x86/urgent' into x86/cpu, to pick up dependency

Signed-off-by: Ingo Molnar <mingo@kernel.org>

69 files changed, 1633 insertions, 909 deletions

diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 616ebd22ef9a..0503f5bfb18d 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -2,7 +2,11 @@
 # Makefile for the linux kernel.
 #
 
-extra-y                := head_$(BITS).o head$(BITS).o head.o vmlinux.lds
+extra-y := head_$(BITS).o
+extra-y += head$(BITS).o
+extra-y += ebda.o
+extra-y += platform-quirks.o
+extra-y += vmlinux.lds
 
 CPPFLAGS_vmlinux.lds += -U$(UTS_MACHINE)
 
@@ -79,7 +83,6 @@ obj-$(CONFIG_X86_MPPARSE)	+= mpparse.o
 obj-y                           += apic/
 obj-$(CONFIG_X86_REBOOTFIXUPS)  += reboot_fixups_32.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
-obj-$(CONFIG_LIVEPATCH)         += livepatch.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
 obj-$(CONFIG_FTRACE_SYSCALLS)   += ftrace.o
 obj-$(CONFIG_X86_TSC)           += trace_clock.o
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 8c2f1ef6ca23..9414f84584e4 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -136,7 +136,7 @@ static int __init acpi_parse_madt(struct acpi_table_header *table)
 {
         struct acpi_table_madt *madt = NULL;
 
-        if (!cpu_has_apic)
+        if (!boot_cpu_has(X86_FEATURE_APIC))
                 return -EINVAL;
 
         madt = (struct acpi_table_madt *)table;
@@ -445,7 +445,6 @@ static void __init acpi_sci_ioapic_setup(u8 bus_irq, u16 polarity, u16 trigger,
                 polarity = acpi_sci_flags & ACPI_MADT_POLARITY_MASK;
 
         mp_override_legacy_irq(bus_irq, polarity, trigger, gsi);
-        acpi_penalize_sci_irq(bus_irq, trigger, polarity);
 
         /*
          * stash over-ride to indicate we've been here
@@ -913,6 +912,15 @@ late_initcall(hpet_insert_resource);
 
 static int __init acpi_parse_fadt(struct acpi_table_header *table)
 {
+        if (!(acpi_gbl_FADT.boot_flags & ACPI_FADT_LEGACY_DEVICES)) {
+                pr_debug("ACPI: no legacy devices present\n");
+                x86_platform.legacy.devices.pnpbios = 0;
+        }
+
+        if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_CMOS_RTC) {
+                pr_debug("ACPI: not registering RTC platform device\n");
+                x86_platform.legacy.rtc = 0;
+        }
 
 #ifdef CONFIG_X86_PM_TIMER
         /* detect the location of the ACPI PM Timer */
@@ -951,7 +959,7 @@ static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
 {
         int count;
 
-        if (!cpu_has_apic)
+        if (!boot_cpu_has(X86_FEATURE_APIC))
                 return -ENODEV;
 
         /*
@@ -979,7 +987,7 @@ static int __init acpi_parse_madt_lapic_entries(void)
         int ret;
         struct acpi_subtable_proc madt_proc[2];
 
-        if (!cpu_has_apic)
+        if (!boot_cpu_has(X86_FEATURE_APIC))
                 return -ENODEV;
 
         /*
@@ -1125,7 +1133,7 @@ static int __init acpi_parse_madt_ioapic_entries(void)
         if (acpi_disabled || acpi_noirq)
                 return -ENODEV;
 
-        if (!cpu_has_apic)
+        if (!boot_cpu_has(X86_FEATURE_APIC))
                 return -ENODEV;
 
         /*
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 25f909362b7a..5cb272a7a5a3 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -11,6 +11,7 @@
 #include <linux/stop_machine.h>
 #include <linux/slab.h>
 #include <linux/kdebug.h>
+#include <asm/text-patching.h>
 #include <asm/alternative.h>
 #include <asm/sections.h>
 #include <asm/pgtable.h>
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index d7867c885bf8..60078a67d7e3 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -607,7 +607,7 @@ static void __init lapic_cal_handler(struct clock_event_device *dev)
         long tapic = apic_read(APIC_TMCCT);
         unsigned long pm = acpi_pm_read_early();
 
-        if (cpu_has_tsc)
+        if (boot_cpu_has(X86_FEATURE_TSC))
                 tsc = rdtsc();
 
         switch (lapic_cal_loops++) {
@@ -668,7 +668,7 @@ calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
         *delta = (long)res;
 
         /* Correct the tsc counter value */
-        if (cpu_has_tsc) {
+        if (boot_cpu_has(X86_FEATURE_TSC)) {
                 res = (((u64)(*deltatsc)) * pm_100ms);
                 do_div(res, deltapm);
                 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
@@ -760,7 +760,7 @@ static int __init calibrate_APIC_clock(void)
         apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
                     lapic_timer_frequency);
 
-        if (cpu_has_tsc) {
+        if (boot_cpu_has(X86_FEATURE_TSC)) {
                 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
                             "%ld.%04ld MHz.\n",
                             (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
@@ -1085,7 +1085,7 @@ void lapic_shutdown(void)
 {
         unsigned long flags;
 
-        if (!cpu_has_apic && !apic_from_smp_config())
+        if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
                 return;
 
         local_irq_save(flags);
@@ -1134,7 +1134,7 @@ void __init init_bsp_APIC(void)
          * Don't do the setup now if we have a SMP BIOS as the
          * through-I/O-APIC virtual wire mode might be active.
          */
-        if (smp_found_config || !cpu_has_apic)
+        if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
                 return;
 
         /*
@@ -1227,7 +1227,7 @@ void setup_local_APIC(void)
         unsigned long long tsc = 0, ntsc;
         long long max_loops = cpu_khz ? cpu_khz : 1000000;
 
-        if (cpu_has_tsc)
+        if (boot_cpu_has(X86_FEATURE_TSC))
                 tsc = rdtsc();
 
         if (disable_apic) {
@@ -1311,7 +1311,7 @@ void setup_local_APIC(void)
                         break;
                 }
                 if (queued) {
-                        if (cpu_has_tsc && cpu_khz) {
+                        if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
                                 ntsc = rdtsc();
                                 max_loops = (cpu_khz << 10) - (ntsc - tsc);
                         } else
@@ -1445,7 +1445,7 @@ static void __x2apic_disable(void)
 {
         u64 msr;
 
-        if (!cpu_has_apic)
+        if (!boot_cpu_has(X86_FEATURE_APIC))
                 return;
 
         rdmsrl(MSR_IA32_APICBASE, msr);
@@ -1632,7 +1632,7 @@ void __init enable_IR_x2apic(void)
  */
 static int __init detect_init_APIC(void)
 {
-        if (!cpu_has_apic) {
+        if (!boot_cpu_has(X86_FEATURE_APIC)) {
                 pr_info("No local APIC present\n");
                 return -1;
         }
@@ -1711,14 +1711,14 @@ static int __init detect_init_APIC(void)
                 goto no_apic;
         case X86_VENDOR_INTEL:
                 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
-                    (boot_cpu_data.x86 == 5 && cpu_has_apic))
+                    (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
                         break;
                 goto no_apic;
         default:
                 goto no_apic;
         }
 
-        if (!cpu_has_apic) {
+        if (!boot_cpu_has(X86_FEATURE_APIC)) {
                 /*
                  * Over-ride BIOS and try to enable the local APIC only if
                  * "lapic" specified.
@@ -2233,19 +2233,19 @@ int __init APIC_init_uniprocessor(void)
                 return -1;
         }
 #ifdef CONFIG_X86_64
-        if (!cpu_has_apic) {
+        if (!boot_cpu_has(X86_FEATURE_APIC)) {
                 disable_apic = 1;
                 pr_info("Apic disabled by BIOS\n");
                 return -1;
         }
 #else
-        if (!smp_found_config && !cpu_has_apic)
+        if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
                 return -1;
 
         /*
          * Complain if the BIOS pretends there is one.
          */
-        if (!cpu_has_apic &&
+        if (!boot_cpu_has(X86_FEATURE_APIC) &&
             APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
                 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
                         boot_cpu_physical_apicid);
@@ -2426,7 +2426,7 @@ static void apic_pm_activate(void)
 static int __init init_lapic_sysfs(void)
 {
         /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
-        if (cpu_has_apic)
+        if (boot_cpu_has(X86_FEATURE_APIC))
                 register_syscore_ops(&lapic_syscore_ops);
 
         return 0;
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
index 331a7a07c48f..13d19ed58514 100644
--- a/arch/x86/kernel/apic/apic_noop.c
+++ b/arch/x86/kernel/apic/apic_noop.c
@@ -100,13 +100,13 @@ static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask,
 
 static u32 noop_apic_read(u32 reg)
 {
-        WARN_ON_ONCE((cpu_has_apic && !disable_apic));
+        WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !disable_apic);
         return 0;
 }
 
 static void noop_apic_write(u32 reg, u32 v)
 {
-        WARN_ON_ONCE(cpu_has_apic && !disable_apic);
+        WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !disable_apic);
 }
 
 struct apic apic_noop = {
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
index 045e424fb368..7788ce643bf4 100644
--- a/arch/x86/kernel/apic/hw_nmi.c
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -18,7 +18,6 @@
 #include <linux/nmi.h>
 #include <linux/module.h>
 #include <linux/delay.h>
-#include <linux/seq_buf.h>
 
 #ifdef CONFIG_HARDLOCKUP_DETECTOR
 u64 hw_nmi_get_sample_period(int watchdog_thresh)
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index fdb0fbfb1197..84e33ff5a6d5 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1454,7 +1454,7 @@ void native_disable_io_apic(void)
                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
         }
 
-        if (cpu_has_apic || apic_from_smp_config())
+        if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
                 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
 }
 
diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c
index 28bde88b0085..2a0f225afebd 100644
--- a/arch/x86/kernel/apic/ipi.c
+++ b/arch/x86/kernel/apic/ipi.c
@@ -230,7 +230,7 @@ int safe_smp_processor_id(void)
 {
         int apicid, cpuid;
 
-        if (!cpu_has_apic)
+        if (!boot_cpu_has(X86_FEATURE_APIC))
                 return 0;
 
         apicid = hard_smp_processor_id();
diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
index ef495511f019..a5e400afc563 100644
--- a/arch/x86/kernel/apic/vector.c
+++ b/arch/x86/kernel/apic/vector.c
@@ -944,7 +944,7 @@ static int __init print_ICs(void)
         print_PIC();
 
         /* don't print out if apic is not there */
-        if (!cpu_has_apic && !apic_from_smp_config())
+        if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
                 return 0;
 
         print_local_APICs(show_lapic);
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 8f4942e2bcbb..29003154fafd 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -48,12 +48,35 @@ static u64 gru_start_paddr, gru_end_paddr;
 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
 static u64 gru_dist_lmask, gru_dist_umask;
 static union uvh_apicid uvh_apicid;
+
+/* info derived from CPUID */
+static struct {
+        unsigned int apicid_shift;
+        unsigned int apicid_mask;
+        unsigned int socketid_shift;    /* aka pnode_shift for UV1/2/3 */
+        unsigned int pnode_mask;
+        unsigned int gpa_shift;
+} uv_cpuid;
+
 int uv_min_hub_revision_id;
 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
 unsigned int uv_apicid_hibits;
 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
 
 static struct apic apic_x2apic_uv_x;
+static struct uv_hub_info_s uv_hub_info_node0;
+
+/* Set this to use hardware error handler instead of kernel panic */
+static int disable_uv_undefined_panic = 1;
+unsigned long uv_undefined(char *str)
+{
+        if (likely(!disable_uv_undefined_panic))
+                panic("UV: error: undefined MMR: %s\n", str);
+        else
+                pr_crit("UV: error: undefined MMR: %s\n", str);
+        return ~0ul;    /* cause a machine fault  */
+}
+EXPORT_SYMBOL(uv_undefined);
 
 static unsigned long __init uv_early_read_mmr(unsigned long addr)
 {
@@ -108,21 +131,71 @@ static int __init early_get_pnodeid(void)
         case UV3_HUB_PART_NUMBER_X:
                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
                 break;
+        case UV4_HUB_PART_NUMBER:
+                uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
+                break;
         }
 
         uv_hub_info->hub_revision = uv_min_hub_revision_id;
-        pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
+        uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
+        pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
+        uv_cpuid.gpa_shift = 46;        /* default unless changed */
+
+        pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
+                node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
+                m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
         return pnode;
 }
 
-static void __init early_get_apic_pnode_shift(void)
+/* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
+#define SMT_LEVEL       0       /* leaf 0xb SMT level */
+#define INVALID_TYPE    0       /* leaf 0xb sub-leaf types */
+#define SMT_TYPE        1
+#define CORE_TYPE       2
+#define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
+#define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
+
+static void set_x2apic_bits(void)
+{
+        unsigned int eax, ebx, ecx, edx, sub_index;
+        unsigned int sid_shift;
+
+        cpuid(0, &eax, &ebx, &ecx, &edx);
+        if (eax < 0xb) {
+                pr_info("UV: CPU does not have CPUID.11\n");
+                return;
+        }
+        cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
+        if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
+                pr_info("UV: CPUID.11 not implemented\n");
+                return;
+        }
+        sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
+        sub_index = 1;
+        do {
+                cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
+                if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
+                        sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
+                        break;
+                }
+                sub_index++;
+        } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
+        uv_cpuid.apicid_shift = 0;
+        uv_cpuid.apicid_mask = (~(-1 << sid_shift));
+        uv_cpuid.socketid_shift = sid_shift;
+}
+
+static void __init early_get_apic_socketid_shift(void)
 {
-        uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
-        if (!uvh_apicid.v)
-                /*
-                 * Old bios, use default value
-                 */
-                uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
+        if (is_uv2_hub() || is_uv3_hub())
+                uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
+
+        set_x2apic_bits();
+
+        pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
+                uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
+        pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
+                uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 }
 
 /*
@@ -150,13 +223,18 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
         if (strncmp(oem_id, "SGI", 3) != 0)
                 return 0;
 
+        /* Setup early hub type field in uv_hub_info for Node 0 */
+        uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
+
         /*
          * Determine UV arch type.
          *   SGI: UV100/1000
          *   SGI2: UV2000/3000
          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
+         *   SGI4: UV400 (truncated to 4 chars because of different varieties)
          */
         uv_hub_info->hub_revision =
+                !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
@@ -165,7 +243,7 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
                 goto badbios;
 
         pnodeid = early_get_pnodeid();
-        early_get_apic_pnode_shift();
+        early_get_apic_socketid_shift();
         x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
         x86_platform.nmi_init = uv_nmi_init;
 
@@ -211,17 +289,11 @@ int is_uv_system(void)
 }
 EXPORT_SYMBOL_GPL(is_uv_system);
 
-DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
-EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
-
-struct uv_blade_info *uv_blade_info;
-EXPORT_SYMBOL_GPL(uv_blade_info);
-
-short *uv_node_to_blade;
-EXPORT_SYMBOL_GPL(uv_node_to_blade);
+void **__uv_hub_info_list;
+EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 
-short *uv_cpu_to_blade;
-EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
+DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
+EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 
 short uv_possible_blades;
 EXPORT_SYMBOL_GPL(uv_possible_blades);
@@ -229,6 +301,115 @@ EXPORT_SYMBOL_GPL(uv_possible_blades);
 unsigned long sn_rtc_cycles_per_second;
 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 
+/* the following values are used for the per node hub info struct */
+static __initdata unsigned short *_node_to_pnode;
+static __initdata unsigned short _min_socket, _max_socket;
+static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
+static __initdata struct uv_gam_range_entry *uv_gre_table;
+static __initdata struct uv_gam_parameters *uv_gp_table;
+static __initdata unsigned short *_socket_to_node;
+static __initdata unsigned short *_socket_to_pnode;
+static __initdata unsigned short *_pnode_to_socket;
+static __initdata struct uv_gam_range_s *_gr_table;
+#define SOCK_EMPTY      ((unsigned short)~0)
+
+extern int uv_hub_info_version(void)
+{
+        return UV_HUB_INFO_VERSION;
+}
+EXPORT_SYMBOL(uv_hub_info_version);
+
+/* Build GAM range lookup table */
+static __init void build_uv_gr_table(void)
+{
+        struct uv_gam_range_entry *gre = uv_gre_table;
+        struct uv_gam_range_s *grt;
+        unsigned long last_limit = 0, ram_limit = 0;
+        int bytes, i, sid, lsid = -1;
+
+        if (!gre)
+                return;
+
+        bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
+        grt = kzalloc(bytes, GFP_KERNEL);
+        BUG_ON(!grt);
+        _gr_table = grt;
+
+        for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
+                if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
+                        if (!ram_limit) {   /* mark hole between ram/non-ram */
+                                ram_limit = last_limit;
+                                last_limit = gre->limit;
+                                lsid++;
+                                continue;
+                        }
+                        last_limit = gre->limit;
+                        pr_info("UV: extra hole in GAM RE table @%d\n",
+                                (int)(gre - uv_gre_table));
+                        continue;
+                }
+                if (_max_socket < gre->sockid) {
+                        pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
+                                gre->sockid, _max_socket,
+                                (int)(gre - uv_gre_table));
+                        continue;
+                }
+                sid = gre->sockid - _min_socket;
+                if (lsid < sid) {               /* new range */
+                        grt = &_gr_table[sid];
+                        grt->base = lsid;
+                        grt->nasid = gre->nasid;
+                        grt->limit = last_limit = gre->limit;
+                        lsid = sid;
+                        continue;
+                }
+                if (lsid == sid && !ram_limit) {        /* update range */
+                        if (grt->limit == last_limit) { /* .. if contiguous */
+                                grt->limit = last_limit = gre->limit;
+                                continue;
+                        }
+                }
+                if (!ram_limit) {               /* non-contiguous ram range */
+                        grt++;
+                        grt->base = sid - 1;
+                        grt->nasid = gre->nasid;
+                        grt->limit = last_limit = gre->limit;
+                        continue;
+                }
+                grt++;                          /* non-contiguous/non-ram */
+                grt->base = grt - _gr_table;    /* base is this entry */
+                grt->nasid = gre->nasid;
+                grt->limit = last_limit = gre->limit;
+                lsid++;
+        }
+
+        /* shorten table if possible */
+        grt++;
+        i = grt - _gr_table;
+        if (i < _gr_table_len) {
+                void *ret;
+
+                bytes = i * sizeof(struct uv_gam_range_s);
+                ret = krealloc(_gr_table, bytes, GFP_KERNEL);
+                if (ret) {
+                        _gr_table = ret;
+                        _gr_table_len = i;
+                }
+        }
+
+        /* display resultant gam range table */
+        for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
+                int gb = grt->base;
+                unsigned long start = gb < 0 ?  0 :
+                        (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
+                unsigned long end =
+                        (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
+
+                pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
+                        i, grt->nasid, start, end, gb);
+        }
+}
+
 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 {
         unsigned long val;
@@ -355,7 +536,6 @@ static unsigned long set_apic_id(unsigned int id)
 
 static unsigned int uv_read_apic_id(void)
 {
-
         return x2apic_get_apic_id(apic_read(APIC_ID));
 }
 
@@ -430,58 +610,38 @@ static void set_x2apic_extra_bits(int pnode)
         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 }
 
-/*
- * Called on boot cpu.
- */
-static __init int boot_pnode_to_blade(int pnode)
-{
-        int blade;
-
-        for (blade = 0; blade < uv_num_possible_blades(); blade++)
-                if (pnode == uv_blade_info[blade].pnode)
-                        return blade;
-        BUG();
-}
-
-struct redir_addr {
-        unsigned long redirect;
-        unsigned long alias;
-};
-
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
-static __initdata struct redir_addr redir_addrs[] = {
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
-};
-
-static unsigned char get_n_lshift(int m_val)
-{
-        union uv3h_gr0_gam_gr_config_u m_gr_config;
-
-        if (is_uv1_hub())
-                return m_val;
-
-        if (is_uv2_hub())
-                return m_val == 40 ? 40 : 39;
-
-        m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
-        return m_gr_config.s3.m_skt;
-}
-
 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 {
         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
+        unsigned long m_redirect;
+        unsigned long m_overlay;
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
-                alias.v = uv_read_local_mmr(redir_addrs[i].alias);
+        for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
+                switch (i) {
+                case 0:
+                        m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
+                        m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
+                        break;
+                case 1:
+                        m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
+                        m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
+                        break;
+                case 2:
+                        m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
+                        m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
+                        break;
+                }
+                alias.v = uv_read_local_mmr(m_overlay);
                 if (alias.s.enable && alias.s.base == 0) {
                         *size = (1UL << alias.s.m_alias);
-                        redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
-                        *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
+                        redirect.v = uv_read_local_mmr(m_redirect);
+                        *base = (unsigned long)redirect.s.dest_base
+                                                        << DEST_SHIFT;
                         return;
                 }
         }
@@ -544,6 +704,8 @@ static __init void map_gru_high(int max_pnode)
 {
         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
+        unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
+        unsigned long base;
 
         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
         if (!gru.s.enable) {
@@ -555,8 +717,9 @@ static __init void map_gru_high(int max_pnode)
                 map_gru_distributed(gru.v);
                 return;
         }
-        map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
-        gru_start_paddr = ((u64)gru.s.base << shift);
+        base = (gru.v & mask) >> shift;
+        map_high("GRU", base, shift, shift, max_pnode, map_wb);
+        gru_start_paddr = ((u64)base << shift);
         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 }
 
@@ -595,6 +758,7 @@ static __initdata struct mmioh_config mmiohs[] = {
         },
 };
 
+/* UV3 & UV4 have identical MMIOH overlay configs */
 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 {
         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
@@ -674,7 +838,7 @@ static __init void map_mmioh_high(int min_pnode, int max_pnode)
         unsigned long mmr, base;
         int shift, enable, m_io, n_io;
 
-        if (is_uv3_hub()) {
+        if (is_uv3_hub() || is_uv4_hub()) {
                 /* Map both MMIOH Regions */
                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
@@ -739,8 +903,8 @@ static __init void uv_rtc_init(void)
  */
 static void uv_heartbeat(unsigned long ignored)
 {
-        struct timer_list *timer = &uv_hub_info->scir.timer;
-        unsigned char bits = uv_hub_info->scir.state;
+        struct timer_list *timer = &uv_scir_info->timer;
+        unsigned char bits = uv_scir_info->state;
 
         /* flip heartbeat bit */
         bits ^= SCIR_CPU_HEARTBEAT;
@@ -760,14 +924,14 @@ static void uv_heartbeat(unsigned long ignored)
 
 static void uv_heartbeat_enable(int cpu)
 {
-        while (!uv_cpu_hub_info(cpu)->scir.enabled) {
-                struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
+        while (!uv_cpu_scir_info(cpu)->enabled) {
+                struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
 
                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
                 setup_timer(timer, uv_heartbeat, cpu);
                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
                 add_timer_on(timer, cpu);
-                uv_cpu_hub_info(cpu)->scir.enabled = 1;
+                uv_cpu_scir_info(cpu)->enabled = 1;
 
                 /* also ensure that boot cpu is enabled */
                 cpu = 0;
@@ -777,9 +941,9 @@ static void uv_heartbeat_enable(int cpu)
 #ifdef CONFIG_HOTPLUG_CPU
 static void uv_heartbeat_disable(int cpu)
 {
-        if (uv_cpu_hub_info(cpu)->scir.enabled) {
-                uv_cpu_hub_info(cpu)->scir.enabled = 0;
-                del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
+        if (uv_cpu_scir_info(cpu)->enabled) {
+                uv_cpu_scir_info(cpu)->enabled = 0;
+                del_timer(&uv_cpu_scir_info(cpu)->timer);
         }
         uv_set_cpu_scir_bits(cpu, 0xff);
 }
@@ -862,157 +1026,475 @@ int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 void uv_cpu_init(void)
 {
         /* CPU 0 initialization will be done via uv_system_init. */
-        if (!uv_blade_info)
+        if (smp_processor_id() == 0)
                 return;
 
-        uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
+        uv_hub_info->nr_online_cpus++;
 
         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
                 set_x2apic_extra_bits(uv_hub_info->pnode);
 }
 
-void __init uv_system_init(void)
+struct mn {
+        unsigned char   m_val;
+        unsigned char   n_val;
+        unsigned char   m_shift;
+        unsigned char   n_lshift;
+};
+
+static void get_mn(struct mn *mnp)
 {
-        union uvh_rh_gam_config_mmr_u  m_n_config;
-        union uvh_node_id_u node_id;
-        unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
-        int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
-        int gnode_extra, min_pnode = 999999, max_pnode = -1;
-        unsigned long mmr_base, present, paddr;
-        unsigned short pnode_mask;
-        unsigned char n_lshift;
-        char *hub = (is_uv1_hub() ? "UV100/1000" :
-                    (is_uv2_hub() ? "UV2000/3000" :
-                    (is_uv3_hub() ? "UV300" : NULL)));
+        union uvh_rh_gam_config_mmr_u m_n_config;
+        union uv3h_gr0_gam_gr_config_u m_gr_config;
 
-        if (!hub) {
-                pr_err("UV: Unknown/unsupported UV hub\n");
-                return;
+        m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
+        mnp->n_val = m_n_config.s.n_skt;
+        if (is_uv4_hub()) {
+                mnp->m_val = 0;
+                mnp->n_lshift = 0;
+        } else if (is_uv3_hub()) {
+                mnp->m_val = m_n_config.s3.m_skt;
+                m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
+                mnp->n_lshift = m_gr_config.s3.m_skt;
+        } else if (is_uv2_hub()) {
+                mnp->m_val = m_n_config.s2.m_skt;
+                mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
+        } else if (is_uv1_hub()) {
+                mnp->m_val = m_n_config.s1.m_skt;
+                mnp->n_lshift = mnp->m_val;
         }
-        pr_info("UV: Found %s hub\n", hub);
+        mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
+}
 
-        /* We now only need to map the MMRs on UV1 */
-        if (is_uv1_hub())
-                map_low_mmrs();
+void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
+{
+        struct mn mn = {0};     /* avoid unitialized warnings */
+        union uvh_node_id_u node_id;
 
-        m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
-        m_val = m_n_config.s.m_skt;
-        n_val = m_n_config.s.n_skt;
-        pnode_mask = (1 << n_val) - 1;
-        n_lshift = get_n_lshift(m_val);
-        mmr_base =
-            uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
-            ~UV_MMR_ENABLE;
+        get_mn(&mn);
+        hub_info->m_val = mn.m_val;
+        hub_info->n_val = mn.n_val;
+        hub_info->m_shift = mn.m_shift;
+        hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
+
+        hub_info->hub_revision = uv_hub_info->hub_revision;
+        hub_info->pnode_mask = uv_cpuid.pnode_mask;
+        hub_info->min_pnode = _min_pnode;
+        hub_info->min_socket = _min_socket;
+        hub_info->pnode_to_socket = _pnode_to_socket;
+        hub_info->socket_to_node = _socket_to_node;
+        hub_info->socket_to_pnode = _socket_to_pnode;
+        hub_info->gr_table_len = _gr_table_len;
+        hub_info->gr_table = _gr_table;
+        hub_info->gpa_mask = mn.m_val ?
+                (1UL << (mn.m_val + mn.n_val)) - 1 :
+                (1UL << uv_cpuid.gpa_shift) - 1;
 
         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
-        gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
-        gnode_upper = ((unsigned long)gnode_extra  << m_val);
-        pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
-                        n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
-                        n_lshift);
+        hub_info->gnode_extra =
+                (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1;
+
+        hub_info->gnode_upper =
+                ((unsigned long)hub_info->gnode_extra << mn.m_val);
+
+        if (uv_gp_table) {
+                hub_info->global_mmr_base = uv_gp_table->mmr_base;
+                hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
+                hub_info->global_gru_base = uv_gp_table->gru_base;
+                hub_info->global_gru_shift = uv_gp_table->gru_shift;
+                hub_info->gpa_shift = uv_gp_table->gpa_shift;
+                hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
+        } else {
+                hub_info->global_mmr_base =
+                        uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
+                                        ~UV_MMR_ENABLE;
+                hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
+        }
 
-        pr_info("UV: global MMR base 0x%lx\n", mmr_base);
+        get_lowmem_redirect(
+                &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
 
-        for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
-                uv_possible_blades +=
-                  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
+        hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
 
-        /* uv_num_possible_blades() is really the hub count */
-        pr_info("UV: Found %d blades, %d hubs\n",
-                        is_uv1_hub() ? uv_num_possible_blades() :
-                        (uv_num_possible_blades() + 1) / 2,
-                        uv_num_possible_blades());
+        /* show system specific info */
+        pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
+                hub_info->n_val, hub_info->m_val,
+                hub_info->m_shift, hub_info->n_lshift);
 
-        bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
-        uv_blade_info = kzalloc(bytes, GFP_KERNEL);
-        BUG_ON(!uv_blade_info);
+        pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
+                hub_info->gpa_mask, hub_info->gpa_shift,
+                hub_info->pnode_mask, hub_info->apic_pnode_shift);
 
-        for (blade = 0; blade < uv_num_possible_blades(); blade++)
-                uv_blade_info[blade].memory_nid = -1;
+        pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
+                hub_info->global_mmr_base, hub_info->global_mmr_shift,
+                hub_info->global_gru_base, hub_info->global_gru_shift);
 
-        get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
+        pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
+                hub_info->gnode_upper, hub_info->gnode_extra);
+}
+
+static void __init decode_gam_params(unsigned long ptr)
+{
+        uv_gp_table = (struct uv_gam_parameters *)ptr;
+
+        pr_info("UV: GAM Params...\n");
+        pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
+                uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
+                uv_gp_table->gru_base, uv_gp_table->gru_shift,
+                uv_gp_table->gpa_shift);
+}
+
+static void __init decode_gam_rng_tbl(unsigned long ptr)
+{
+        struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
+        unsigned long lgre = 0;
+        int index = 0;
+        int sock_min = 999999, pnode_min = 99999;
+        int sock_max = -1, pnode_max = -1;
+
+        uv_gre_table = gre;
+        for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
+                if (!index) {
+                        pr_info("UV: GAM Range Table...\n");
+                        pr_info("UV:  # %20s %14s %5s %4s %5s %3s %2s %3s\n",
+                                "Range", "", "Size", "Type", "NASID",
+                                "SID", "PN", "PXM");
+                }
+                pr_info(
+                "UV: %2d: 0x%014lx-0x%014lx %5luG %3d   %04x  %02x %02x %3d\n",
+                        index++,
+                        (unsigned long)lgre << UV_GAM_RANGE_SHFT,
+                        (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
+                        ((unsigned long)(gre->limit - lgre)) >>
+                                (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
+                        gre->type, gre->nasid, gre->sockid,
+                        gre->pnode, gre->pxm);
+
+                lgre = gre->limit;
+                if (sock_min > gre->sockid)
+                        sock_min = gre->sockid;
+                if (sock_max < gre->sockid)
+                        sock_max = gre->sockid;
+                if (pnode_min > gre->pnode)
+                        pnode_min = gre->pnode;
+                if (pnode_max < gre->pnode)
+                        pnode_max = gre->pnode;
+        }
+        _min_socket = sock_min;
+        _max_socket = sock_max;
+        _min_pnode = pnode_min;
+        _max_pnode = pnode_max;
+        _gr_table_len = index;
+        pr_info(
+        "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
+                index, _min_socket, _max_socket, _min_pnode, _max_pnode);
+}
+
+static void __init decode_uv_systab(void)
+{
+        struct uv_systab *st;
+        int i;
+
+        st = uv_systab;
+        if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub())
+                return;
+        if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) {
+                pr_crit(
+                "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
+                        st->revision, UV_SYSTAB_VERSION_UV4_LATEST);
+                BUG();
+        }
+
+        for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
+                unsigned long ptr = st->entry[i].offset;
 
-        bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
-        uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
-        BUG_ON(!uv_node_to_blade);
-        memset(uv_node_to_blade, 255, bytes);
+                if (!ptr)
+                        continue;
+
+                ptr = ptr + (unsigned long)st;
 
-        bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
-        uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
-        BUG_ON(!uv_cpu_to_blade);
-        memset(uv_cpu_to_blade, 255, bytes);
+                switch (st->entry[i].type) {
+                case UV_SYSTAB_TYPE_GAM_PARAMS:
+                        decode_gam_params(ptr);
+                        break;
 
-        blade = 0;
+                case UV_SYSTAB_TYPE_GAM_RNG_TBL:
+                        decode_gam_rng_tbl(ptr);
+                        break;
+                }
+        }
+}
+
+/*
+ * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
+ * .. NB: UVH_NODE_PRESENT_TABLE is going away,
+ * .. being replaced by GAM Range Table
+ */
+static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
+{
+        int i, uv_pb = 0;
+
+        pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
-                present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
-                for (j = 0; j < 64; j++) {
-                        if (!test_bit(j, &present))
-                                continue;
-                        pnode = (i * 64 + j) & pnode_mask;
-                        uv_blade_info[blade].pnode = pnode;
-                        uv_blade_info[blade].nr_possible_cpus = 0;
-                        uv_blade_info[blade].nr_online_cpus = 0;
-                        spin_lock_init(&uv_blade_info[blade].nmi_lock);
-                        min_pnode = min(pnode, min_pnode);
-                        max_pnode = max(pnode, max_pnode);
-                        blade++;
+                unsigned long np;
+
+                np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
+                if (np)
+                        pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
+
+                uv_pb += hweight64(np);
+        }
+        if (uv_possible_blades != uv_pb)
+                uv_possible_blades = uv_pb;
+}
+
+static void __init build_socket_tables(void)
+{
+        struct uv_gam_range_entry *gre = uv_gre_table;
+        int num, nump;
+        int cpu, i, lnid;
+        int minsock = _min_socket;
+        int maxsock = _max_socket;
+        int minpnode = _min_pnode;
+        int maxpnode = _max_pnode;
+        size_t bytes;
+
+        if (!gre) {
+                if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
+                        pr_info("UV: No UVsystab socket table, ignoring\n");
+                        return;         /* not required */
+                }
+                pr_crit(
+                "UV: Error: UVsystab address translations not available!\n");
+                BUG();
+        }
+
+        /* build socket id -> node id, pnode */
+        num = maxsock - minsock + 1;
+        bytes = num * sizeof(_socket_to_node[0]);
+        _socket_to_node = kmalloc(bytes, GFP_KERNEL);
+        _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
+
+        nump = maxpnode - minpnode + 1;
+        bytes = nump * sizeof(_pnode_to_socket[0]);
+        _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
+        BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
+
+        for (i = 0; i < num; i++)
+                _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
+
+        for (i = 0; i < nump; i++)
+                _pnode_to_socket[i] = SOCK_EMPTY;
+
+        /* fill in pnode/node/addr conversion list values */
+        pr_info("UV: GAM Building socket/pnode/pxm conversion tables\n");
+        for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
+                if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
+                        continue;
+                i = gre->sockid - minsock;
+                if (_socket_to_pnode[i] != SOCK_EMPTY)
+                        continue;       /* duplicate */
+                _socket_to_pnode[i] = gre->pnode;
+                _socket_to_node[i] = gre->pxm;
+
+                i = gre->pnode - minpnode;
+                _pnode_to_socket[i] = gre->sockid;
+
+                pr_info(
+                "UV: sid:%02x type:%d nasid:%04x pn:%02x pxm:%2d pn2s:%2x\n",
+                        gre->sockid, gre->type, gre->nasid,
+                        _socket_to_pnode[gre->sockid - minsock],
+                        _socket_to_node[gre->sockid - minsock],
+                        _pnode_to_socket[gre->pnode - minpnode]);
+        }
+
+        /* check socket -> node values */
+        lnid = -1;
+        for_each_present_cpu(cpu) {
+                int nid = cpu_to_node(cpu);
+                int apicid, sockid;
+
+                if (lnid == nid)
+                        continue;
+                lnid = nid;
+                apicid = per_cpu(x86_cpu_to_apicid, cpu);
+                sockid = apicid >> uv_cpuid.socketid_shift;
+                i = sockid - minsock;
+
+                if (nid != _socket_to_node[i]) {
+                        pr_warn(
+                        "UV: %02x: type:%d socket:%02x PXM:%02x != node:%2d\n",
+                                i, sockid, gre->type, _socket_to_node[i], nid);
+                        _socket_to_node[i] = nid;
+                }
+        }
+
+        /* Setup physical blade to pnode translation from GAM Range Table */
+        bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
+        _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
+        BUG_ON(!_node_to_pnode);
+
+        for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
+                unsigned short sockid;
+
+                for (sockid = minsock; sockid <= maxsock; sockid++) {
+                        if (lnid == _socket_to_node[sockid - minsock]) {
+                                _node_to_pnode[lnid] =
+                                        _socket_to_pnode[sockid - minsock];
+                                break;
+                        }
+                }
+                if (sockid > maxsock) {
+                        pr_err("UV: socket for node %d not found!\n", lnid);
+                        BUG();
+                }
+        }
+
+        /*
+         * If socket id == pnode or socket id == node for all nodes,
+         *   system runs faster by removing corresponding conversion table.
+         */
+        pr_info("UV: Checking socket->node/pnode for identity maps\n");
+        if (minsock == 0) {
+                for (i = 0; i < num; i++)
+                        if (_socket_to_node[i] == SOCK_EMPTY ||
+                                i != _socket_to_node[i])
+                                break;
+                if (i >= num) {
+                        kfree(_socket_to_node);
+                        _socket_to_node = NULL;
+                        pr_info("UV: 1:1 socket_to_node table removed\n");
                 }
         }
+        if (minsock == minpnode) {
+                for (i = 0; i < num; i++)
+                        if (_socket_to_pnode[i] != SOCK_EMPTY &&
+                                _socket_to_pnode[i] != i + minpnode)
+                                break;
+                if (i >= num) {
+                        kfree(_socket_to_pnode);
+                        _socket_to_pnode = NULL;
+                        pr_info("UV: 1:1 socket_to_pnode table removed\n");
+                }
+        }
+}
+
+void __init uv_system_init(void)
+{
+        struct uv_hub_info_s hub_info = {0};
+        int bytes, cpu, nodeid;
+        unsigned short min_pnode = 9999, max_pnode = 0;
+        char *hub = is_uv4_hub() ? "UV400" :
+                    is_uv3_hub() ? "UV300" :
+                    is_uv2_hub() ? "UV2000/3000" :
+                    is_uv1_hub() ? "UV100/1000" : NULL;
+
+        if (!hub) {
+                pr_err("UV: Unknown/unsupported UV hub\n");
+                return;
+        }
+        pr_info("UV: Found %s hub\n", hub);
+
+        map_low_mmrs();
+
+        uv_bios_init();                 /* get uv_systab for decoding */
+        decode_uv_systab();
+        build_socket_tables();
+        build_uv_gr_table();
+        uv_init_hub_info(&hub_info);
+        uv_possible_blades = num_possible_nodes();
+        if (!_node_to_pnode)
+                boot_init_possible_blades(&hub_info);
+
+        /* uv_num_possible_blades() is really the hub count */
+        pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
+                        uv_num_possible_blades(),
+                        num_possible_nodes(),
+                        num_possible_cpus());
 
-        uv_bios_init();
         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
                             &sn_region_size, &system_serial_number);
+        hub_info.coherency_domain_number = sn_coherency_id;
         uv_rtc_init();
 
-        for_each_present_cpu(cpu) {
-                int apicid = per_cpu(x86_cpu_to_apicid, cpu);
+        bytes = sizeof(void *) * uv_num_possible_blades();
+        __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
+        BUG_ON(!__uv_hub_info_list);
 
-                nid = cpu_to_node(cpu);
-                /*
-                 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
-                 */
-                uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
-                uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
-                uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
+        bytes = sizeof(struct uv_hub_info_s);
+        for_each_node(nodeid) {
+                struct uv_hub_info_s *new_hub;
 
-                uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
-                uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
+                if (__uv_hub_info_list[nodeid]) {
+                        pr_err("UV: Node %d UV HUB already initialized!?\n",
+                                nodeid);
+                        BUG();
+                }
+
+                /* Allocate new per hub info list */
+                new_hub = (nodeid == 0) ?
+                        &uv_hub_info_node0 :
+                        kzalloc_node(bytes, GFP_KERNEL, nodeid);
+                BUG_ON(!new_hub);
+                __uv_hub_info_list[nodeid] = new_hub;
+                new_hub = uv_hub_info_list(nodeid);
+                BUG_ON(!new_hub);
+                *new_hub = hub_info;
+
+                /* Use information from GAM table if available */
+                if (_node_to_pnode)
+                        new_hub->pnode = _node_to_pnode[nodeid];
+                else    /* Fill in during cpu loop */
+                        new_hub->pnode = 0xffff;
+                new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
+                new_hub->memory_nid = -1;
+                new_hub->nr_possible_cpus = 0;
+                new_hub->nr_online_cpus = 0;
+        }
 
+        /* Initialize per cpu info */
+        for_each_possible_cpu(cpu) {
+                int apicid = per_cpu(x86_cpu_to_apicid, cpu);
+                int numa_node_id;
+                unsigned short pnode;
+
+                nodeid = cpu_to_node(cpu);
+                numa_node_id = numa_cpu_node(cpu);
                 pnode = uv_apicid_to_pnode(apicid);
-                blade = boot_pnode_to_blade(pnode);
-                lcpu = uv_blade_info[blade].nr_possible_cpus;
-                uv_blade_info[blade].nr_possible_cpus++;
-
-                /* Any node on the blade, else will contain -1. */
-                uv_blade_info[blade].memory_nid = nid;
-
-                uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
-                uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
-                uv_cpu_hub_info(cpu)->m_val = m_val;
-                uv_cpu_hub_info(cpu)->n_val = n_val;
-                uv_cpu_hub_info(cpu)->numa_blade_id = blade;
-                uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
-                uv_cpu_hub_info(cpu)->pnode = pnode;
-                uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
-                uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
-                uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
-                uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
-                uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
-                uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
-                uv_node_to_blade[nid] = blade;
-                uv_cpu_to_blade[cpu] = blade;
+
+                uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
+                uv_cpu_info_per(cpu)->blade_cpu_id =
+                        uv_cpu_hub_info(cpu)->nr_possible_cpus++;
+                if (uv_cpu_hub_info(cpu)->memory_nid == -1)
+                        uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
+                if (nodeid != numa_node_id &&   /* init memoryless node */
+                    uv_hub_info_list(numa_node_id)->pnode == 0xffff)
+                        uv_hub_info_list(numa_node_id)->pnode = pnode;
+                else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
+                        uv_cpu_hub_info(cpu)->pnode = pnode;
+                uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
         }
 
-        /* Add blade/pnode info for nodes without cpus */
-        for_each_online_node(nid) {
-                if (uv_node_to_blade[nid] >= 0)
-                        continue;
-                paddr = node_start_pfn(nid) << PAGE_SHIFT;
-                pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
-                blade = boot_pnode_to_blade(pnode);
-                uv_node_to_blade[nid] = blade;
+        for_each_node(nodeid) {
+                unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
+
+                /* Add pnode info for pre-GAM list nodes without cpus */
+                if (pnode == 0xffff) {
+                        unsigned long paddr;
+
+                        paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
+                        pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
+                        uv_hub_info_list(nodeid)->pnode = pnode;
+                }
+                min_pnode = min(pnode, min_pnode);
+                max_pnode = max(pnode, max_pnode);
+                pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
+                        nodeid,
+                        uv_hub_info_list(nodeid)->pnode,
+                        uv_hub_info_list(nodeid)->nr_possible_cpus);
         }
 
+        pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
         map_gru_high(max_pnode);
         map_mmr_high(max_pnode);
         map_mmioh_high(min_pnode, max_pnode);
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 9307f182fe30..c7364bd633e1 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -2267,7 +2267,7 @@ static int __init apm_init(void)
 
         dmi_check_system(apm_dmi_table);
 
-        if (apm_info.bios.version == 0 || paravirt_enabled() || machine_is_olpc()) {
+        if (apm_info.bios.version == 0 || machine_is_olpc()) {
                 printk(KERN_INFO "apm: BIOS not found.\n");
                 return -ENODEV;
         }
diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c
index 5c042466f274..674134e9f5e5 100644
--- a/arch/x86/kernel/asm-offsets.c
+++ b/arch/x86/kernel/asm-offsets.c
@@ -80,6 +80,7 @@ void common(void) {
         OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch);
         OFFSET(BP_version, boot_params, hdr.version);
         OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment);
+        OFFSET(BP_init_size, boot_params, hdr.init_size);
         OFFSET(BP_pref_address, boot_params, hdr.pref_address);
         OFFSET(BP_code32_start, boot_params, hdr.code32_start);
 
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 2fec875392cc..c343a54bed39 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -565,14 +565,17 @@ static void early_init_amd(struct cpuinfo_x86 *c)
          * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
          * after 16h.
          */
-        if (cpu_has_apic && c->x86 > 0x16) {
-                set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
-        } else if (cpu_has_apic && c->x86 >= 0xf) {
-                /* check CPU config space for extended APIC ID */
-                unsigned int val;
-                val = read_pci_config(0, 24, 0, 0x68);
-                if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
+        if (boot_cpu_has(X86_FEATURE_APIC)) {
+                if (c->x86 > 0x16)
                         set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
+                else if (c->x86 >= 0xf) {
+                        /* check CPU config space for extended APIC ID */
+                        unsigned int val;
+
+                        val = read_pci_config(0, 24, 0, 0x68);
+                        if ((val >> 17 & 0x3) == 0x3)
+                                set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
+                }
         }
 #endif
 
@@ -628,6 +631,7 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
          */
         msr_set_bit(MSR_K7_HWCR, 6);
 #endif
+        set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
 }
 
 static void init_amd_gh(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8394b3d1f94f..0fe6953f421c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -37,6 +37,7 @@
 #include <asm/mtrr.h>
 #include <linux/numa.h>
 #include <asm/asm.h>
+#include <asm/bugs.h>
 #include <asm/cpu.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
@@ -270,6 +271,8 @@ static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 static __init int setup_disable_smep(char *arg)
 {
         setup_clear_cpu_cap(X86_FEATURE_SMEP);
+        /* Check for things that depend on SMEP being enabled: */
+        check_mpx_erratum(&boot_cpu_data);
         return 1;
 }
 __setup("nosmep", setup_disable_smep);
@@ -310,6 +313,10 @@ static bool pku_disabled;
 
 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
 {
+        /* check the boot processor, plus compile options for PKU: */
+        if (!cpu_feature_enabled(X86_FEATURE_PKU))
+                return;
+        /* checks the actual processor's cpuid bits: */
         if (!cpu_has(c, X86_FEATURE_PKU))
                 return;
         if (pku_disabled)
@@ -430,7 +437,7 @@ void load_percpu_segment(int cpu)
 #ifdef CONFIG_X86_32
         loadsegment(fs, __KERNEL_PERCPU);
 #else
-        loadsegment(gs, 0);
+        __loadsegment_simple(gs, 0);
         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
 #endif
         load_stack_canary_segment();
@@ -717,6 +724,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
                 }
         }
 
+        if (c->extended_cpuid_level >= 0x80000007) {
+                cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
+
+                c->x86_capability[CPUID_8000_0007_EBX] = ebx;
+                c->x86_power = edx;
+        }
+
         if (c->extended_cpuid_level >= 0x80000008) {
                 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
 
@@ -729,9 +743,6 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
                 c->x86_phys_bits = 36;
 #endif
 
-        if (c->extended_cpuid_level >= 0x80000007)
-                c->x86_power = cpuid_edx(0x80000007);
-
         if (c->extended_cpuid_level >= 0x8000000a)
                 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
 
@@ -862,30 +873,34 @@ static void detect_nopl(struct cpuinfo_x86 *c)
 #else
         set_cpu_cap(c, X86_FEATURE_NOPL);
 #endif
+}
 
+static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_64
         /*
-         * ESPFIX is a strange bug.  All real CPUs have it.  Paravirt
-         * systems that run Linux at CPL > 0 may or may not have the
-         * issue, but, even if they have the issue, there's absolutely
-         * nothing we can do about it because we can't use the real IRET
-         * instruction.
+         * Empirically, writing zero to a segment selector on AMD does
+         * not clear the base, whereas writing zero to a segment
+         * selector on Intel does clear the base.  Intel's behavior
+         * allows slightly faster context switches in the common case
+         * where GS is unused by the prev and next threads.
          *
-         * NB: For the time being, only 32-bit kernels support
-         * X86_BUG_ESPFIX as such.  64-bit kernels directly choose
-         * whether to apply espfix using paravirt hooks.  If any
-         * non-paravirt system ever shows up that does *not* have the
-         * ESPFIX issue, we can change this.
+         * Since neither vendor documents this anywhere that I can see,
+         * detect it directly instead of hardcoding the choice by
+         * vendor.
+         *
+         * I've designated AMD's behavior as the "bug" because it's
+         * counterintuitive and less friendly.
          */
-#ifdef CONFIG_X86_32
-#ifdef CONFIG_PARAVIRT
-        do {
-                extern void native_iret(void);
-                if (pv_cpu_ops.iret == native_iret)
-                        set_cpu_bug(c, X86_BUG_ESPFIX);
-        } while (0);
-#else
-        set_cpu_bug(c, X86_BUG_ESPFIX);
-#endif
+
+        unsigned long old_base, tmp;
+        rdmsrl(MSR_FS_BASE, old_base);
+        wrmsrl(MSR_FS_BASE, 1);
+        loadsegment(fs, 0);
+        rdmsrl(MSR_FS_BASE, tmp);
+        if (tmp != 0)
+                set_cpu_bug(c, X86_BUG_NULL_SEG);
+        wrmsrl(MSR_FS_BASE, old_base);
 #endif
 }
 
@@ -921,6 +936,33 @@ static void generic_identify(struct cpuinfo_x86 *c)
         get_model_name(c); /* Default name */
 
         detect_nopl(c);
+
+        detect_null_seg_behavior(c);
+
+        /*
+         * ESPFIX is a strange bug.  All real CPUs have it.  Paravirt
+         * systems that run Linux at CPL > 0 may or may not have the
+         * issue, but, even if they have the issue, there's absolutely
+         * nothing we can do about it because we can't use the real IRET
+         * instruction.
+         *
+         * NB: For the time being, only 32-bit kernels support
+         * X86_BUG_ESPFIX as such.  64-bit kernels directly choose
+         * whether to apply espfix using paravirt hooks.  If any
+         * non-paravirt system ever shows up that does *not* have the
+         * ESPFIX issue, we can change this.
+         */
+#ifdef CONFIG_X86_32
+# ifdef CONFIG_PARAVIRT
+        do {
+                extern void native_iret(void);
+                if (pv_cpu_ops.iret == native_iret)
+                        set_cpu_bug(c, X86_BUG_ESPFIX);
+        } while (0);
+# else
+        set_cpu_bug(c, X86_BUG_ESPFIX);
+# endif
+#endif
 }
 
 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
@@ -1076,12 +1118,12 @@ void enable_sep_cpu(void)
         struct tss_struct *tss;
         int cpu;
 
+        if (!boot_cpu_has(X86_FEATURE_SEP))
+                return;
+
         cpu = get_cpu();
         tss = &per_cpu(cpu_tss, cpu);
 
-        if (!boot_cpu_has(X86_FEATURE_SEP))
-                goto out;
-
         /*
          * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
          * see the big comment in struct x86_hw_tss's definition.
@@ -1096,7 +1138,6 @@ void enable_sep_cpu(void)
 
         wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
 
-out:
         put_cpu();
 }
 #endif
@@ -1528,7 +1569,7 @@ void cpu_init(void)
         pr_info("Initializing CPU#%d\n", cpu);
 
         if (cpu_feature_enabled(X86_FEATURE_VME) ||
-            cpu_has_tsc ||
+            boot_cpu_has(X86_FEATURE_TSC) ||
             boot_cpu_has(X86_FEATURE_DE))
                 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 6adef9cac23e..bd9dcd6b712d 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -333,7 +333,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
                 switch (dir0_lsn) {
                 case 0xd:  /* either a 486SLC or DLC w/o DEVID */
                         dir0_msn = 0;
-                        p = Cx486_name[(cpu_has_fpu ? 1 : 0)];
+                        p = Cx486_name[!!boot_cpu_has(X86_FEATURE_FPU)];
                         break;
 
                 case 0xe:  /* a 486S A step */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5354080f76c3..c1a89bc026ac 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -25,6 +25,41 @@
 #include <asm/apic.h>
 #endif
 
+/*
+ * Just in case our CPU detection goes bad, or you have a weird system,
+ * allow a way to override the automatic disabling of MPX.
+ */
+static int forcempx;
+
+static int __init forcempx_setup(char *__unused)
+{
+        forcempx = 1;
+
+        return 1;
+}
+__setup("intel-skd-046-workaround=disable", forcempx_setup);
+
+void check_mpx_erratum(struct cpuinfo_x86 *c)
+{
+        if (forcempx)
+                return;
+        /*
+         * Turn off the MPX feature on CPUs where SMEP is not
+         * available or disabled.
+         *
+         * Works around Intel Erratum SKD046: "Branch Instructions
+         * May Initialize MPX Bound Registers Incorrectly".
+         *
+         * This might falsely disable MPX on systems without
+         * SMEP, like Atom processors without SMEP.  But there
+         * is no such hardware known at the moment.
+         */
+        if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
+                setup_clear_cpu_cap(X86_FEATURE_MPX);
+                pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
+        }
+}
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
         u64 misc_enable;
@@ -173,6 +208,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
                 if (edx & (1U << 28))
                         c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
         }
+
+        check_mpx_erratum(c);
 }
 
 #ifdef CONFIG_X86_32
@@ -233,7 +270,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
          * The Quark is also family 5, but does not have the same bug.
          */
         clear_cpu_bug(c, X86_BUG_F00F);
-        if (!paravirt_enabled() && c->x86 == 5 && c->x86_model < 9) {
+        if (c->x86 == 5 && c->x86_model < 9) {
                 static int f00f_workaround_enabled;
 
                 set_cpu_bug(c, X86_BUG_F00F);
@@ -280,7 +317,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
          * integrated APIC (see 11AP erratum in "Pentium Processor
          * Specification Update").
          */
-        if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
+        if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
                 set_cpu_bug(c, X86_BUG_11AP);
 
@@ -335,7 +372,7 @@ static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
 {
         unsigned int eax, ebx, ecx, edx;
 
-        if (c->cpuid_level < 4)
+        if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
                 return 1;
 
         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
diff --git a/arch/x86/kernel/cpu/mcheck/mce-genpool.c b/arch/x86/kernel/cpu/mcheck/mce-genpool.c
index 2658e2af74ec..93d824ec3120 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-genpool.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-genpool.c
@@ -26,6 +26,52 @@ static struct gen_pool *mce_evt_pool;
 static LLIST_HEAD(mce_event_llist);
 static char gen_pool_buf[MCE_POOLSZ];
 
+/*
+ * Compare the record "t" with each of the records on list "l" to see if
+ * an equivalent one is present in the list.
+ */
+static bool is_duplicate_mce_record(struct mce_evt_llist *t, struct mce_evt_llist *l)
+{
+        struct mce_evt_llist *node;
+        struct mce *m1, *m2;
+
+        m1 = &t->mce;
+
+        llist_for_each_entry(node, &l->llnode, llnode) {
+                m2 = &node->mce;
+
+                if (!mce_cmp(m1, m2))
+                        return true;
+        }
+        return false;
+}
+
+/*
+ * The system has panicked - we'd like to peruse the list of MCE records
+ * that have been queued, but not seen by anyone yet.  The list is in
+ * reverse time order, so we need to reverse it. While doing that we can
+ * also drop duplicate records (these were logged because some banks are
+ * shared between cores or by all threads on a socket).
+ */
+struct llist_node *mce_gen_pool_prepare_records(void)
+{
+        struct llist_node *head;
+        LLIST_HEAD(new_head);
+        struct mce_evt_llist *node, *t;
+
+        head = llist_del_all(&mce_event_llist);
+        if (!head)
+                return NULL;
+
+        /* squeeze out duplicates while reversing order */
+        llist_for_each_entry_safe(node, t, head, llnode) {
+                if (!is_duplicate_mce_record(node, t))
+                        llist_add(&node->llnode, &new_head);
+        }
+
+        return new_head.first;
+}
+
 void mce_gen_pool_process(void)
 {
         struct llist_node *head;
diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index 547720efd923..cd74a3f00aea 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -35,6 +35,7 @@ void mce_gen_pool_process(void);
 bool mce_gen_pool_empty(void);
 int mce_gen_pool_add(struct mce *mce);
 int mce_gen_pool_init(void);
+struct llist_node *mce_gen_pool_prepare_records(void);
 
 extern int (*mce_severity)(struct mce *a, int tolerant, char **msg, bool is_excp);
 struct dentry *mce_get_debugfs_dir(void);
@@ -81,3 +82,17 @@ static inline int apei_clear_mce(u64 record_id)
 #endif
 
 void mce_inject_log(struct mce *m);
+
+/*
+ * We consider records to be equivalent if bank+status+addr+misc all match.
+ * This is only used when the system is going down because of a fatal error
+ * to avoid cluttering the console log with essentially repeated information.
+ * In normal processing all errors seen are logged.
+ */
+static inline bool mce_cmp(struct mce *m1, struct mce *m2)
+{
+        return m1->bank != m2->bank ||
+                m1->status != m2->status ||
+                m1->addr != m2->addr ||
+                m1->misc != m2->misc;
+}
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 5119766d9889..631356c8cca4 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -204,6 +204,33 @@ static int error_context(struct mce *m)
         return IN_KERNEL;
 }
 
+static int mce_severity_amd_smca(struct mce *m, int err_ctx)
+{
+        u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
+        u32 low, high;
+
+        /*
+         * We need to look at the following bits:
+         * - "succor" bit (data poisoning support), and
+         * - TCC bit (Task Context Corrupt)
+         * in MCi_STATUS to determine error severity.
+         */
+        if (!mce_flags.succor)
+                return MCE_PANIC_SEVERITY;
+
+        if (rdmsr_safe(addr, &low, &high))
+                return MCE_PANIC_SEVERITY;
+
+        /* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */
+        if ((low & MCI_CONFIG_MCAX) &&
+            (m->status & MCI_STATUS_TCC) &&
+            (err_ctx == IN_KERNEL))
+                return MCE_PANIC_SEVERITY;
+
+         /* ...otherwise invoke hwpoison handler. */
+        return MCE_AR_SEVERITY;
+}
+
 /*
  * See AMD Error Scope Hierarchy table in a newer BKDG. For example
  * 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features"
@@ -225,6 +252,9 @@ static int mce_severity_amd(struct mce *m, int tolerant, char **msg, bool is_exc
                  * to at least kill process to prolong system operation.
                  */
                 if (mce_flags.overflow_recov) {
+                        if (mce_flags.smca)
+                                return mce_severity_amd_smca(m, ctx);
+
                         /* software can try to contain */
                         if (!(m->mcgstatus & MCG_STATUS_RIPV) && (ctx == IN_KERNEL))
                                 return MCE_PANIC_SEVERITY;
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index f0c921b03e42..92e5e37d97bf 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -161,7 +161,6 @@ void mce_log(struct mce *mce)
         if (!mce_gen_pool_add(mce))
                 irq_work_queue(&mce_irq_work);
 
-        mce->finished = 0;
         wmb();
         for (;;) {
                 entry = mce_log_get_idx_check(mcelog.next);
@@ -194,7 +193,6 @@ void mce_log(struct mce *mce)
         mcelog.entry[entry].finished = 1;
         wmb();
 
-        mce->finished = 1;
         set_bit(0, &mce_need_notify);
 }
 
@@ -224,6 +222,53 @@ void mce_unregister_decode_chain(struct notifier_block *nb)
 }
 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
 
+static inline u32 ctl_reg(int bank)
+{
+        return MSR_IA32_MCx_CTL(bank);
+}
+
+static inline u32 status_reg(int bank)
+{
+        return MSR_IA32_MCx_STATUS(bank);
+}
+
+static inline u32 addr_reg(int bank)
+{
+        return MSR_IA32_MCx_ADDR(bank);
+}
+
+static inline u32 misc_reg(int bank)
+{
+        return MSR_IA32_MCx_MISC(bank);
+}
+
+static inline u32 smca_ctl_reg(int bank)
+{
+        return MSR_AMD64_SMCA_MCx_CTL(bank);
+}
+
+static inline u32 smca_status_reg(int bank)
+{
+        return MSR_AMD64_SMCA_MCx_STATUS(bank);
+}
+
+static inline u32 smca_addr_reg(int bank)
+{
+        return MSR_AMD64_SMCA_MCx_ADDR(bank);
+}
+
+static inline u32 smca_misc_reg(int bank)
+{
+        return MSR_AMD64_SMCA_MCx_MISC(bank);
+}
+
+struct mca_msr_regs msr_ops = {
+        .ctl    = ctl_reg,
+        .status = status_reg,
+        .addr   = addr_reg,
+        .misc   = misc_reg
+};
+
 static void print_mce(struct mce *m)
 {
         int ret = 0;
@@ -290,7 +335,9 @@ static void wait_for_panic(void)
 
 static void mce_panic(const char *msg, struct mce *final, char *exp)
 {
-        int i, apei_err = 0;
+        int apei_err = 0;
+        struct llist_node *pending;
+        struct mce_evt_llist *l;
 
         if (!fake_panic) {
                 /*
@@ -307,11 +354,10 @@ static void mce_panic(const char *msg, struct mce *final, char *exp)
                 if (atomic_inc_return(&mce_fake_panicked) > 1)
                         return;
         }
+        pending = mce_gen_pool_prepare_records();
         /* First print corrected ones that are still unlogged */
-        for (i = 0; i < MCE_LOG_LEN; i++) {
-                struct mce *m = &mcelog.entry[i];
-                if (!(m->status & MCI_STATUS_VAL))
-                        continue;
+        llist_for_each_entry(l, pending, llnode) {
+                struct mce *m = &l->mce;
                 if (!(m->status & MCI_STATUS_UC)) {
                         print_mce(m);
                         if (!apei_err)
@@ -319,13 +365,11 @@ static void mce_panic(const char *msg, struct mce *final, char *exp)
                 }
         }
         /* Now print uncorrected but with the final one last */
-        for (i = 0; i < MCE_LOG_LEN; i++) {
-                struct mce *m = &mcelog.entry[i];
-                if (!(m->status & MCI_STATUS_VAL))
-                        continue;
+        llist_for_each_entry(l, pending, llnode) {
+                struct mce *m = &l->mce;
                 if (!(m->status & MCI_STATUS_UC))
                         continue;
-                if (!final || memcmp(m, final, sizeof(struct mce))) {
+                if (!final || mce_cmp(m, final)) {
                         print_mce(m);
                         if (!apei_err)
                                 apei_err = apei_write_mce(m);
@@ -356,11 +400,11 @@ static int msr_to_offset(u32 msr)
 
         if (msr == mca_cfg.rip_msr)
                 return offsetof(struct mce, ip);
-        if (msr == MSR_IA32_MCx_STATUS(bank))
+        if (msr == msr_ops.status(bank))
                 return offsetof(struct mce, status);
-        if (msr == MSR_IA32_MCx_ADDR(bank))
+        if (msr == msr_ops.addr(bank))
                 return offsetof(struct mce, addr);
-        if (msr == MSR_IA32_MCx_MISC(bank))
+        if (msr == msr_ops.misc(bank))
                 return offsetof(struct mce, misc);
         if (msr == MSR_IA32_MCG_STATUS)
                 return offsetof(struct mce, mcgstatus);
@@ -523,9 +567,9 @@ static struct notifier_block mce_srao_nb = {
 static void mce_read_aux(struct mce *m, int i)
 {
         if (m->status & MCI_STATUS_MISCV)
-                m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
+                m->misc = mce_rdmsrl(msr_ops.misc(i));
         if (m->status & MCI_STATUS_ADDRV) {
-                m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
+                m->addr = mce_rdmsrl(msr_ops.addr(i));
 
                 /*
                  * Mask the reported address by the reported granularity.
@@ -607,7 +651,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                 m.tsc = 0;
 
                 barrier();
-                m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
+                m.status = mce_rdmsrl(msr_ops.status(i));
                 if (!(m.status & MCI_STATUS_VAL))
                         continue;
 
@@ -654,7 +698,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                 /*
                  * Clear state for this bank.
                  */
-                mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
+                mce_wrmsrl(msr_ops.status(i), 0);
         }
 
         /*
@@ -679,7 +723,7 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
         char *tmp;
 
         for (i = 0; i < mca_cfg.banks; i++) {
-                m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
+                m->status = mce_rdmsrl(msr_ops.status(i));
                 if (m->status & MCI_STATUS_VAL) {
                         __set_bit(i, validp);
                         if (quirk_no_way_out)
@@ -830,9 +874,9 @@ static int mce_start(int *no_way_out)
 
         atomic_add(*no_way_out, &global_nwo);
         /*
-         * global_nwo should be updated before mce_callin
+         * Rely on the implied barrier below, such that global_nwo
+         * is updated before mce_callin.
          */
-        smp_wmb();
         order = atomic_inc_return(&mce_callin);
 
         /*
@@ -957,7 +1001,7 @@ static void mce_clear_state(unsigned long *toclear)
 
         for (i = 0; i < mca_cfg.banks; i++) {
                 if (test_bit(i, toclear))
-                        mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
+                        mce_wrmsrl(msr_ops.status(i), 0);
         }
 }
 
@@ -994,11 +1038,12 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         int i;
         int worst = 0;
         int severity;
+
         /*
          * Establish sequential order between the CPUs entering the machine
          * check handler.
          */
-        int order;
+        int order = -1;
         /*
          * If no_way_out gets set, there is no safe way to recover from this
          * MCE.  If mca_cfg.tolerant is cranked up, we'll try anyway.
@@ -1012,7 +1057,12 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         DECLARE_BITMAP(toclear, MAX_NR_BANKS);
         DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
         char *msg = "Unknown";
-        int lmce = 0;
+
+        /*
+         * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
+         * on Intel.
+         */
+        int lmce = 1;
 
         /* If this CPU is offline, just bail out. */
         if (cpu_is_offline(smp_processor_id())) {
@@ -1051,19 +1101,20 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                 kill_it = 1;
 
         /*
-         * Check if this MCE is signaled to only this logical processor
+         * Check if this MCE is signaled to only this logical processor,
+         * on Intel only.
          */
-        if (m.mcgstatus & MCG_STATUS_LMCES)
-                lmce = 1;
-        else {
-                /*
-                 * Go through all the banks in exclusion of the other CPUs.
-                 * This way we don't report duplicated events on shared banks
-                 * because the first one to see it will clear it.
-                 * If this is a Local MCE, then no need to perform rendezvous.
-                 */
+        if (m.cpuvendor == X86_VENDOR_INTEL)
+                lmce = m.mcgstatus & MCG_STATUS_LMCES;
+
+        /*
+         * Go through all banks in exclusion of the other CPUs. This way we
+         * don't report duplicated events on shared banks because the first one
+         * to see it will clear it. If this is a Local MCE, then no need to
+         * perform rendezvous.
+         */
+        if (!lmce)
                 order = mce_start(&no_way_out);
-        }
 
         for (i = 0; i < cfg->banks; i++) {
                 __clear_bit(i, toclear);
@@ -1076,7 +1127,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                 m.addr = 0;
                 m.bank = i;
 
-                m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
+                m.status = mce_rdmsrl(msr_ops.status(i));
                 if ((m.status & MCI_STATUS_VAL) == 0)
                         continue;
 
@@ -1420,7 +1471,6 @@ static void __mcheck_cpu_init_generic(void)
         enum mcp_flags m_fl = 0;
         mce_banks_t all_banks;
         u64 cap;
-        int i;
 
         if (!mca_cfg.bootlog)
                 m_fl = MCP_DONTLOG;
@@ -1436,14 +1486,19 @@ static void __mcheck_cpu_init_generic(void)
         rdmsrl(MSR_IA32_MCG_CAP, cap);
         if (cap & MCG_CTL_P)
                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+}
+
+static void __mcheck_cpu_init_clear_banks(void)
+{
+        int i;
 
         for (i = 0; i < mca_cfg.banks; i++) {
                 struct mce_bank *b = &mce_banks[i];
 
                 if (!b->init)
                         continue;
-                wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
-                wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
+                wrmsrl(msr_ops.ctl(i), b->ctl);
+                wrmsrl(msr_ops.status(i), 0);
         }
 }
 
@@ -1495,7 +1550,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
                          */
                         clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
                 }
-                if (c->x86 <= 17 && cfg->bootlog < 0) {
+                if (c->x86 < 17 && cfg->bootlog < 0) {
                         /*
                          * Lots of broken BIOS around that don't clear them
                          * by default and leave crap in there. Don't log:
@@ -1628,11 +1683,19 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
                 break;
 
         case X86_VENDOR_AMD: {
-                u32 ebx = cpuid_ebx(0x80000007);
+                mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
+                mce_flags.succor         = !!cpu_has(c, X86_FEATURE_SUCCOR);
+                mce_flags.smca           = !!cpu_has(c, X86_FEATURE_SMCA);
 
-                mce_flags.overflow_recov = !!(ebx & BIT(0));
-                mce_flags.succor         = !!(ebx & BIT(1));
-                mce_flags.smca           = !!(ebx & BIT(3));
+                /*
+                 * Install proper ops for Scalable MCA enabled processors
+                 */
+                if (mce_flags.smca) {
+                        msr_ops.ctl     = smca_ctl_reg;
+                        msr_ops.status  = smca_status_reg;
+                        msr_ops.addr    = smca_addr_reg;
+                        msr_ops.misc    = smca_misc_reg;
+                }
                 mce_amd_feature_init(c);
 
                 break;
@@ -1717,6 +1780,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
 
         __mcheck_cpu_init_generic();
         __mcheck_cpu_init_vendor(c);
+        __mcheck_cpu_init_clear_banks();
         __mcheck_cpu_init_timer();
 }
 
@@ -2082,7 +2146,7 @@ static void mce_disable_error_reporting(void)
                 struct mce_bank *b = &mce_banks[i];
 
                 if (b->init)
-                        wrmsrl(MSR_IA32_MCx_CTL(i), 0);
+                        wrmsrl(msr_ops.ctl(i), 0);
         }
         return;
 }
@@ -2121,6 +2185,7 @@ static void mce_syscore_resume(void)
 {
         __mcheck_cpu_init_generic();
         __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
+        __mcheck_cpu_init_clear_banks();
 }
 
 static struct syscore_ops mce_syscore_ops = {
@@ -2138,6 +2203,7 @@ static void mce_cpu_restart(void *data)
         if (!mce_available(raw_cpu_ptr(&cpu_info)))
                 return;
         __mcheck_cpu_init_generic();
+        __mcheck_cpu_init_clear_banks();
         __mcheck_cpu_init_timer();
 }
 
@@ -2413,7 +2479,7 @@ static void mce_reenable_cpu(void *h)
                 struct mce_bank *b = &mce_banks[i];
 
                 if (b->init)
-                        wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
+                        wrmsrl(msr_ops.ctl(i), b->ctl);
         }
 }
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 9d656fd436ef..10b0661651e0 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -54,14 +54,6 @@
 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
 #define SMCA_THR_LVT_OFF        0xF000
 
-/*
- * OS is required to set the MCAX bit to acknowledge that it is now using the
- * new MSR ranges and new registers under each bank. It also means that the OS
- * will configure deferred errors in the new MCx_CONFIG register. If the bit is
- * not set, uncorrectable errors will cause a system panic.
- */
-#define SMCA_MCAX_EN_OFF        0x1
-
 static const char * const th_names[] = {
         "load_store",
         "insn_fetch",
@@ -333,7 +325,7 @@ static u32 get_block_address(u32 current_addr, u32 low, u32 high,
         /* Fall back to method we used for older processors: */
         switch (block) {
         case 0:
-                addr = MSR_IA32_MCx_MISC(bank);
+                addr = msr_ops.misc(bank);
                 break;
         case 1:
                 offset = ((low & MASK_BLKPTR_LO) >> 21);
@@ -351,6 +343,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
                         int offset, u32 misc_high)
 {
         unsigned int cpu = smp_processor_id();
+        u32 smca_low, smca_high, smca_addr;
         struct threshold_block b;
         int new;
 
@@ -369,24 +362,49 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 
         b.interrupt_enable = 1;
 
-        if (mce_flags.smca) {
-                u32 smca_low, smca_high;
-                u32 smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);
+        if (!mce_flags.smca) {
+                new = (misc_high & MASK_LVTOFF_HI) >> 20;
+                goto set_offset;
+        }
 
-                if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) {
-                        smca_high |= SMCA_MCAX_EN_OFF;
-                        wrmsr(smca_addr, smca_low, smca_high);
-                }
+        smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);
 
-                /* Gather LVT offset for thresholding: */
-                if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
-                        goto out;
+        if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) {
+                /*
+                 * OS is required to set the MCAX bit to acknowledge that it is
+                 * now using the new MSR ranges and new registers under each
+                 * bank. It also means that the OS will configure deferred
+                 * errors in the new MCx_CONFIG register. If the bit is not set,
+                 * uncorrectable errors will cause a system panic.
+                 *
+                 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
+                 */
+                smca_high |= BIT(0);
 
-                new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
-        } else {
-                new = (misc_high & MASK_LVTOFF_HI) >> 20;
+                /*
+                 * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR}
+                 * registers with the option of additionally logging to
+                 * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set.
+                 *
+                 * This bit is usually set by BIOS to retain the old behavior
+                 * for OSes that don't use the new registers. Linux supports the
+                 * new registers so let's disable that additional logging here.
+                 *
+                 * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high
+                 * portion of the MSR).
+                 */
+                smca_high &= ~BIT(2);
+
+                wrmsr(smca_addr, smca_low, smca_high);
         }
 
+        /* Gather LVT offset for thresholding: */
+        if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
+                goto out;
+
+        new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+
+set_offset:
         offset = setup_APIC_mce_threshold(offset, new);
 
         if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
@@ -430,12 +448,23 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
                 deferred_error_interrupt_enable(c);
 }
 
-static void __log_error(unsigned int bank, bool threshold_err, u64 misc)
+static void
+__log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
 {
+        u32 msr_status = msr_ops.status(bank);
+        u32 msr_addr = msr_ops.addr(bank);
         struct mce m;
         u64 status;
 
-        rdmsrl(MSR_IA32_MCx_STATUS(bank), status);
+        WARN_ON_ONCE(deferred_err && threshold_err);
+
+        if (deferred_err && mce_flags.smca) {
+                msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank);
+                msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank);
+        }
+
+        rdmsrl(msr_status, status);
+
         if (!(status & MCI_STATUS_VAL))
                 return;
 
@@ -448,10 +477,11 @@ static void __log_error(unsigned int bank, bool threshold_err, u64 misc)
                 m.misc = misc;
 
         if (m.status & MCI_STATUS_ADDRV)
-                rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr);
+                rdmsrl(msr_addr, m.addr);
 
         mce_log(&m);
-        wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);
+
+        wrmsrl(msr_status, 0);
 }
 
 static inline void __smp_deferred_error_interrupt(void)
@@ -479,17 +509,21 @@ asmlinkage __visible void smp_trace_deferred_error_interrupt(void)
 /* APIC interrupt handler for deferred errors */
 static void amd_deferred_error_interrupt(void)
 {
-        u64 status;
         unsigned int bank;
+        u32 msr_status;
+        u64 status;
 
         for (bank = 0; bank < mca_cfg.banks; ++bank) {
-                rdmsrl(MSR_IA32_MCx_STATUS(bank), status);
+                msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank)
+                                              : msr_ops.status(bank);
+
+                rdmsrl(msr_status, status);
 
                 if (!(status & MCI_STATUS_VAL) ||
                     !(status & MCI_STATUS_DEFERRED))
                         continue;
 
-                __log_error(bank, false, 0);
+                __log_error(bank, true, false, 0);
                 break;
         }
 }
@@ -544,7 +578,7 @@ static void amd_threshold_interrupt(void)
         return;
 
 log:
-        __log_error(bank, true, ((u64)high << 32) | low);
+        __log_error(bank, false, true, ((u64)high << 32) | low);
 }
 
 /*
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 1e8bb6c94f14..1defb8ea882c 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -84,7 +84,7 @@ static int cmci_supported(int *banks)
          */
         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
                 return 0;
-        if (!cpu_has_apic || lapic_get_maxlvt() < 6)
+        if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
                 return 0;
         rdmsrl(MSR_IA32_MCG_CAP, cap);
         *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index ac780cad3b86..6b9dc4d18ccc 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -450,7 +450,7 @@ asmlinkage __visible void smp_trace_thermal_interrupt(struct pt_regs *regs)
 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
 static int intel_thermal_supported(struct cpuinfo_x86 *c)
 {
-        if (!cpu_has_apic)
+        if (!boot_cpu_has(X86_FEATURE_APIC))
                 return 0;
         if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
                 return 0;
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index cbb3cf09b065..65cbbcd48fe4 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -422,7 +422,7 @@ static void show_saved_mc(void)
                 data_size = get_datasize(mc_saved_header);
                 date = mc_saved_header->date;
 
-                pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, toal size=0x%x, date = %04x-%02x-%02x\n",
+                pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n",
                          i, sig, pf, rev, total_size,
                          date & 0xffff,
                          date >> 24,
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index f1bed301bdb2..16e37a2581ac 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -444,11 +444,24 @@ static void __init print_mtrr_state(void)
                 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
 }
 
+/* PAT setup for BP. We need to go through sync steps here */
+void __init mtrr_bp_pat_init(void)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        prepare_set();
+
+        pat_init();
+
+        post_set();
+        local_irq_restore(flags);
+}
+
 /* Grab all of the MTRR state for this CPU into *state */
 bool __init get_mtrr_state(void)
 {
         struct mtrr_var_range *vrs;
-        unsigned long flags;
         unsigned lo, dummy;
         unsigned int i;
 
@@ -481,15 +494,6 @@ bool __init get_mtrr_state(void)
 
         mtrr_state_set = 1;
 
-        /* PAT setup for BP. We need to go through sync steps here */
-        local_irq_save(flags);
-        prepare_set();
-
-        pat_init();
-
-        post_set();
-        local_irq_restore(flags);
-
         return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED);
 }
 
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 10f8d4796240..7d393ecdeee6 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -752,6 +752,9 @@ void __init mtrr_bp_init(void)
                         /* BIOS may override */
                         __mtrr_enabled = get_mtrr_state();
 
+                        if (mtrr_enabled())
+                                mtrr_bp_pat_init();
+
                         if (mtrr_cleanup(phys_addr)) {
                                 changed_by_mtrr_cleanup = 1;
                                 mtrr_if->set_all();
@@ -759,8 +762,16 @@ void __init mtrr_bp_init(void)
                 }
         }
 
-        if (!mtrr_enabled())
+        if (!mtrr_enabled()) {
                 pr_info("MTRR: Disabled\n");
+
+                /*
+                 * PAT initialization relies on MTRR's rendezvous handler.
+                 * Skip PAT init until the handler can initialize both
+                 * features independently.
+                 */
+                pat_disable("MTRRs disabled, skipping PAT initialization too.");
+        }
 }
 
 void mtrr_ap_init(void)
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h
index 951884dcc433..6c7ced07d16d 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.h
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.h
@@ -52,6 +52,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt);
 void fill_mtrr_var_range(unsigned int index,
                 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
 bool get_mtrr_state(void);
+void mtrr_bp_pat_init(void);
 
 extern void set_mtrr_ops(const struct mtrr_ops *ops);
 
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 1f4acd68b98b..3fe45f84ced4 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -151,7 +151,7 @@ static void __init dtb_lapic_setup(void)
                 return;
 
         /* Did the boot loader setup the local APIC ? */
-        if (!cpu_has_apic) {
+        if (!boot_cpu_has(X86_FEATURE_APIC)) {
                 if (apic_force_enable(r.start))
                         return;
         }
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index 8efa57a5f29e..2bb25c3fe2e8 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -260,19 +260,12 @@ int __die(const char *str, struct pt_regs *regs, long err)
         unsigned long sp;
 #endif
         printk(KERN_DEFAULT
-               "%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter);
-#ifdef CONFIG_PREEMPT
-        printk("PREEMPT ");
-#endif
-#ifdef CONFIG_SMP
-        printk("SMP ");
-#endif
-        if (debug_pagealloc_enabled())
-                printk("DEBUG_PAGEALLOC ");
-#ifdef CONFIG_KASAN
-        printk("KASAN");
-#endif
-        printk("\n");
+               "%s: %04lx [#%d]%s%s%s%s\n", str, err & 0xffff, ++die_counter,
+               IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT"         : "",
+               IS_ENABLED(CONFIG_SMP)     ? " SMP"             : "",
+               debug_pagealloc_enabled()  ? " DEBUG_PAGEALLOC" : "",
+               IS_ENABLED(CONFIG_KASAN)   ? " KASAN"           : "");
+
         if (notify_die(DIE_OOPS, str, regs, err,
                         current->thread.trap_nr, SIGSEGV) == NOTIFY_STOP)
                 return 1;
diff --git a/arch/x86/kernel/head.c b/arch/x86/kernel/ebda.c
index 992f442ca155..afe65dffee80 100644
--- a/arch/x86/kernel/head.c
+++ b/arch/x86/kernel/ebda.c
@@ -38,7 +38,7 @@ void __init reserve_ebda_region(void)
          * that the paravirt case can handle memory setup
          * correctly, without our help.
          */
-        if (paravirt_enabled())
+        if (!x86_platform.legacy.ebda_search)
                 return;
 
         /* end of low (conventional) memory */
diff --git a/arch/x86/kernel/fpu/bugs.c b/arch/x86/kernel/fpu/bugs.c
index dd9ca9b60ff3..aad34aafc0e0 100644
--- a/arch/x86/kernel/fpu/bugs.c
+++ b/arch/x86/kernel/fpu/bugs.c
@@ -21,11 +21,15 @@ static double __initdata y = 3145727.0;
  * We should really only care about bugs here
  * anyway. Not features.
  */
-static void __init check_fpu(void)
+void __init fpu__init_check_bugs(void)
 {
         u32 cr0_saved;
         s32 fdiv_bug;
 
+        /* kernel_fpu_begin/end() relies on patched alternative instructions. */
+        if (!boot_cpu_has(X86_FEATURE_FPU))
+                return;
+
         /* We might have CR0::TS set already, clear it: */
         cr0_saved = read_cr0();
         write_cr0(cr0_saved & ~X86_CR0_TS);
@@ -59,13 +63,3 @@ static void __init check_fpu(void)
                 pr_warn("Hmm, FPU with FDIV bug\n");
         }
 }
-
-void __init fpu__init_check_bugs(void)
-{
-        /*
-         * kernel_fpu_begin/end() in check_fpu() relies on the patched
-         * alternative instructions.
-         */
-        if (cpu_has_fpu)
-                check_fpu();
-}
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index 8e37cc8a539a..97027545a72d 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -217,14 +217,14 @@ static inline void fpstate_init_fstate(struct fregs_state *fp)
 
 void fpstate_init(union fpregs_state *state)
 {
-        if (!cpu_has_fpu) {
+        if (!static_cpu_has(X86_FEATURE_FPU)) {
                 fpstate_init_soft(&state->soft);
                 return;
         }
 
         memset(state, 0, xstate_size);
 
-        if (cpu_has_fxsr)
+        if (static_cpu_has(X86_FEATURE_FXSR))
                 fpstate_init_fxstate(&state->fxsave);
         else
                 fpstate_init_fstate(&state->fsave);
@@ -237,7 +237,7 @@ int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
         dst_fpu->fpregs_active = 0;
         dst_fpu->last_cpu = -1;
 
-        if (!src_fpu->fpstate_active || !cpu_has_fpu)
+        if (!src_fpu->fpstate_active || !static_cpu_has(X86_FEATURE_FPU))
                 return 0;
 
         WARN_ON_FPU(src_fpu != &current->thread.fpu);
@@ -506,33 +506,6 @@ void fpu__clear(struct fpu *fpu)
  * x87 math exception handling:
  */
 
-static inline unsigned short get_fpu_cwd(struct fpu *fpu)
-{
-        if (cpu_has_fxsr) {
-                return fpu->state.fxsave.cwd;
-        } else {
-                return (unsigned short)fpu->state.fsave.cwd;
-        }
-}
-
-static inline unsigned short get_fpu_swd(struct fpu *fpu)
-{
-        if (cpu_has_fxsr) {
-                return fpu->state.fxsave.swd;
-        } else {
-                return (unsigned short)fpu->state.fsave.swd;
-        }
-}
-
-static inline unsigned short get_fpu_mxcsr(struct fpu *fpu)
-{
-        if (cpu_has_xmm) {
-                return fpu->state.fxsave.mxcsr;
-        } else {
-                return MXCSR_DEFAULT;
-        }
-}
-
 int fpu__exception_code(struct fpu *fpu, int trap_nr)
 {
         int err;
@@ -547,10 +520,15 @@ int fpu__exception_code(struct fpu *fpu, int trap_nr)
                  * so if this combination doesn't produce any single exception,
                  * then we have a bad program that isn't synchronizing its FPU usage
                  * and it will suffer the consequences since we won't be able to
-                 * fully reproduce the context of the exception
+                 * fully reproduce the context of the exception.
                  */
-                cwd = get_fpu_cwd(fpu);
-                swd = get_fpu_swd(fpu);
+                if (boot_cpu_has(X86_FEATURE_FXSR)) {
+                        cwd = fpu->state.fxsave.cwd;
+                        swd = fpu->state.fxsave.swd;
+                } else {
+                        cwd = (unsigned short)fpu->state.fsave.cwd;
+                        swd = (unsigned short)fpu->state.fsave.swd;
+                }
 
                 err = swd & ~cwd;
         } else {
@@ -560,7 +538,11 @@ int fpu__exception_code(struct fpu *fpu, int trap_nr)
                  * unmasked exception was caught we must mask the exception mask bits
                  * at 0x1f80, and then use these to mask the exception bits at 0x3f.
                  */
-                unsigned short mxcsr = get_fpu_mxcsr(fpu);
+                unsigned short mxcsr = MXCSR_DEFAULT;
+
+                if (boot_cpu_has(X86_FEATURE_XMM))
+                        mxcsr = fpu->state.fxsave.mxcsr;
+
                 err = ~(mxcsr >> 7) & mxcsr;
         }
 
diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c
index 54c86fffbf9f..aacfd7a82cec 100644
--- a/arch/x86/kernel/fpu/init.c
+++ b/arch/x86/kernel/fpu/init.c
@@ -29,22 +29,22 @@ static void fpu__init_cpu_generic(void)
         unsigned long cr0;
         unsigned long cr4_mask = 0;
 
-        if (cpu_has_fxsr)
+        if (boot_cpu_has(X86_FEATURE_FXSR))
                 cr4_mask |= X86_CR4_OSFXSR;
-        if (cpu_has_xmm)
+        if (boot_cpu_has(X86_FEATURE_XMM))
                 cr4_mask |= X86_CR4_OSXMMEXCPT;
         if (cr4_mask)
                 cr4_set_bits(cr4_mask);
 
         cr0 = read_cr0();
         cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
-        if (!cpu_has_fpu)
+        if (!boot_cpu_has(X86_FEATURE_FPU))
                 cr0 |= X86_CR0_EM;
         write_cr0(cr0);
 
         /* Flush out any pending x87 state: */
 #ifdef CONFIG_MATH_EMULATION
-        if (!cpu_has_fpu)
+        if (!boot_cpu_has(X86_FEATURE_FPU))
                 fpstate_init_soft(&current->thread.fpu.state.soft);
         else
 #endif
@@ -89,7 +89,7 @@ static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
         }
 
 #ifndef CONFIG_MATH_EMULATION
-        if (!cpu_has_fpu) {
+        if (!boot_cpu_has(X86_FEATURE_FPU)) {
                 pr_emerg("x86/fpu: Giving up, no FPU found and no math emulation present\n");
                 for (;;)
                         asm volatile("hlt");
@@ -106,7 +106,7 @@ static void __init fpu__init_system_mxcsr(void)
 {
         unsigned int mask = 0;
 
-        if (cpu_has_fxsr) {
+        if (boot_cpu_has(X86_FEATURE_FXSR)) {
                 /* Static because GCC does not get 16-byte stack alignment right: */
                 static struct fxregs_state fxregs __initdata;
 
@@ -212,7 +212,7 @@ static void __init fpu__init_system_xstate_size_legacy(void)
          * fpu__init_system_xstate().
          */
 
-        if (!cpu_has_fpu) {
+        if (!boot_cpu_has(X86_FEATURE_FPU)) {
                 /*
                  * Disable xsave as we do not support it if i387
                  * emulation is enabled.
@@ -221,7 +221,7 @@ static void __init fpu__init_system_xstate_size_legacy(void)
                 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
                 xstate_size = sizeof(struct swregs_state);
         } else {
-                if (cpu_has_fxsr)
+                if (boot_cpu_has(X86_FEATURE_FXSR))
                         xstate_size = sizeof(struct fxregs_state);
                 else
                         xstate_size = sizeof(struct fregs_state);
diff --git a/arch/x86/kernel/fpu/regset.c b/arch/x86/kernel/fpu/regset.c
index 8bd1c003942a..81422dfb152b 100644
--- a/arch/x86/kernel/fpu/regset.c
+++ b/arch/x86/kernel/fpu/regset.c
@@ -21,7 +21,10 @@ int regset_xregset_fpregs_active(struct task_struct *target, const struct user_r
 {
         struct fpu *target_fpu = &target->thread.fpu;
 
-        return (cpu_has_fxsr && target_fpu->fpstate_active) ? regset->n : 0;
+        if (boot_cpu_has(X86_FEATURE_FXSR) && target_fpu->fpstate_active)
+                return regset->n;
+        else
+                return 0;
 }
 
 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
@@ -30,7 +33,7 @@ int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
 {
         struct fpu *fpu = &target->thread.fpu;
 
-        if (!cpu_has_fxsr)
+        if (!boot_cpu_has(X86_FEATURE_FXSR))
                 return -ENODEV;
 
         fpu__activate_fpstate_read(fpu);
@@ -47,7 +50,7 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
         struct fpu *fpu = &target->thread.fpu;
         int ret;
 
-        if (!cpu_has_fxsr)
+        if (!boot_cpu_has(X86_FEATURE_FXSR))
                 return -ENODEV;
 
         fpu__activate_fpstate_write(fpu);
@@ -65,7 +68,7 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
          * update the header bits in the xsave header, indicating the
          * presence of FP and SSE state.
          */
-        if (cpu_has_xsave)
+        if (boot_cpu_has(X86_FEATURE_XSAVE))
                 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
 
         return ret;
@@ -79,7 +82,7 @@ int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
         struct xregs_state *xsave;
         int ret;
 
-        if (!cpu_has_xsave)
+        if (!boot_cpu_has(X86_FEATURE_XSAVE))
                 return -ENODEV;
 
         fpu__activate_fpstate_read(fpu);
@@ -108,7 +111,7 @@ int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
         struct xregs_state *xsave;
         int ret;
 
-        if (!cpu_has_xsave)
+        if (!boot_cpu_has(X86_FEATURE_XSAVE))
                 return -ENODEV;
 
         fpu__activate_fpstate_write(fpu);
@@ -275,10 +278,10 @@ int fpregs_get(struct task_struct *target, const struct user_regset *regset,
 
         fpu__activate_fpstate_read(fpu);
 
-        if (!static_cpu_has(X86_FEATURE_FPU))
+        if (!boot_cpu_has(X86_FEATURE_FPU))
                 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
 
-        if (!cpu_has_fxsr)
+        if (!boot_cpu_has(X86_FEATURE_FXSR))
                 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
                                            &fpu->state.fsave, 0,
                                            -1);
@@ -306,10 +309,10 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
         fpu__activate_fpstate_write(fpu);
         fpstate_sanitize_xstate(fpu);
 
-        if (!static_cpu_has(X86_FEATURE_FPU))
+        if (!boot_cpu_has(X86_FEATURE_FPU))
                 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
 
-        if (!cpu_has_fxsr)
+        if (!boot_cpu_has(X86_FEATURE_FXSR))
                 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
                                           &fpu->state.fsave, 0,
                                           -1);
@@ -325,7 +328,7 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
          * update the header bit in the xsave header, indicating the
          * presence of FP.
          */
-        if (cpu_has_xsave)
+        if (boot_cpu_has(X86_FEATURE_XSAVE))
                 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
         return ret;
 }
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index b48ef35b28d4..4ea2a59483c7 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -190,7 +190,7 @@ void fpstate_sanitize_xstate(struct fpu *fpu)
  */
 void fpu__init_cpu_xstate(void)
 {
-        if (!cpu_has_xsave || !xfeatures_mask)
+        if (!boot_cpu_has(X86_FEATURE_XSAVE) || !xfeatures_mask)
                 return;
 
         cr4_set_bits(X86_CR4_OSXSAVE);
@@ -280,7 +280,7 @@ static void __init setup_xstate_comp(void)
         xstate_comp_offsets[0] = 0;
         xstate_comp_offsets[1] = offsetof(struct fxregs_state, xmm_space);
 
-        if (!cpu_has_xsaves) {
+        if (!boot_cpu_has(X86_FEATURE_XSAVES)) {
                 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
                         if (xfeature_enabled(i)) {
                                 xstate_comp_offsets[i] = xstate_offsets[i];
@@ -316,13 +316,13 @@ static void __init setup_init_fpu_buf(void)
         WARN_ON_FPU(!on_boot_cpu);
         on_boot_cpu = 0;
 
-        if (!cpu_has_xsave)
+        if (!boot_cpu_has(X86_FEATURE_XSAVE))
                 return;
 
         setup_xstate_features();
         print_xstate_features();
 
-        if (cpu_has_xsaves) {
+        if (boot_cpu_has(X86_FEATURE_XSAVES)) {
                 init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask;
                 init_fpstate.xsave.header.xfeatures = xfeatures_mask;
         }
@@ -417,7 +417,7 @@ static int xfeature_size(int xfeature_nr)
  */
 static int using_compacted_format(void)
 {
-        return cpu_has_xsaves;
+        return boot_cpu_has(X86_FEATURE_XSAVES);
 }
 
 static void __xstate_dump_leaves(void)
@@ -549,7 +549,7 @@ static unsigned int __init calculate_xstate_size(void)
         unsigned int eax, ebx, ecx, edx;
         unsigned int calculated_xstate_size;
 
-        if (!cpu_has_xsaves) {
+        if (!boot_cpu_has(X86_FEATURE_XSAVES)) {
                 /*
                  * - CPUID function 0DH, sub-function 0:
                  *    EBX enumerates the size (in bytes) required by
@@ -630,7 +630,7 @@ void __init fpu__init_system_xstate(void)
         WARN_ON_FPU(!on_boot_cpu);
         on_boot_cpu = 0;
 
-        if (!cpu_has_xsave) {
+        if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
                 pr_info("x86/fpu: Legacy x87 FPU detected.\n");
                 return;
         }
@@ -667,7 +667,7 @@ void __init fpu__init_system_xstate(void)
         pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n",
                 xfeatures_mask,
                 xstate_size,
-                cpu_has_xsaves ? "compacted" : "standard");
+                boot_cpu_has(X86_FEATURE_XSAVES) ? "compacted" : "standard");
 }
 
 /*
@@ -678,7 +678,7 @@ void fpu__resume_cpu(void)
         /*
          * Restore XCR0 on xsave capable CPUs:
          */
-        if (cpu_has_xsave)
+        if (boot_cpu_has(X86_FEATURE_XSAVE))
                 xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask);
 }
 
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index 2911ef3a9f1c..d784bb547a9d 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -34,6 +34,8 @@ asmlinkage __visible void __init i386_start_kernel(void)
         cr4_init_shadow();
         sanitize_boot_params(&boot_params);
 
+        x86_early_init_platform_quirks();
+
         /* Call the subarch specific early setup function */
         switch (boot_params.hdr.hardware_subarch) {
         case X86_SUBARCH_INTEL_MID:
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 1f4422d5c8d0..b72fb0b71dd1 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -182,6 +182,7 @@ void __init x86_64_start_reservations(char *real_mode_data)
         if (!boot_params.hdr.version)
                 copy_bootdata(__va(real_mode_data));
 
+        x86_early_init_platform_quirks();
         reserve_ebda_region();
 
         switch (boot_params.hdr.hardware_subarch) {
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index af1112980dd4..6f8902b0d151 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -555,62 +555,53 @@ early_idt_handler_common:
          */
         cld
 
-        cmpl $2,(%esp)          # X86_TRAP_NMI
-        je .Lis_nmi             # Ignore NMI
-
-        cmpl $2,%ss:early_recursion_flag
-        je hlt_loop
         incl %ss:early_recursion_flag
 
-        push %eax               # 16(%esp)
-        push %ecx               # 12(%esp)
-        push %edx               #  8(%esp)
-        push %ds                #  4(%esp)
-        push %es                #  0(%esp)
-        movl $(__KERNEL_DS),%eax
-        movl %eax,%ds
-        movl %eax,%es
-
-        cmpl $(__KERNEL_CS),32(%esp)
-        jne 10f
+        /* The vector number is in pt_regs->gs */
 
-        leal 28(%esp),%eax      # Pointer to %eip
-        call early_fixup_exception
-        andl %eax,%eax
-        jnz ex_entry            /* found an exception entry */
-
-10:
-#ifdef CONFIG_PRINTK
-        xorl %eax,%eax
-        movw %ax,2(%esp)        /* clean up the segment values on some cpus */
-        movw %ax,6(%esp)
-        movw %ax,34(%esp)
-        leal  40(%esp),%eax
-        pushl %eax              /* %esp before the exception */
-        pushl %ebx
-        pushl %ebp
-        pushl %esi
-        pushl %edi
-        movl %cr2,%eax
-        pushl %eax
-        pushl (20+6*4)(%esp)    /* trapno */
-        pushl $fault_msg
-        call printk
-#endif
-        call dump_stack
-hlt_loop:
-        hlt
-        jmp hlt_loop
-
-ex_entry:
-        pop %es
-        pop %ds
-        pop %edx
-        pop %ecx
-        pop %eax
-        decl %ss:early_recursion_flag
-.Lis_nmi:
-        addl $8,%esp            /* drop vector number and error code */
+        cld
+        pushl   %fs             /* pt_regs->fs */
+        movw    $0, 2(%esp)     /* clear high bits (some CPUs leave garbage) */
+        pushl   %es             /* pt_regs->es */
+        movw    $0, 2(%esp)     /* clear high bits (some CPUs leave garbage) */
+        pushl   %ds             /* pt_regs->ds */
+        movw    $0, 2(%esp)     /* clear high bits (some CPUs leave garbage) */
+        pushl   %eax            /* pt_regs->ax */
+        pushl   %ebp            /* pt_regs->bp */
+        pushl   %edi            /* pt_regs->di */
+        pushl   %esi            /* pt_regs->si */
+        pushl   %edx            /* pt_regs->dx */
+        pushl   %ecx            /* pt_regs->cx */
+        pushl   %ebx            /* pt_regs->bx */
+
+        /* Fix up DS and ES */
+        movl    $(__KERNEL_DS), %ecx
+        movl    %ecx, %ds
+        movl    %ecx, %es
+
+        /* Load the vector number into EDX */
+        movl    PT_GS(%esp), %edx
+
+        /* Load GS into pt_regs->gs and clear high bits */
+        movw    %gs, PT_GS(%esp)
+        movw    $0, PT_GS+2(%esp)
+
+        movl    %esp, %eax      /* args are pt_regs (EAX), trapnr (EDX) */
+        call    early_fixup_exception
+
+        popl    %ebx            /* pt_regs->bx */
+        popl    %ecx            /* pt_regs->cx */
+        popl    %edx            /* pt_regs->dx */
+        popl    %esi            /* pt_regs->si */
+        popl    %edi            /* pt_regs->di */
+        popl    %ebp            /* pt_regs->bp */
+        popl    %eax            /* pt_regs->ax */
+        popl    %ds             /* pt_regs->ds */
+        popl    %es             /* pt_regs->es */
+        popl    %fs             /* pt_regs->fs */
+        popl    %gs             /* pt_regs->gs */
+        decl    %ss:early_recursion_flag
+        addl    $4, %esp        /* pop pt_regs->orig_ax */
         iret
 ENDPROC(early_idt_handler_common)
 
@@ -647,10 +638,14 @@ ignore_int:
         popl %eax
 #endif
         iret
+
+hlt_loop:
+        hlt
+        jmp hlt_loop
 ENDPROC(ignore_int)
 __INITDATA
         .align 4
-early_recursion_flag:
+GLOBAL(early_recursion_flag)
         .long 0
 
 __REFDATA
@@ -715,19 +710,6 @@ __INITRODATA
 int_msg:
         .asciz "Unknown interrupt or fault at: %p %p %p\n"
 
-fault_msg:
-/* fault info: */
-        .ascii "BUG: Int %d: CR2 %p\n"
-/* regs pushed in early_idt_handler: */
-        .ascii "     EDI %p  ESI %p  EBP %p  EBX %p\n"
-        .ascii "     ESP %p   ES %p   DS %p\n"
-        .ascii "     EDX %p  ECX %p  EAX %p\n"
-/* fault frame: */
-        .ascii "     vec %p  err %p  EIP %p   CS %p  flg %p\n"
-        .ascii "Stack: %p %p %p %p %p %p %p %p\n"
-        .ascii "       %p %p %p %p %p %p %p %p\n"
-        .asciz "       %p %p %p %p %p %p %p %p\n"
-
 #include "../../x86/xen/xen-head.S"
 
 /*
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 22fbf9df61bb..5df831ef1442 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -20,6 +20,7 @@
 #include <asm/processor-flags.h>
 #include <asm/percpu.h>
 #include <asm/nops.h>
+#include "../entry/calling.h"
 
 #ifdef CONFIG_PARAVIRT
 #include <asm/asm-offsets.h>
@@ -64,6 +65,14 @@ startup_64:
          * tables and then reload them.
          */
 
+        /*
+         * Setup stack for verify_cpu(). "-8" because stack_start is defined
+         * this way, see below. Our best guess is a NULL ptr for stack
+         * termination heuristics and we don't want to break anything which
+         * might depend on it (kgdb, ...).
+         */
+        leaq    (__end_init_task - 8)(%rip), %rsp
+
         /* Sanitize CPU configuration */
         call verify_cpu
 
@@ -350,90 +359,48 @@ early_idt_handler_common:
          */
         cld
 
-        cmpl $2,(%rsp)          # X86_TRAP_NMI
-        je .Lis_nmi             # Ignore NMI
-
-        cmpl $2,early_recursion_flag(%rip)
-        jz  1f
         incl early_recursion_flag(%rip)
 
-        pushq %rax              # 64(%rsp)
-        pushq %rcx              # 56(%rsp)
-        pushq %rdx              # 48(%rsp)
-        pushq %rsi              # 40(%rsp)
-        pushq %rdi              # 32(%rsp)
-        pushq %r8               # 24(%rsp)
-        pushq %r9               # 16(%rsp)
-        pushq %r10              #  8(%rsp)
-        pushq %r11              #  0(%rsp)
-
-        cmpl $__KERNEL_CS,96(%rsp)
-        jne 11f
-
-        cmpl $14,72(%rsp)       # Page fault?
+        /* The vector number is currently in the pt_regs->di slot. */
+        pushq %rsi                              /* pt_regs->si */
+        movq 8(%rsp), %rsi                      /* RSI = vector number */
+        movq %rdi, 8(%rsp)                      /* pt_regs->di = RDI */
+        pushq %rdx                              /* pt_regs->dx */
+        pushq %rcx                              /* pt_regs->cx */
+        pushq %rax                              /* pt_regs->ax */
+        pushq %r8                               /* pt_regs->r8 */
+        pushq %r9                               /* pt_regs->r9 */
+        pushq %r10                              /* pt_regs->r10 */
+        pushq %r11                              /* pt_regs->r11 */
+        pushq %rbx                              /* pt_regs->bx */
+        pushq %rbp                              /* pt_regs->bp */
+        pushq %r12                              /* pt_regs->r12 */
+        pushq %r13                              /* pt_regs->r13 */
+        pushq %r14                              /* pt_regs->r14 */
+        pushq %r15                              /* pt_regs->r15 */
+
+        cmpq $14,%rsi           /* Page fault? */
         jnz 10f
-        GET_CR2_INTO(%rdi)      # can clobber any volatile register if pv
+        GET_CR2_INTO(%rdi)      /* Can clobber any volatile register if pv */
         call early_make_pgtable
         andl %eax,%eax
-        jz 20f                  # All good
+        jz 20f                  /* All good */
 
 10:
-        leaq 88(%rsp),%rdi      # Pointer to %rip
+        movq %rsp,%rdi          /* RDI = pt_regs; RSI is already trapnr */
         call early_fixup_exception
-        andl %eax,%eax
-        jnz 20f                 # Found an exception entry
-
-11:
-#ifdef CONFIG_EARLY_PRINTK
-        GET_CR2_INTO(%r9)       # can clobber any volatile register if pv
-        movl 80(%rsp),%r8d      # error code
-        movl 72(%rsp),%esi      # vector number
-        movl 96(%rsp),%edx      # %cs
-        movq 88(%rsp),%rcx      # %rip
-        xorl %eax,%eax
-        leaq early_idt_msg(%rip),%rdi
-        call early_printk
-        cmpl $2,early_recursion_flag(%rip)
-        jz  1f
-        call dump_stack
-#ifdef CONFIG_KALLSYMS  
-        leaq early_idt_ripmsg(%rip),%rdi
-        movq 40(%rsp),%rsi      # %rip again
-        call __print_symbol
-#endif
-#endif /* EARLY_PRINTK */
-1:      hlt
-        jmp 1b
-
-20:     # Exception table entry found or page table generated
-        popq %r11
-        popq %r10
-        popq %r9
-        popq %r8
-        popq %rdi
-        popq %rsi
-        popq %rdx
-        popq %rcx
-        popq %rax
+
+20:
         decl early_recursion_flag(%rip)
-.Lis_nmi:
-        addq $16,%rsp           # drop vector number and error code
-        INTERRUPT_RETURN
+        jmp restore_regs_and_iret
 ENDPROC(early_idt_handler_common)
 
         __INITDATA
 
         .balign 4
-early_recursion_flag:
+GLOBAL(early_recursion_flag)
         .long 0
 
-#ifdef CONFIG_EARLY_PRINTK
-early_idt_msg:
-        .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
-early_idt_ripmsg:
-        .asciz "RIP %s\n"
-#endif /* CONFIG_EARLY_PRINTK */
-
 #define NEXT_PAGE(name) \
         .balign PAGE_SIZE; \
 GLOBAL(name)
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index a1f0e4a5c47e..f112af7aa62e 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -54,7 +54,7 @@ struct hpet_dev {
         char                            name[10];
 };
 
-inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
+static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
 {
         return container_of(evtdev, struct hpet_dev, evt);
 }
@@ -773,7 +773,6 @@ static struct clocksource clocksource_hpet = {
         .mask           = HPET_MASK,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
         .resume         = hpet_resume_counter,
-        .archdata       = { .vclock_mode = VCLOCK_HPET },
 };
 
 static int hpet_clocksource_register(void)
diff --git a/arch/x86/kernel/jump_label.c b/arch/x86/kernel/jump_label.c
index e565e0e4d216..fc25f698d792 100644
--- a/arch/x86/kernel/jump_label.c
+++ b/arch/x86/kernel/jump_label.c
@@ -13,6 +13,7 @@
 #include <linux/cpu.h>
 #include <asm/kprobes.h>
 #include <asm/alternative.h>
+#include <asm/text-patching.h>
 
 #ifdef HAVE_JUMP_LABEL
 
diff --git a/arch/x86/kernel/kexec-bzimage64.c b/arch/x86/kernel/kexec-bzimage64.c
index 2af478e3fd4e..f2356bda2b05 100644
--- a/arch/x86/kernel/kexec-bzimage64.c
+++ b/arch/x86/kernel/kexec-bzimage64.c
@@ -19,8 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/efi.h>
-#include <linux/verify_pefile.h>
-#include <keys/system_keyring.h>
+#include <linux/verification.h>
 
 #include <asm/bootparam.h>
 #include <asm/setup.h>
@@ -529,18 +528,9 @@ static int bzImage64_cleanup(void *loader_data)
 #ifdef CONFIG_KEXEC_BZIMAGE_VERIFY_SIG
 static int bzImage64_verify_sig(const char *kernel, unsigned long kernel_len)
 {
-        bool trusted;
-        int ret;
-
-        ret = verify_pefile_signature(kernel, kernel_len,
-                                      system_trusted_keyring,
-                                      VERIFYING_KEXEC_PE_SIGNATURE,
-                                      &trusted);
-        if (ret < 0)
-                return ret;
-        if (!trusted)
-                return -EKEYREJECTED;
-        return 0;
+        return verify_pefile_signature(kernel, kernel_len,
+                                       NULL,
+                                       VERIFYING_KEXEC_PE_SIGNATURE);
 }
 #endif
 
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 2da6ee9ae69b..04cde527d728 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -45,6 +45,7 @@
 #include <linux/uaccess.h>
 #include <linux/memory.h>
 
+#include <asm/text-patching.h>
 #include <asm/debugreg.h>
 #include <asm/apicdef.h>
 #include <asm/apic.h>
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index ae703acb85c1..38cf7a741250 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -51,6 +51,7 @@
 #include <linux/ftrace.h>
 #include <linux/frame.h>
 
+#include <asm/text-patching.h>
 #include <asm/cacheflush.h>
 #include <asm/desc.h>
 #include <asm/pgtable.h>
diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c
index 7b3b9d15c47a..4425f593f0ec 100644
--- a/arch/x86/kernel/kprobes/opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -29,6 +29,7 @@
 #include <linux/kallsyms.h>
 #include <linux/ftrace.h>
 
+#include <asm/text-patching.h>
 #include <asm/cacheflush.h>
 #include <asm/desc.h>
 #include <asm/pgtable.h>
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index dc1207e2f193..eea2a6f72b31 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -285,14 +285,6 @@ static void __init paravirt_ops_setup(void)
 {
         pv_info.name = "KVM";
 
-        /*
-         * KVM isn't paravirt in the sense of paravirt_enabled.  A KVM
-         * guest kernel works like a bare metal kernel with additional
-         * features, and paravirt_enabled is about features that are
-         * missing.
-         */
-        pv_info.paravirt_enabled = 0;
-
         if (kvm_para_has_feature(KVM_FEATURE_NOP_IO_DELAY))
                 pv_cpu_ops.io_delay = kvm_io_delay;
 
diff --git a/arch/x86/kernel/livepatch.c b/arch/x86/kernel/livepatch.c
deleted file mode 100644
index 92fc1a51f994..000000000000
--- a/arch/x86/kernel/livepatch.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * livepatch.c - x86-specific Kernel Live Patching Core
- *
- * Copyright (C) 2014 Seth Jennings <sjenning@redhat.com>
- * Copyright (C) 2014 SUSE
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/module.h>
-#include <linux/uaccess.h>
-#include <asm/elf.h>
-#include <asm/livepatch.h>
-
-/**
- * klp_write_module_reloc() - write a relocation in a module
- * @mod:        module in which the section to be modified is found
- * @type:       ELF relocation type (see asm/elf.h)
- * @loc:        address that the relocation should be written to
- * @value:      relocation value (sym address + addend)
- *
- * This function writes a relocation to the specified location for
- * a particular module.
- */
-int klp_write_module_reloc(struct module *mod, unsigned long type,
-                           unsigned long loc, unsigned long value)
-{
-        size_t size = 4;
-        unsigned long val;
-        unsigned long core = (unsigned long)mod->core_layout.base;
-        unsigned long core_size = mod->core_layout.size;
-
-        switch (type) {
-        case R_X86_64_NONE:
-                return 0;
-        case R_X86_64_64:
-                val = value;
-                size = 8;
-                break;
-        case R_X86_64_32:
-                val = (u32)value;
-                break;
-        case R_X86_64_32S:
-                val = (s32)value;
-                break;
-        case R_X86_64_PC32:
-                val = (u32)(value - loc);
-                break;
-        default:
-                /* unsupported relocation type */
-                return -EINVAL;
-        }
-
-        if (loc < core || loc >= core + core_size)
-                /* loc does not point to any symbol inside the module */
-                return -EINVAL;
-
-        return probe_kernel_write((void *)loc, &val, size);
-}
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index ba7fbba9831b..5a294e48b185 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -538,3 +538,48 @@ overflow:
         return -ENOEXEC;
 }
 #endif /* CONFIG_KEXEC_FILE */
+
+static int
+kexec_mark_range(unsigned long start, unsigned long end, bool protect)
+{
+        struct page *page;
+        unsigned int nr_pages;
+
+        /*
+         * For physical range: [start, end]. We must skip the unassigned
+         * crashk resource with zero-valued "end" member.
+         */
+        if (!end || start > end)
+                return 0;
+
+        page = pfn_to_page(start >> PAGE_SHIFT);
+        nr_pages = (end >> PAGE_SHIFT) - (start >> PAGE_SHIFT) + 1;
+        if (protect)
+                return set_pages_ro(page, nr_pages);
+        else
+                return set_pages_rw(page, nr_pages);
+}
+
+static void kexec_mark_crashkres(bool protect)
+{
+        unsigned long control;
+
+        kexec_mark_range(crashk_low_res.start, crashk_low_res.end, protect);
+
+        /* Don't touch the control code page used in crash_kexec().*/
+        control = PFN_PHYS(page_to_pfn(kexec_crash_image->control_code_page));
+        /* Control code page is located in the 2nd page. */
+        kexec_mark_range(crashk_res.start, control + PAGE_SIZE - 1, protect);
+        control += KEXEC_CONTROL_PAGE_SIZE;
+        kexec_mark_range(control, crashk_res.end, protect);
+}
+
+void arch_kexec_protect_crashkres(void)
+{
+        kexec_mark_crashkres(true);
+}
+
+void arch_kexec_unprotect_crashkres(void)
+{
+        kexec_mark_crashkres(false);
+}
diff --git a/arch/x86/kernel/mcount_64.S b/arch/x86/kernel/mcount_64.S
index ed48a9f465f8..61924222a9e1 100644
--- a/arch/x86/kernel/mcount_64.S
+++ b/arch/x86/kernel/mcount_64.S
@@ -182,7 +182,8 @@ GLOBAL(ftrace_graph_call)
         jmp ftrace_stub
 #endif
 
-GLOBAL(ftrace_stub)
+/* This is weak to keep gas from relaxing the jumps */
+WEAK(ftrace_stub)
         retq
 END(ftrace_caller)
 
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index 005c03e93fc5..477ae806c2fa 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -31,6 +31,7 @@
 #include <linux/jump_label.h>
 #include <linux/random.h>
 
+#include <asm/text-patching.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/setup.h>
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index f08ac28b8136..7b3b3f24c3ea 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -294,7 +294,6 @@ enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
 
 struct pv_info pv_info = {
         .name = "bare hardware",
-        .paravirt_enabled = 0,
         .kernel_rpl = 0,
         .shared_kernel_pmd = 1, /* Only used when CONFIG_X86_PAE is set */
 
@@ -339,8 +338,10 @@ __visible struct pv_cpu_ops pv_cpu_ops = {
         .write_cr8 = native_write_cr8,
 #endif
         .wbinvd = native_wbinvd,
-        .read_msr = native_read_msr_safe,
-        .write_msr = native_write_msr_safe,
+        .read_msr = native_read_msr,
+        .write_msr = native_write_msr,
+        .read_msr_safe = native_read_msr_safe,
+        .write_msr_safe = native_write_msr_safe,
         .read_pmc = native_read_pmc,
         .load_tr_desc = native_load_tr_desc,
         .set_ldt = native_set_ldt,
diff --git a/arch/x86/kernel/pci-iommu_table.c b/arch/x86/kernel/pci-iommu_table.c
index 35ccf75696eb..f712dfdf1357 100644
--- a/arch/x86/kernel/pci-iommu_table.c
+++ b/arch/x86/kernel/pci-iommu_table.c
@@ -72,7 +72,7 @@ void __init check_iommu_entries(struct iommu_table_entry *start,
         }
 }
 #else
-inline void check_iommu_entries(struct iommu_table_entry *start,
+void __init check_iommu_entries(struct iommu_table_entry *start,
                                        struct iommu_table_entry *finish)
 {
 }
diff --git a/arch/x86/kernel/platform-quirks.c b/arch/x86/kernel/platform-quirks.c
new file mode 100644
index 000000000000..b2f8a33b36ff
--- /dev/null
+++ b/arch/x86/kernel/platform-quirks.c
@@ -0,0 +1,35 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/setup.h>
+#include <asm/bios_ebda.h>
+
+void __init x86_early_init_platform_quirks(void)
+{
+        x86_platform.legacy.rtc = 1;
+        x86_platform.legacy.ebda_search = 0;
+        x86_platform.legacy.devices.pnpbios = 1;
+
+        switch (boot_params.hdr.hardware_subarch) {
+        case X86_SUBARCH_PC:
+                x86_platform.legacy.ebda_search = 1;
+                break;
+        case X86_SUBARCH_XEN:
+        case X86_SUBARCH_LGUEST:
+        case X86_SUBARCH_INTEL_MID:
+        case X86_SUBARCH_CE4100:
+                x86_platform.legacy.devices.pnpbios = 0;
+                x86_platform.legacy.rtc = 0;
+                break;
+        }
+
+        if (x86_platform.set_legacy_features)
+                x86_platform.set_legacy_features();
+}
+
+#if defined(CONFIG_PNPBIOS)
+bool __init arch_pnpbios_disabled(void)
+{
+        return x86_platform.legacy.devices.pnpbios == 0;
+}
+#endif
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 2915d54e9dd5..96becbbb52e0 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -97,10 +97,9 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
 /*
  * Free current thread data structures etc..
  */
-void exit_thread(void)
+void exit_thread(struct task_struct *tsk)
 {
-        struct task_struct *me = current;
-        struct thread_struct *t = &me->thread;
+        struct thread_struct *t = &tsk->thread;
         unsigned long *bp = t->io_bitmap_ptr;
         struct fpu *fpu = &t->fpu;
 
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 6cbab31ac23a..6e789ca1f841 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -136,25 +136,6 @@ void release_thread(struct task_struct *dead_task)
         }
 }
 
-static inline void set_32bit_tls(struct task_struct *t, int tls, u32 addr)
-{
-        struct user_desc ud = {
-                .base_addr = addr,
-                .limit = 0xfffff,
-                .seg_32bit = 1,
-                .limit_in_pages = 1,
-                .useable = 1,
-        };
-        struct desc_struct *desc = t->thread.tls_array;
-        desc += tls;
-        fill_ldt(desc, &ud);
-}
-
-static inline u32 read_32bit_tls(struct task_struct *t, int tls)
-{
-        return get_desc_base(&t->thread.tls_array[tls]);
-}
-
 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
                 unsigned long arg, struct task_struct *p, unsigned long tls)
 {
@@ -169,9 +150,9 @@ int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
         p->thread.io_bitmap_ptr = NULL;
 
         savesegment(gs, p->thread.gsindex);
-        p->thread.gs = p->thread.gsindex ? 0 : me->thread.gs;
+        p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase;
         savesegment(fs, p->thread.fsindex);
-        p->thread.fs = p->thread.fsindex ? 0 : me->thread.fs;
+        p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase;
         savesegment(es, p->thread.es);
         savesegment(ds, p->thread.ds);
         memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
@@ -210,7 +191,7 @@ int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
          */
         if (clone_flags & CLONE_SETTLS) {
 #ifdef CONFIG_IA32_EMULATION
-                if (is_ia32_task())
+                if (in_ia32_syscall())
                         err = do_set_thread_area(p, -1,
                                 (struct user_desc __user *)tls, 0);
                 else
@@ -282,7 +263,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
         struct fpu *next_fpu = &next->fpu;
         int cpu = smp_processor_id();
         struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
-        unsigned fsindex, gsindex;
+        unsigned prev_fsindex, prev_gsindex;
         fpu_switch_t fpu_switch;
 
         fpu_switch = switch_fpu_prepare(prev_fpu, next_fpu, cpu);
@@ -292,8 +273,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
          *
          * (e.g. xen_load_tls())
          */
-        savesegment(fs, fsindex);
-        savesegment(gs, gsindex);
+        savesegment(fs, prev_fsindex);
+        savesegment(gs, prev_gsindex);
 
         /*
          * Load TLS before restoring any segments so that segment loads
@@ -336,66 +317,104 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
          * Switch FS and GS.
          *
          * These are even more complicated than DS and ES: they have
-         * 64-bit bases are that controlled by arch_prctl.  Those bases
-         * only differ from the values in the GDT or LDT if the selector
-         * is 0.
-         *
-         * Loading the segment register resets the hidden base part of
-         * the register to 0 or the value from the GDT / LDT.  If the
-         * next base address zero, writing 0 to the segment register is
-         * much faster than using wrmsr to explicitly zero the base.
-         *
-         * The thread_struct.fs and thread_struct.gs values are 0
-         * if the fs and gs bases respectively are not overridden
-         * from the values implied by fsindex and gsindex.  They
-         * are nonzero, and store the nonzero base addresses, if
-         * the bases are overridden.
-         *
-         * (fs != 0 && fsindex != 0) || (gs != 0 && gsindex != 0) should
-         * be impossible.
-         *
-         * Therefore we need to reload the segment registers if either
-         * the old or new selector is nonzero, and we need to override
-         * the base address if next thread expects it to be overridden.
+         * 64-bit bases are that controlled by arch_prctl.  The bases
+         * don't necessarily match the selectors, as user code can do
+         * any number of things to cause them to be inconsistent.
          *
-         * This code is unnecessarily slow in the case where the old and
-         * new indexes are zero and the new base is nonzero -- it will
-         * unnecessarily write 0 to the selector before writing the new
-         * base address.
+         * We don't promise to preserve the bases if the selectors are
+         * nonzero.  We also don't promise to preserve the base if the
+         * selector is zero and the base doesn't match whatever was
+         * most recently passed to ARCH_SET_FS/GS.  (If/when the
+         * FSGSBASE instructions are enabled, we'll need to offer
+         * stronger guarantees.)
          *
-         * Note: This all depends on arch_prctl being the only way that
-         * user code can override the segment base.  Once wrfsbase and
-         * wrgsbase are enabled, most of this code will need to change.
+         * As an invariant,
+         * (fsbase != 0 && fsindex != 0) || (gsbase != 0 && gsindex != 0) is
+         * impossible.
          */
-        if (unlikely(fsindex | next->fsindex | prev->fs)) {
+        if (next->fsindex) {
+                /* Loading a nonzero value into FS sets the index and base. */
                 loadsegment(fs, next->fsindex);
-
-                /*
-                 * If user code wrote a nonzero value to FS, then it also
-                 * cleared the overridden base address.
-                 *
-                 * XXX: if user code wrote 0 to FS and cleared the base
-                 * address itself, we won't notice and we'll incorrectly
-                 * restore the prior base address next time we reschdule
-                 * the process.
-                 */
-                if (fsindex)
-                        prev->fs = 0;
+        } else {
+                if (next->fsbase) {
+                        /* Next index is zero but next base is nonzero. */
+                        if (prev_fsindex)
+                                loadsegment(fs, 0);
+                        wrmsrl(MSR_FS_BASE, next->fsbase);
+                } else {
+                        /* Next base and index are both zero. */
+                        if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
+                                /*
+                                 * We don't know the previous base and can't
+                                 * find out without RDMSR.  Forcibly clear it.
+                                 */
+                                loadsegment(fs, __USER_DS);
+                                loadsegment(fs, 0);
+                        } else {
+                                /*
+                                 * If the previous index is zero and ARCH_SET_FS
+                                 * didn't change the base, then the base is
+                                 * also zero and we don't need to do anything.
+                                 */
+                                if (prev->fsbase || prev_fsindex)
+                                        loadsegment(fs, 0);
+                        }
+                }
         }
-        if (next->fs)
-                wrmsrl(MSR_FS_BASE, next->fs);
-        prev->fsindex = fsindex;
+        /*
+         * Save the old state and preserve the invariant.
+         * NB: if prev_fsindex == 0, then we can't reliably learn the base
+         * without RDMSR because Intel user code can zero it without telling
+         * us and AMD user code can program any 32-bit value without telling
+         * us.
+         */
+        if (prev_fsindex)
+                prev->fsbase = 0;
+        prev->fsindex = prev_fsindex;
 
-        if (unlikely(gsindex | next->gsindex | prev->gs)) {
+        if (next->gsindex) {
+                /* Loading a nonzero value into GS sets the index and base. */
                 load_gs_index(next->gsindex);
-
-                /* This works (and fails) the same way as fsindex above. */
-                if (gsindex)
-                        prev->gs = 0;
+        } else {
+                if (next->gsbase) {
+                        /* Next index is zero but next base is nonzero. */
+                        if (prev_gsindex)
+                                load_gs_index(0);
+                        wrmsrl(MSR_KERNEL_GS_BASE, next->gsbase);
+                } else {
+                        /* Next base and index are both zero. */
+                        if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
+                                /*
+                                 * We don't know the previous base and can't
+                                 * find out without RDMSR.  Forcibly clear it.
+                                 *
+                                 * This contains a pointless SWAPGS pair.
+                                 * Fixing it would involve an explicit check
+                                 * for Xen or a new pvop.
+                                 */
+                                load_gs_index(__USER_DS);
+                                load_gs_index(0);
+                        } else {
+                                /*
+                                 * If the previous index is zero and ARCH_SET_GS
+                                 * didn't change the base, then the base is
+                                 * also zero and we don't need to do anything.
+                                 */
+                                if (prev->gsbase || prev_gsindex)
+                                        load_gs_index(0);
+                        }
+                }
         }
-        if (next->gs)
-                wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
-        prev->gsindex = gsindex;
+        /*
+         * Save the old state and preserve the invariant.
+         * NB: if prev_gsindex == 0, then we can't reliably learn the base
+         * without RDMSR because Intel user code can zero it without telling
+         * us and AMD user code can program any 32-bit value without telling
+         * us.
+         */
+        if (prev_gsindex)
+                prev->gsbase = 0;
+        prev->gsindex = prev_gsindex;
 
         switch_fpu_finish(next_fpu, fpu_switch);
 
@@ -513,81 +532,47 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
 
         switch (code) {
         case ARCH_SET_GS:
-                if (addr >= TASK_SIZE_OF(task))
+                if (addr >= TASK_SIZE_MAX)
                         return -EPERM;
                 cpu = get_cpu();
-                /* handle small bases via the GDT because that's faster to
-                   switch. */
-                if (addr <= 0xffffffff) {
-                        set_32bit_tls(task, GS_TLS, addr);
-                        if (doit) {
-                                load_TLS(&task->thread, cpu);
-                                load_gs_index(GS_TLS_SEL);
-                        }
-                        task->thread.gsindex = GS_TLS_SEL;
-                        task->thread.gs = 0;
-                } else {
-                        task->thread.gsindex = 0;
-                        task->thread.gs = addr;
-                        if (doit) {
-                                load_gs_index(0);
-                                ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr);
-                        }
+                task->thread.gsindex = 0;
+                task->thread.gsbase = addr;
+                if (doit) {
+                        load_gs_index(0);
+                        ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr);
                 }
                 put_cpu();
                 break;
         case ARCH_SET_FS:
                 /* Not strictly needed for fs, but do it for symmetry
                    with gs */
-                if (addr >= TASK_SIZE_OF(task))
+                if (addr >= TASK_SIZE_MAX)
                         return -EPERM;
                 cpu = get_cpu();
-                /* handle small bases via the GDT because that's faster to
-                   switch. */
-                if (addr <= 0xffffffff) {
-                        set_32bit_tls(task, FS_TLS, addr);
-                        if (doit) {
-                                load_TLS(&task->thread, cpu);
-                                loadsegment(fs, FS_TLS_SEL);
-                        }
-                        task->thread.fsindex = FS_TLS_SEL;
-                        task->thread.fs = 0;
-                } else {
-                        task->thread.fsindex = 0;
-                        task->thread.fs = addr;
-                        if (doit) {
-                                /* set the selector to 0 to not confuse
-                                   __switch_to */
-                                loadsegment(fs, 0);
-                                ret = wrmsrl_safe(MSR_FS_BASE, addr);
-                        }
+                task->thread.fsindex = 0;
+                task->thread.fsbase = addr;
+                if (doit) {
+                        /* set the selector to 0 to not confuse __switch_to */
+                        loadsegment(fs, 0);
+                        ret = wrmsrl_safe(MSR_FS_BASE, addr);
                 }
                 put_cpu();
                 break;
         case ARCH_GET_FS: {
                 unsigned long base;
-                if (task->thread.fsindex == FS_TLS_SEL)
-                        base = read_32bit_tls(task, FS_TLS);
-                else if (doit)
+                if (doit)
                         rdmsrl(MSR_FS_BASE, base);
                 else
-                        base = task->thread.fs;
+                        base = task->thread.fsbase;
                 ret = put_user(base, (unsigned long __user *)addr);
                 break;
         }
         case ARCH_GET_GS: {
                 unsigned long base;
-                unsigned gsindex;
-                if (task->thread.gsindex == GS_TLS_SEL)
-                        base = read_32bit_tls(task, GS_TLS);
-                else if (doit) {
-                        savesegment(gs, gsindex);
-                        if (gsindex)
-                                rdmsrl(MSR_KERNEL_GS_BASE, base);
-                        else
-                                base = task->thread.gs;
-                } else
-                        base = task->thread.gs;
+                if (doit)
+                        rdmsrl(MSR_KERNEL_GS_BASE, base);
+                else
+                        base = task->thread.gsbase;
                 ret = put_user(base, (unsigned long __user *)addr);
                 break;
         }
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 32e9d9cbb884..600edd225e81 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -303,29 +303,11 @@ static int set_segment_reg(struct task_struct *task,
 
         switch (offset) {
         case offsetof(struct user_regs_struct,fs):
-                /*
-                 * If this is setting fs as for normal 64-bit use but
-                 * setting fs_base has implicitly changed it, leave it.
-                 */
-                if ((value == FS_TLS_SEL && task->thread.fsindex == 0 &&
-                     task->thread.fs != 0) ||
-                    (value == 0 && task->thread.fsindex == FS_TLS_SEL &&
-                     task->thread.fs == 0))
-                        break;
                 task->thread.fsindex = value;
                 if (task == current)
                         loadsegment(fs, task->thread.fsindex);
                 break;
         case offsetof(struct user_regs_struct,gs):
-                /*
-                 * If this is setting gs as for normal 64-bit use but
-                 * setting gs_base has implicitly changed it, leave it.
-                 */
-                if ((value == GS_TLS_SEL && task->thread.gsindex == 0 &&
-                     task->thread.gs != 0) ||
-                    (value == 0 && task->thread.gsindex == GS_TLS_SEL &&
-                     task->thread.gs == 0))
-                        break;
                 task->thread.gsindex = value;
                 if (task == current)
                         load_gs_index(task->thread.gsindex);
@@ -410,23 +392,23 @@ static int putreg(struct task_struct *child,
 
 #ifdef CONFIG_X86_64
         case offsetof(struct user_regs_struct,fs_base):
-                if (value >= TASK_SIZE_OF(child))
+                if (value >= TASK_SIZE_MAX)
                         return -EIO;
                 /*
                  * When changing the segment base, use do_arch_prctl
                  * to set either thread.fs or thread.fsindex and the
                  * corresponding GDT slot.
                  */
-                if (child->thread.fs != value)
+                if (child->thread.fsbase != value)
                         return do_arch_prctl(child, ARCH_SET_FS, value);
                 return 0;
         case offsetof(struct user_regs_struct,gs_base):
                 /*
                  * Exactly the same here as the %fs handling above.
                  */
-                if (value >= TASK_SIZE_OF(child))
+                if (value >= TASK_SIZE_MAX)
                         return -EIO;
-                if (child->thread.gs != value)
+                if (child->thread.gsbase != value)
                         return do_arch_prctl(child, ARCH_SET_GS, value);
                 return 0;
 #endif
@@ -453,31 +435,17 @@ static unsigned long getreg(struct task_struct *task, unsigned long offset)
 #ifdef CONFIG_X86_64
         case offsetof(struct user_regs_struct, fs_base): {
                 /*
-                 * do_arch_prctl may have used a GDT slot instead of
-                 * the MSR.  To userland, it appears the same either
-                 * way, except the %fs segment selector might not be 0.
+                 * XXX: This will not behave as expected if called on
+                 * current or if fsindex != 0.
                  */
-                unsigned int seg = task->thread.fsindex;
-                if (task->thread.fs != 0)
-                        return task->thread.fs;
-                if (task == current)
-                        asm("movl %%fs,%0" : "=r" (seg));
-                if (seg != FS_TLS_SEL)
-                        return 0;
-                return get_desc_base(&task->thread.tls_array[FS_TLS]);
+                return task->thread.fsbase;
         }
         case offsetof(struct user_regs_struct, gs_base): {
                 /*
-                 * Exactly the same here as the %fs handling above.
+                 * XXX: This will not behave as expected if called on
+                 * current or if fsindex != 0.
                  */
-                unsigned int seg = task->thread.gsindex;
-                if (task->thread.gs != 0)
-                        return task->thread.gs;
-                if (task == current)
-                        asm("movl %%gs,%0" : "=r" (seg));
-                if (seg != GS_TLS_SEL)
-                        return 0;
-                return get_desc_base(&task->thread.tls_array[GS_TLS]);
+                return task->thread.gsbase;
         }
 #endif
         }
@@ -1266,7 +1234,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         compat_ulong_t caddr, compat_ulong_t cdata)
 {
 #ifdef CONFIG_X86_X32_ABI
-        if (!is_ia32_task())
+        if (!in_ia32_syscall())
                 return x32_arch_ptrace(child, request, caddr, cdata);
 #endif
 #ifdef CONFIG_IA32_EMULATION
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index ab0adc0fa5db..a9b31eb815f2 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -535,6 +535,15 @@ static void native_machine_emergency_restart(void)
         mode = reboot_mode == REBOOT_WARM ? 0x1234 : 0;
         *((unsigned short *)__va(0x472)) = mode;
 
+        /*
+         * If an EFI capsule has been registered with the firmware then
+         * override the reboot= parameter.
+         */
+        if (efi_capsule_pending(NULL)) {
+                pr_info("EFI capsule is pending, forcing EFI reboot.\n");
+                reboot_type = BOOT_EFI;
+        }
+
         for (;;) {
                 /* Could also try the reset bit in the Hammer NB */
                 switch (reboot_type) {
diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index 4af8d063fb36..eceaa082ec3f 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -14,6 +14,7 @@
 #include <asm/time.h>
 #include <asm/intel-mid.h>
 #include <asm/rtc.h>
+#include <asm/setup.h>
 
 #ifdef CONFIG_X86_32
 /*
@@ -185,22 +186,7 @@ static __init int add_rtc_cmos(void)
                 }
         }
 #endif
-        if (of_have_populated_dt())
-                return 0;
-
-        /* Intel MID platforms don't have ioport rtc */
-        if (intel_mid_identify_cpu())
-                return -ENODEV;
-
-#ifdef CONFIG_ACPI
-        if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_CMOS_RTC) {
-                /* This warning can likely go away again in a year or two. */
-                pr_info("ACPI: not registering RTC platform device\n");
-                return -ENODEV;
-        }
-#endif
-
-        if (paravirt_enabled() && !paravirt_has(RTC))
+        if (!x86_platform.legacy.rtc)
                 return -ENODEV;
 
         platform_device_register(&rtc_device);
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 2367ae07eb76..c4e7b3991b60 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -398,6 +398,11 @@ static void __init reserve_initrd(void)
 
         memblock_free(ramdisk_image, ramdisk_end - ramdisk_image);
 }
+
+static void __init early_initrd_acpi_init(void)
+{
+        early_acpi_table_init((void *)initrd_start, initrd_end - initrd_start);
+}
 #else
 static void __init early_reserve_initrd(void)
 {
@@ -405,6 +410,9 @@ static void __init early_reserve_initrd(void)
 static void __init reserve_initrd(void)
 {
 }
+static void __init early_initrd_acpi_init(void)
+{
+}
 #endif /* CONFIG_BLK_DEV_INITRD */
 
 static void __init parse_setup_data(void)
@@ -1138,9 +1146,7 @@ void __init setup_arch(char **cmdline_p)
 
         reserve_initrd();
 
-#if defined(CONFIG_ACPI) && defined(CONFIG_BLK_DEV_INITRD)
-        acpi_initrd_override((void *)initrd_start, initrd_end - initrd_start);
-#endif
+        early_initrd_acpi_init();
 
         vsmp_init();
 
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 548ddf7d6fd2..22cc2f9f8aec 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -248,18 +248,17 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size,
         if (config_enabled(CONFIG_X86_64))
                 sp -= 128;
 
-        if (!onsigstack) {
-                /* This is the X/Open sanctioned signal stack switching.  */
-                if (ka->sa.sa_flags & SA_ONSTACK) {
-                        if (current->sas_ss_size)
-                                sp = current->sas_ss_sp + current->sas_ss_size;
-                } else if (config_enabled(CONFIG_X86_32) &&
-                           (regs->ss & 0xffff) != __USER_DS &&
-                           !(ka->sa.sa_flags & SA_RESTORER) &&
-                           ka->sa.sa_restorer) {
-                                /* This is the legacy signal stack switching. */
-                                sp = (unsigned long) ka->sa.sa_restorer;
-                }
+        /* This is the X/Open sanctioned signal stack switching.  */
+        if (ka->sa.sa_flags & SA_ONSTACK) {
+                if (sas_ss_flags(sp) == 0)
+                        sp = current->sas_ss_sp + current->sas_ss_size;
+        } else if (config_enabled(CONFIG_X86_32) &&
+                   !onsigstack &&
+                   (regs->ss & 0xffff) != __USER_DS &&
+                   !(ka->sa.sa_flags & SA_RESTORER) &&
+                   ka->sa.sa_restorer) {
+                /* This is the legacy signal stack switching. */
+                sp = (unsigned long) ka->sa.sa_restorer;
         }
 
         if (fpu->fpstate_active) {
@@ -391,7 +390,7 @@ static int __setup_rt_frame(int sig, struct ksignal *ksig,
                 put_user_ex(&frame->uc, &frame->puc);
 
                 /* Create the ucontext.  */
-                if (cpu_has_xsave)
+                if (boot_cpu_has(X86_FEATURE_XSAVE))
                         put_user_ex(UC_FP_XSTATE, &frame->uc.uc_flags);
                 else
                         put_user_ex(0, &frame->uc.uc_flags);
@@ -442,7 +441,7 @@ static unsigned long frame_uc_flags(struct pt_regs *regs)
 {
         unsigned long flags;
 
-        if (cpu_has_xsave)
+        if (boot_cpu_has(X86_FEATURE_XSAVE))
                 flags = UC_FP_XSTATE | UC_SIGCONTEXT_SS;
         else
                 flags = UC_SIGCONTEXT_SS;
@@ -762,7 +761,7 @@ handle_signal(struct ksignal *ksig, struct pt_regs *regs)
 static inline unsigned long get_nr_restart_syscall(const struct pt_regs *regs)
 {
 #ifdef CONFIG_X86_64
-        if (is_ia32_task())
+        if (in_ia32_syscall())
                 return __NR_ia32_restart_syscall;
 #endif
 #ifdef CONFIG_X86_X32_ABI
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index a2065d3b3b39..fafe8b923cac 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -332,6 +332,11 @@ static void __init smp_init_package_map(void)
          * primary cores.
          */
         ncpus = boot_cpu_data.x86_max_cores;
+        if (!ncpus) {
+                pr_warn("x86_max_cores == zero !?!?");
+                ncpus = 1;
+        }
+
         __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
 
         /*
@@ -1231,7 +1236,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
          * If we couldn't find a local APIC, then get out of here now!
          */
         if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
-            !cpu_has_apic) {
+            !boot_cpu_has(X86_FEATURE_APIC)) {
                 if (!disable_apic) {
                         pr_err("BIOS bug, local APIC #%d not detected!...\n",
                                 boot_cpu_physical_apicid);
diff --git a/arch/x86/kernel/sysfb_efi.c b/arch/x86/kernel/sysfb_efi.c
index b285d4e8c68e..623965e86b65 100644
--- a/arch/x86/kernel/sysfb_efi.c
+++ b/arch/x86/kernel/sysfb_efi.c
@@ -68,6 +68,21 @@ struct efifb_dmi_info efifb_dmi_list[] = {
         [M_UNKNOWN] = { NULL, 0, 0, 0, 0, OVERRIDE_NONE }
 };
 
+void efifb_setup_from_dmi(struct screen_info *si, const char *opt)
+{
+        int i;
+
+        for (i = 0; i < M_UNKNOWN; i++) {
+                if (efifb_dmi_list[i].base != 0 &&
+                    !strcmp(opt, efifb_dmi_list[i].optname)) {
+                        si->lfb_base = efifb_dmi_list[i].base;
+                        si->lfb_linelength = efifb_dmi_list[i].stride;
+                        si->lfb_width = efifb_dmi_list[i].width;
+                        si->lfb_height = efifb_dmi_list[i].height;
+                }
+        }
+}
+
 #define choose_value(dmivalue, fwvalue, field, flags) ({        \
                 typeof(fwvalue) _ret_ = fwvalue;                \
                 if ((flags) & (field))                          \
@@ -106,14 +121,24 @@ static int __init efifb_set_system(const struct dmi_system_id *id)
                                         continue;
                                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
                                         resource_size_t start, end;
+                                        unsigned long flags;
+
+                                        flags = pci_resource_flags(dev, i);
+                                        if (!(flags & IORESOURCE_MEM))
+                                                continue;
+
+                                        if (flags & IORESOURCE_UNSET)
+                                                continue;
+
+                                        if (pci_resource_len(dev, i) == 0)
+                                                continue;
 
                                         start = pci_resource_start(dev, i);
-                                        if (start == 0)
-                                                break;
                                         end = pci_resource_end(dev, i);
                                         if (screen_info.lfb_base >= start &&
                                             screen_info.lfb_base < end) {
                                                 found_bar = 1;
+                                                break;
                                         }
                                 }
                         }
diff --git a/arch/x86/kernel/tboot.c b/arch/x86/kernel/tboot.c
index e72a07f20b05..9b0185fbe3eb 100644
--- a/arch/x86/kernel/tboot.c
+++ b/arch/x86/kernel/tboot.c
@@ -74,12 +74,6 @@ void __init tboot_probe(void)
                 return;
         }
 
-        /* only a natively booted kernel should be using TXT */
-        if (paravirt_enabled()) {
-                pr_warning("non-0 tboot_addr but pv_ops is enabled\n");
-                return;
-        }
-
         /* Map and check for tboot UUID. */
         set_fixmap(FIX_TBOOT_BASE, boot_params.tboot_addr);
         tboot = (struct tboot *)fix_to_virt(FIX_TBOOT_BASE);
diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c
index 7fc5e843f247..9692a5e9fdab 100644
--- a/arch/x86/kernel/tls.c
+++ b/arch/x86/kernel/tls.c
@@ -114,6 +114,7 @@ int do_set_thread_area(struct task_struct *p, int idx,
                        int can_allocate)
 {
         struct user_desc info;
+        unsigned short __maybe_unused sel, modified_sel;
 
         if (copy_from_user(&info, u_info, sizeof(info)))
                 return -EFAULT;
@@ -141,6 +142,47 @@ int do_set_thread_area(struct task_struct *p, int idx,
 
         set_tls_desc(p, idx, &info, 1);
 
+        /*
+         * If DS, ES, FS, or GS points to the modified segment, forcibly
+         * refresh it.  Only needed on x86_64 because x86_32 reloads them
+         * on return to user mode.
+         */
+        modified_sel = (idx << 3) | 3;
+
+        if (p == current) {
+#ifdef CONFIG_X86_64
+                savesegment(ds, sel);
+                if (sel == modified_sel)
+                        loadsegment(ds, sel);
+
+                savesegment(es, sel);
+                if (sel == modified_sel)
+                        loadsegment(es, sel);
+
+                savesegment(fs, sel);
+                if (sel == modified_sel)
+                        loadsegment(fs, sel);
+
+                savesegment(gs, sel);
+                if (sel == modified_sel)
+                        load_gs_index(sel);
+#endif
+
+#ifdef CONFIG_X86_32_LAZY_GS
+                savesegment(gs, sel);
+                if (sel == modified_sel)
+                        loadsegment(gs, sel);
+#endif
+        } else {
+#ifdef CONFIG_X86_64
+                if (p->thread.fsindex == modified_sel)
+                        p->thread.fsbase = info.base_addr;
+
+                if (p->thread.gsindex == modified_sel)
+                        p->thread.gsbase = info.base_addr;
+#endif
+        }
+
         return 0;
 }
 
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 06cbe25861f1..d1590486204a 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -51,6 +51,7 @@
 #include <asm/processor.h>
 #include <asm/debugreg.h>
 #include <linux/atomic.h>
+#include <asm/text-patching.h>
 #include <asm/ftrace.h>
 #include <asm/traps.h>
 #include <asm/desc.h>
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index c9c4c7ce3eb2..38ba6de56ede 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -36,7 +36,7 @@ static int __read_mostly tsc_unstable;
 
 /* native_sched_clock() is called before tsc_init(), so
    we must start with the TSC soft disabled to prevent
-   erroneous rdtsc usage on !cpu_has_tsc processors */
+   erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
 static int __read_mostly tsc_disabled = -1;
 
 static DEFINE_STATIC_KEY_FALSE(__use_tsc);
@@ -834,15 +834,15 @@ int recalibrate_cpu_khz(void)
 #ifndef CONFIG_SMP
         unsigned long cpu_khz_old = cpu_khz;
 
-        if (cpu_has_tsc) {
-                tsc_khz = x86_platform.calibrate_tsc();
-                cpu_khz = tsc_khz;
-                cpu_data(0).loops_per_jiffy =
-                        cpufreq_scale(cpu_data(0).loops_per_jiffy,
-                                        cpu_khz_old, cpu_khz);
-                return 0;
-        } else
+        if (!boot_cpu_has(X86_FEATURE_TSC))
                 return -ENODEV;
+
+        tsc_khz = x86_platform.calibrate_tsc();
+        cpu_khz = tsc_khz;
+        cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
+                                                    cpu_khz_old, cpu_khz);
+
+        return 0;
 #else
         return -ENODEV;
 #endif
@@ -922,9 +922,6 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
         struct cpufreq_freqs *freq = data;
         unsigned long *lpj;
 
-        if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
-                return 0;
-
         lpj = &boot_cpu_data.loops_per_jiffy;
 #ifdef CONFIG_SMP
         if (!(freq->flags & CPUFREQ_CONST_LOOPS))
@@ -954,9 +951,9 @@ static struct notifier_block time_cpufreq_notifier_block = {
         .notifier_call  = time_cpufreq_notifier
 };
 
-static int __init cpufreq_tsc(void)
+static int __init cpufreq_register_tsc_scaling(void)
 {
-        if (!cpu_has_tsc)
+        if (!boot_cpu_has(X86_FEATURE_TSC))
                 return 0;
         if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
                 return 0;
@@ -965,7 +962,7 @@ static int __init cpufreq_tsc(void)
         return 0;
 }
 
-core_initcall(cpufreq_tsc);
+core_initcall(cpufreq_register_tsc_scaling);
 
 #endif /* CONFIG_CPU_FREQ */
 
@@ -1081,7 +1078,7 @@ static void __init check_system_tsc_reliable(void)
  */
 int unsynchronized_tsc(void)
 {
-        if (!cpu_has_tsc || tsc_unstable)
+        if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
                 return 1;
 
 #ifdef CONFIG_SMP
@@ -1205,7 +1202,7 @@ out:
 
 static int __init init_tsc_clocksource(void)
 {
-        if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
+        if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
                 return 0;
 
         if (tsc_clocksource_reliable)
@@ -1242,7 +1239,7 @@ void __init tsc_init(void)
         u64 lpj;
         int cpu;
 
-        if (!cpu_has_tsc) {
+        if (!boot_cpu_has(X86_FEATURE_TSC)) {
                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
                 return;
         }
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 92ae6acac8a7..9911a0620f9a 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -23,6 +23,7 @@
 #include <asm/param.h>
 
 /* CPU reference clock frequency: in KHz */
+#define FREQ_80         80000
 #define FREQ_83         83200
 #define FREQ_100        99840
 #define FREQ_133        133200
@@ -56,6 +57,8 @@ static struct freq_desc freq_desc_tables[] = {
         { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
         /* ANN */
         { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+        /* AIRMONT */
+        { 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80, 0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
@@ -92,7 +95,7 @@ unsigned long try_msr_calibrate_tsc(void)
 
         if (freq_desc_tables[cpu_index].msr_plat) {
                 rdmsr(MSR_PLATFORM_INFO, lo, hi);
-                ratio = (lo >> 8) & 0x1f;
+                ratio = (lo >> 8) & 0xff;
         } else {
                 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
                 ratio = (hi >> 8) & 0x1f;
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c
index bf4db6eaec8f..6c1ff31d99ff 100644
--- a/arch/x86/kernel/uprobes.c
+++ b/arch/x86/kernel/uprobes.c
@@ -516,7 +516,7 @@ struct uprobe_xol_ops {
 
 static inline int sizeof_long(void)
 {
-        return is_ia32_task() ? 4 : 8;
+        return in_ia32_syscall() ? 4 : 8;
 }
 
 static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
@@ -578,7 +578,7 @@ static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
         riprel_post_xol(auprobe, regs);
 }
 
-static struct uprobe_xol_ops default_xol_ops = {
+static const struct uprobe_xol_ops default_xol_ops = {
         .pre_xol  = default_pre_xol_op,
         .post_xol = default_post_xol_op,
         .abort    = default_abort_op,
@@ -695,7 +695,7 @@ static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn)
                 0, insn->immediate.nbytes);
 }
 
-static struct uprobe_xol_ops branch_xol_ops = {
+static const struct uprobe_xol_ops branch_xol_ops = {
         .emulate  = branch_emulate_op,
         .post_xol = branch_post_xol_op,
 };
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 4c941f88d405..9297a002d8e5 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -334,7 +334,7 @@ SECTIONS
                 __brk_limit = .;
         }
 
-        . = ALIGN(PAGE_SIZE);
+        . = ALIGN(PAGE_SIZE);           /* keep VO_INIT_SIZE page aligned */
         _end = .;
 
         STABS_DEBUG