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authorLen Brown <len.brown@intel.com>2016-06-17 01:22:45 -0400
committerIngo Molnar <mingo@kernel.org>2016-07-10 11:00:13 -0400
commit14bb4e34860af48ef1ea0f52b11611ce4db987fe (patch)
tree0d40b2413323ee87d883fb961a11926f56283d99 /arch/x86/kernel
parentba8268330dc18d309a39175ea4d2c5d86c2cef09 (diff)
x86/tsc_msr: Remove debugging messages
Debugging messages are not necessary after all of the possible hardware failures that never occur. Instead, this code can simply return 0. This code also doesn't need to print in the success case. tsc_init() already prints the TSC frequency, and apic=debug is available if anybody really is interested in printing the LAPIC frequency. Signed-off-by: Len Brown <len.brown@intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/cf03279a125b95dfa9b8d3d5b4a66de09cd04050.1466138954.git.len.brown@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r--arch/x86/kernel/tsc_msr.c19
1 files changed, 3 insertions, 16 deletions
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 4ec5e560ed73..f7ba44b89cc4 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -76,9 +76,10 @@ static int match_cpu(u8 family, u8 model)
76 (freq_desc_tables[cpu_index].freqs[freq_id]) 76 (freq_desc_tables[cpu_index].freqs[freq_id])
77 77
78/* 78/*
79 * Do MSR calibration only for known/supported CPUs. 79 * MSR-based CPU/TSC frequency discovery for certain CPUs.
80 * 80 *
81 * Returns the calibration value or 0 if MSR calibration failed. 81 * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
82 * Return processor base frequency in KHz, or 0 on failure.
82 */ 83 */
83unsigned long try_msr_calibrate_tsc(void) 84unsigned long try_msr_calibrate_tsc(void)
84{ 85{
@@ -100,31 +101,17 @@ unsigned long try_msr_calibrate_tsc(void)
100 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); 101 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
101 ratio = (hi >> 8) & 0x1f; 102 ratio = (hi >> 8) & 0x1f;
102 } 103 }
103 pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
104
105 if (!ratio)
106 goto fail;
107 104
108 /* Get FSB FREQ ID */ 105 /* Get FSB FREQ ID */
109 rdmsr(MSR_FSB_FREQ, lo, hi); 106 rdmsr(MSR_FSB_FREQ, lo, hi);
110 freq_id = lo & 0x7; 107 freq_id = lo & 0x7;
111 freq = id_to_freq(cpu_index, freq_id); 108 freq = id_to_freq(cpu_index, freq_id);
112 pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
113 freq_id, freq);
114 if (!freq)
115 goto fail;
116 109
117 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ 110 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
118 res = freq * ratio; 111 res = freq * ratio;
119 pr_info("TSC runs at %lu KHz\n", res);
120 112
121#ifdef CONFIG_X86_LOCAL_APIC 113#ifdef CONFIG_X86_LOCAL_APIC
122 lapic_timer_frequency = (freq * 1000) / HZ; 114 lapic_timer_frequency = (freq * 1000) / HZ;
123 pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
124#endif 115#endif
125 return res; 116 return res;
126
127fail:
128 pr_warn("Fast TSC calibration using MSR failed\n");
129 return 0;
130} 117}