x86/fpu: Rename XSAVE macros

There are two concepts that have some confusing naming:
 1. Extended State Component numbers (currently called
    XFEATURE_BIT_*)
 2. Extended State Component masks (currently called XSTATE_*)

The numbers are (currently) from 0-9.  State component 3 is the
bounds registers for MPX, for instance.

But when we want to enable "state component 3", we go set a bit
in XCR0.  The bit we set is 1<<3.  We can check to see if a
state component feature is enabled by looking at its bit.

The current 'xfeature_bit's are at best xfeature bit _numbers_.
Calling them bits is at best inconsistent with ending the enum
list with 'XFEATURES_NR_MAX'.

This patch renames the enum to be 'xfeature'.  These also
happen to be what the Intel documentation calls a "state
component".

We also want to differentiate these from the "XSTATE_*" macros.
The "XSTATE_*" macros are a mask, and we rename them to match.

These macros are reasonably widely used so this patch is a
wee bit big, but this really is just a rename.

The only non-mechanical part of this is the

	s/XSTATE_EXTEND_MASK/XFEATURE_MASK_EXTEND/

We need a better name for it, but that's another patch.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: dave@sr71.net
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/20150902233126.38653250@viggo.jf.intel.com
[ Ported to v4.3-rc1. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>

2 files changed, 34 insertions, 24 deletions

diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h
index 5dc1a18ef11c..9f20d10af3b1 100644
--- a/arch/x86/include/asm/fpu/types.h
+++ b/arch/x86/include/asm/fpu/types.h
@@ -95,30 +95,36 @@ struct swregs_state {
 /*
  * List of XSAVE features Linux knows about:
  */
-enum xfeature_bit {
-        XSTATE_BIT_FP,
-        XSTATE_BIT_SSE,
-        XSTATE_BIT_YMM,
-        XSTATE_BIT_BNDREGS,
-        XSTATE_BIT_BNDCSR,
-        XSTATE_BIT_OPMASK,
-        XSTATE_BIT_ZMM_Hi256,
-        XSTATE_BIT_Hi16_ZMM,
+enum xfeature {
+        XFEATURE_FP,
+        XFEATURE_SSE,
+        /*
+         * Values above here are "legacy states".
+         * Those below are "extended states".
+         */
+        XFEATURE_YMM,
+        XFEATURE_BNDREGS,
+        XFEATURE_BNDCSR,
+        XFEATURE_OPMASK,
+        XFEATURE_ZMM_Hi256,
+        XFEATURE_Hi16_ZMM,
 
         XFEATURES_NR_MAX,
 };
 
-#define XSTATE_FP               (1 << XSTATE_BIT_FP)
-#define XSTATE_SSE              (1 << XSTATE_BIT_SSE)
-#define XSTATE_YMM              (1 << XSTATE_BIT_YMM)
-#define XSTATE_BNDREGS          (1 << XSTATE_BIT_BNDREGS)
-#define XSTATE_BNDCSR           (1 << XSTATE_BIT_BNDCSR)
-#define XSTATE_OPMASK           (1 << XSTATE_BIT_OPMASK)
-#define XSTATE_ZMM_Hi256        (1 << XSTATE_BIT_ZMM_Hi256)
-#define XSTATE_Hi16_ZMM         (1 << XSTATE_BIT_Hi16_ZMM)
+#define XFEATURE_MASK_FP                (1 << XFEATURE_FP)
+#define XFEATURE_MASK_SSE               (1 << XFEATURE_SSE)
+#define XFEATURE_MASK_YMM               (1 << XFEATURE_YMM)
+#define XFEATURE_MASK_BNDREGS           (1 << XFEATURE_BNDREGS)
+#define XFEATURE_MASK_BNDCSR            (1 << XFEATURE_BNDCSR)
+#define XFEATURE_MASK_OPMASK            (1 << XFEATURE_OPMASK)
+#define XFEATURE_MASK_ZMM_Hi256         (1 << XFEATURE_ZMM_Hi256)
+#define XFEATURE_MASK_Hi16_ZMM          (1 << XFEATURE_Hi16_ZMM)
 
-#define XSTATE_FPSSE            (XSTATE_FP | XSTATE_SSE)
-#define XSTATE_AVX512           (XSTATE_OPMASK | XSTATE_ZMM_Hi256 | XSTATE_Hi16_ZMM)
+#define XFEATURE_MASK_FPSSE             (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
+#define XFEATURE_MASK_AVX512            (XFEATURE_MASK_OPMASK \
+                                         | XFEATURE_MASK_ZMM_Hi256 \
+                                         | XFEATURE_MASK_Hi16_ZMM)
 
 /*
  * There are 16x 256-bit AVX registers named YMM0-YMM15.
diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h
index d5a9b736553c..3a6c89b70307 100644
--- a/arch/x86/include/asm/fpu/xstate.h
+++ b/arch/x86/include/asm/fpu/xstate.h
@@ -6,7 +6,7 @@
 #include <linux/uaccess.h>
 
 /* Bit 63 of XCR0 is reserved for future expansion */
-#define XSTATE_EXTEND_MASK      (~(XSTATE_FPSSE | (1ULL << 63)))
+#define XFEATURE_MASK_EXTEND    (~(XFEATURE_MASK_FPSSE | (1ULL << 63)))
 
 #define XSTATE_CPUID            0x0000000d
 
@@ -19,14 +19,18 @@
 #define XSAVE_YMM_OFFSET    (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
 
 /* Supported features which support lazy state saving */
-#define XSTATE_LAZY     (XSTATE_FP | XSTATE_SSE | XSTATE_YMM                  \
-                        | XSTATE_OPMASK | XSTATE_ZMM_Hi256 | XSTATE_Hi16_ZMM)
+#define XFEATURE_MASK_LAZY      (XFEATURE_MASK_FP | \
+                                 XFEATURE_MASK_SSE | \
+                                 XFEATURE_MASK_YMM | \
+                                 XFEATURE_MASK_OPMASK | \
+                                 XFEATURE_MASK_ZMM_Hi256 | \
+                                 XFEATURE_MASK_Hi16_ZMM)
 
 /* Supported features which require eager state saving */
-#define XSTATE_EAGER    (XSTATE_BNDREGS | XSTATE_BNDCSR)
+#define XFEATURE_MASK_EAGER     (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)
 
 /* All currently supported features */
-#define XCNTXT_MASK     (XSTATE_LAZY | XSTATE_EAGER)
+#define XCNTXT_MASK     (XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER)
 
 #ifdef CONFIG_X86_64
 #define REX_PREFIX      "0x48, "