x86/mm: Add barriers and document switch_mm()-vs-flush synchronization

When switch_mm() activates a new PGD, it also sets a bit that
tells other CPUs that the PGD is in use so that TLB flush IPIs
will be sent.  In order for that to work correctly, the bit
needs to be visible prior to loading the PGD and therefore
starting to fill the local TLB.

Document all the barriers that make this work correctly and add
a couple that were missing.

Signed-off-by: Andy Lutomirski <luto@kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mm@kvack.org
Cc: stable@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 32 insertions, 1 deletions

diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 379cd3658799..1edc9cd198b8 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -116,8 +116,34 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #endif
                 cpumask_set_cpu(cpu, mm_cpumask(next));
 
-                /* Re-load page tables */
+                /*
+                 * Re-load page tables.
+                 *
+                 * This logic has an ordering constraint:
+                 *
+                 *  CPU 0: Write to a PTE for 'next'
+                 *  CPU 0: load bit 1 in mm_cpumask.  if nonzero, send IPI.
+                 *  CPU 1: set bit 1 in next's mm_cpumask
+                 *  CPU 1: load from the PTE that CPU 0 writes (implicit)
+                 *
+                 * We need to prevent an outcome in which CPU 1 observes
+                 * the new PTE value and CPU 0 observes bit 1 clear in
+                 * mm_cpumask.  (If that occurs, then the IPI will never
+                 * be sent, and CPU 0's TLB will contain a stale entry.)
+                 *
+                 * The bad outcome can occur if either CPU's load is
+                 * reordered before that CPU's store, so both CPUs much
+                 * execute full barriers to prevent this from happening.
+                 *
+                 * Thus, switch_mm needs a full barrier between the
+                 * store to mm_cpumask and any operation that could load
+                 * from next->pgd.  This barrier synchronizes with
+                 * remote TLB flushers.  Fortunately, load_cr3 is
+                 * serializing and thus acts as a full barrier.
+                 *
+                 */
                 load_cr3(next->pgd);
+
                 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
 
                 /* Stop flush ipis for the previous mm */
@@ -156,10 +182,15 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                          * schedule, protecting us from simultaneous changes.
                          */
                         cpumask_set_cpu(cpu, mm_cpumask(next));
+
                         /*
                          * We were in lazy tlb mode and leave_mm disabled
                          * tlb flush IPI delivery. We must reload CR3
                          * to make sure to use no freed page tables.
+                         *
+                         * As above, this is a barrier that forces
+                         * TLB repopulation to be ordered after the
+                         * store to mm_cpumask.
                          */
                         load_cr3(next->pgd);
                         trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);