Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (99 commits)
  drivers/virt: add missing linux/interrupt.h to fsl_hypervisor.c
  powerpc/85xx: fix mpic configuration in CAMP mode
  powerpc: Copy back TIF flags on return from softirq stack
  powerpc/64: Make server perfmon only built on ppc64 server devices
  powerpc/pseries: Fix hvc_vio.c build due to recent changes
  powerpc: Exporting boot_cpuid_phys
  powerpc: Add CFAR to oops output
  hvc_console: Add kdb support
  powerpc/pseries: Fix hvterm_raw_get_chars to accept < 16 chars, fixing xmon
  powerpc/irq: Quieten irq mapping printks
  powerpc: Enable lockup and hung task detectors in pseries and ppc64 defeconfigs
  powerpc: Add mpt2sas driver to pseries and ppc64 defconfig
  powerpc: Disable IRQs off tracer in ppc64 defconfig
  powerpc: Sync pseries and ppc64 defconfigs
  powerpc/pseries/hvconsole: Fix dropped console output
  hvc_console: Improve tty/console put_chars handling
  powerpc/kdump: Fix timeout in crash_kexec_wait_realmode
  powerpc/mm: Fix output of total_ram.
  powerpc/cpufreq: Add cpufreq driver for Momentum Maple boards
  powerpc: Correct annotations of pmu registration functions
  ...

Fix up trivial Kconfig/Makefile conflicts in arch/powerpc, drivers, and
drivers/cpufreq

7 files changed, 438 insertions, 163 deletions

diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 0efa990e3344..cf736ca0cf05 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64)		:= -mno-minimal-toc
 
 mpic-msi-obj-$(CONFIG_PCI_MSI)  += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
 obj-$(CONFIG_MPIC)              += mpic.o $(mpic-msi-obj-y)
+obj-$(CONFIG_PPC_EPAPR_HV_PIC)  += ehv_pic.o
 fsl-msi-obj-$(CONFIG_PCI_MSI)   += fsl_msi.o
 obj-$(CONFIG_PPC_MSI_BITMAP)    += msi_bitmap.o
 
diff --git a/arch/powerpc/sysdev/ehv_pic.c b/arch/powerpc/sysdev/ehv_pic.c
new file mode 100644
index 000000000000..af1a5df46b3e
--- /dev/null
+++ b/arch/powerpc/sysdev/ehv_pic.c
@@ -0,0 +1,302 @@
+/*
+ *  Driver for ePAPR Embedded Hypervisor PIC
+ *
+ *  Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ *  Author: Ashish Kalra <ashish.kalra@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/smp.h>
+#include <asm/machdep.h>
+#include <asm/ehv_pic.h>
+#include <asm/fsl_hcalls.h>
+
+#include "../../../kernel/irq/settings.h"
+
+static struct ehv_pic *global_ehv_pic;
+static DEFINE_SPINLOCK(ehv_pic_lock);
+
+static u32 hwirq_intspec[NR_EHV_PIC_INTS];
+static u32 __iomem *mpic_percpu_base_vaddr;
+
+#define IRQ_TYPE_MPIC_DIRECT 4
+#define MPIC_EOI  0x00B0
+
+/*
+ * Linux descriptor level callbacks
+ */
+
+void ehv_pic_unmask_irq(struct irq_data *d)
+{
+        unsigned int src = virq_to_hw(d->irq);
+
+        ev_int_set_mask(src, 0);
+}
+
+void ehv_pic_mask_irq(struct irq_data *d)
+{
+        unsigned int src = virq_to_hw(d->irq);
+
+        ev_int_set_mask(src, 1);
+}
+
+void ehv_pic_end_irq(struct irq_data *d)
+{
+        unsigned int src = virq_to_hw(d->irq);
+
+        ev_int_eoi(src);
+}
+
+void ehv_pic_direct_end_irq(struct irq_data *d)
+{
+        out_be32(mpic_percpu_base_vaddr + MPIC_EOI / 4, 0);
+}
+
+int ehv_pic_set_affinity(struct irq_data *d, const struct cpumask *dest,
+                         bool force)
+{
+        unsigned int src = virq_to_hw(d->irq);
+        unsigned int config, prio, cpu_dest;
+        int cpuid = irq_choose_cpu(dest);
+        unsigned long flags;
+
+        spin_lock_irqsave(&ehv_pic_lock, flags);
+        ev_int_get_config(src, &config, &prio, &cpu_dest);
+        ev_int_set_config(src, config, prio, cpuid);
+        spin_unlock_irqrestore(&ehv_pic_lock, flags);
+
+        return 0;
+}
+
+static unsigned int ehv_pic_type_to_vecpri(unsigned int type)
+{
+        /* Now convert sense value */
+
+        switch (type & IRQ_TYPE_SENSE_MASK) {
+        case IRQ_TYPE_EDGE_RISING:
+                return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
+                       EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
+
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_EDGE_BOTH:
+                return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
+                       EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
+
+        case IRQ_TYPE_LEVEL_HIGH:
+                return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
+                       EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
+
+        case IRQ_TYPE_LEVEL_LOW:
+        default:
+                return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
+                       EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
+        }
+}
+
+int ehv_pic_set_irq_type(struct irq_data *d, unsigned int flow_type)
+{
+        unsigned int src = virq_to_hw(d->irq);
+        struct irq_desc *desc = irq_to_desc(d->irq);
+        unsigned int vecpri, vold, vnew, prio, cpu_dest;
+        unsigned long flags;
+
+        if (flow_type == IRQ_TYPE_NONE)
+                flow_type = IRQ_TYPE_LEVEL_LOW;
+
+        irq_settings_clr_level(desc);
+        irq_settings_set_trigger_mask(desc, flow_type);
+        if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
+                irq_settings_set_level(desc);
+
+        vecpri = ehv_pic_type_to_vecpri(flow_type);
+
+        spin_lock_irqsave(&ehv_pic_lock, flags);
+        ev_int_get_config(src, &vold, &prio, &cpu_dest);
+        vnew = vold & ~(EHV_PIC_INFO(VECPRI_POLARITY_MASK) |
+                        EHV_PIC_INFO(VECPRI_SENSE_MASK));
+        vnew |= vecpri;
+
+        /*
+         * TODO : Add specific interface call for platform to set
+         * individual interrupt priorities.
+         * platform currently using static/default priority for all ints
+         */
+
+        prio = 8;
+
+        ev_int_set_config(src, vecpri, prio, cpu_dest);
+
+        spin_unlock_irqrestore(&ehv_pic_lock, flags);
+        return 0;
+}
+
+static struct irq_chip ehv_pic_irq_chip = {
+        .irq_mask       = ehv_pic_mask_irq,
+        .irq_unmask     = ehv_pic_unmask_irq,
+        .irq_eoi        = ehv_pic_end_irq,
+        .irq_set_type   = ehv_pic_set_irq_type,
+};
+
+static struct irq_chip ehv_pic_direct_eoi_irq_chip = {
+        .irq_mask       = ehv_pic_mask_irq,
+        .irq_unmask     = ehv_pic_unmask_irq,
+        .irq_eoi        = ehv_pic_direct_end_irq,
+        .irq_set_type   = ehv_pic_set_irq_type,
+};
+
+/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+unsigned int ehv_pic_get_irq(void)
+{
+        int irq;
+
+        BUG_ON(global_ehv_pic == NULL);
+
+        if (global_ehv_pic->coreint_flag)
+                irq = mfspr(SPRN_EPR); /* if core int mode */
+        else
+                ev_int_iack(0, &irq); /* legacy mode */
+
+        if (irq == 0xFFFF)    /* 0xFFFF --> no irq is pending */
+                return NO_IRQ;
+
+        /*
+         * this will also setup revmap[] in the slow path for the first
+         * time, next calls will always use fast path by indexing revmap
+         */
+        return irq_linear_revmap(global_ehv_pic->irqhost, irq);
+}
+
+static int ehv_pic_host_match(struct irq_host *h, struct device_node *node)
+{
+        /* Exact match, unless ehv_pic node is NULL */
+        return h->of_node == NULL || h->of_node == node;
+}
+
+static int ehv_pic_host_map(struct irq_host *h, unsigned int virq,
+                         irq_hw_number_t hw)
+{
+        struct ehv_pic *ehv_pic = h->host_data;
+        struct irq_chip *chip;
+
+        /* Default chip */
+        chip = &ehv_pic->hc_irq;
+
+        if (mpic_percpu_base_vaddr)
+                if (hwirq_intspec[hw] & IRQ_TYPE_MPIC_DIRECT)
+                        chip = &ehv_pic_direct_eoi_irq_chip;
+
+        irq_set_chip_data(virq, chip);
+        /*
+         * using handle_fasteoi_irq as our irq handler, this will
+         * only call the eoi callback and suitable for the MPIC
+         * controller which set ISR/IPR automatically and clear the
+         * highest priority active interrupt in ISR/IPR when we do
+         * a specific eoi
+         */
+        irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
+
+        /* Set default irq type */
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
+
+        return 0;
+}
+
+static int ehv_pic_host_xlate(struct irq_host *h, struct device_node *ct,
+                           const u32 *intspec, unsigned int intsize,
+                           irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+
+{
+        /*
+         * interrupt sense values coming from the guest device tree
+         * interrupt specifiers can have four possible sense and
+         * level encoding information and they need to
+         * be translated between firmware type & linux type.
+         */
+
+        static unsigned char map_of_senses_to_linux_irqtype[4] = {
+                IRQ_TYPE_EDGE_FALLING,
+                IRQ_TYPE_EDGE_RISING,
+                IRQ_TYPE_LEVEL_LOW,
+                IRQ_TYPE_LEVEL_HIGH,
+        };
+
+        *out_hwirq = intspec[0];
+        if (intsize > 1) {
+                hwirq_intspec[intspec[0]] = intspec[1];
+                *out_flags = map_of_senses_to_linux_irqtype[intspec[1] &
+                                                        ~IRQ_TYPE_MPIC_DIRECT];
+        } else {
+                *out_flags = IRQ_TYPE_NONE;
+        }
+
+        return 0;
+}
+
+static struct irq_host_ops ehv_pic_host_ops = {
+        .match = ehv_pic_host_match,
+        .map = ehv_pic_host_map,
+        .xlate = ehv_pic_host_xlate,
+};
+
+void __init ehv_pic_init(void)
+{
+        struct device_node *np, *np2;
+        struct ehv_pic *ehv_pic;
+        int coreint_flag = 1;
+
+        np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
+        if (!np) {
+                pr_err("ehv_pic_init: could not find epapr,hv-pic node\n");
+                return;
+        }
+
+        if (!of_find_property(np, "has-external-proxy", NULL))
+                coreint_flag = 0;
+
+        ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
+        if (!ehv_pic) {
+                of_node_put(np);
+                return;
+        }
+
+        ehv_pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
+                NR_EHV_PIC_INTS, &ehv_pic_host_ops, 0);
+
+        if (!ehv_pic->irqhost) {
+                of_node_put(np);
+                return;
+        }
+
+        np2 = of_find_compatible_node(NULL, NULL, "fsl,hv-mpic-per-cpu");
+        if (np2) {
+                mpic_percpu_base_vaddr = of_iomap(np2, 0);
+                if (!mpic_percpu_base_vaddr)
+                        pr_err("ehv_pic_init: of_iomap failed\n");
+
+                of_node_put(np2);
+        }
+
+        ehv_pic->irqhost->host_data = ehv_pic;
+        ehv_pic->hc_irq = ehv_pic_irq_chip;
+        ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
+        ehv_pic->coreint_flag = coreint_flag;
+
+        global_ehv_pic = ehv_pic;
+        irq_set_default_host(global_ehv_pic->irqhost);
+}
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index ba5cb3fa7074..3bba8bdb58b0 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -38,10 +38,17 @@ static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
 
 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
 {
+        u8 progif;
+
         /* if we aren't a PCIe don't bother */
         if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
                 return;
 
+        /* if we aren't in host mode don't bother */
+        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
+        if (progif & 0x1)
+                return;
+
         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
         fsl_pcie_bus_fixup = 1;
         return;
@@ -323,6 +330,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
         struct pci_controller *hose;
         struct resource rsrc;
         const int *bus_range;
+        u8 progif;
 
         if (!of_device_is_available(dev)) {
                 pr_warning("%s: disabled\n", dev->full_name);
@@ -353,6 +361,18 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 
         setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
                 PPC_INDIRECT_TYPE_BIG_ENDIAN);
+
+        early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
+        if ((progif & 1) == 1) {
+                /* unmap cfg_data & cfg_addr separately if not on same page */
+                if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
+                    ((unsigned long)hose->cfg_addr & PAGE_MASK))
+                        iounmap(hose->cfg_data);
+                iounmap(hose->cfg_addr);
+                pcibios_free_controller(hose);
+                return 0;
+        }
+
         setup_pci_cmd(hose);
 
         /* check PCI express link status */
@@ -380,70 +400,11 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 
         return 0;
 }
-
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header);
 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
 
-#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
-DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
 
+#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
 struct mpc83xx_pcie_priv {
         void __iomem *cfg_type0;
         void __iomem *cfg_type1;
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 19e5015e039b..265313e8396b 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -41,6 +41,7 @@
 #include <sysdev/fsl_soc.h>
 #include <mm/mmu_decl.h>
 #include <asm/cpm2.h>
+#include <asm/fsl_hcalls.h>     /* For the Freescale hypervisor */
 
 extern void init_fcc_ioports(struct fs_platform_info*);
 extern void init_fec_ioports(struct fs_platform_info*);
@@ -252,3 +253,29 @@ void fsl_rstcr_restart(char *cmd)
 struct platform_diu_data_ops diu_ops;
 EXPORT_SYMBOL(diu_ops);
 #endif
+
+/*
+ * Restart the current partition
+ *
+ * This function should be assigned to the ppc_md.restart function pointer,
+ * to initiate a partition restart when we're running under the Freescale
+ * hypervisor.
+ */
+void fsl_hv_restart(char *cmd)
+{
+        pr_info("hv restart\n");
+        fh_partition_restart(-1);
+}
+
+/*
+ * Halt the current partition
+ *
+ * This function should be assigned to the ppc_md.power_off and ppc_md.halt
+ * function pointers, to shut down the partition when we're running under
+ * the Freescale hypervisor.
+ */
+void fsl_hv_halt(void)
+{
+        pr_info("hv exit\n");
+        fh_partition_stop(-1);
+}
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 53609489a62b..2ece02beb8ff 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -36,5 +36,8 @@ struct platform_diu_data_ops {
 extern struct platform_diu_data_ops diu_ops;
 #endif
 
+void fsl_hv_restart(char *cmd);
+void fsl_hv_halt(void);
+
 #endif
 #endif
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 58d7a534f877..d5d3ff3d757e 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -598,42 +598,6 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
 
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 
-#ifdef CONFIG_SMP
-static int irq_choose_cpu(const struct cpumask *mask)
-{
-        int cpuid;
-
-        if (cpumask_equal(mask, cpu_all_mask)) {
-                static int irq_rover = 0;
-                static DEFINE_RAW_SPINLOCK(irq_rover_lock);
-                unsigned long flags;
-
-                /* Round-robin distribution... */
-        do_round_robin:
-                raw_spin_lock_irqsave(&irq_rover_lock, flags);
-
-                irq_rover = cpumask_next(irq_rover, cpu_online_mask);
-                if (irq_rover >= nr_cpu_ids)
-                        irq_rover = cpumask_first(cpu_online_mask);
-
-                cpuid = irq_rover;
-
-                raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
-        } else {
-                cpuid = cpumask_first_and(mask, cpu_online_mask);
-                if (cpuid >= nr_cpu_ids)
-                        goto do_round_robin;
-        }
-
-        return get_hard_smp_processor_id(cpuid);
-}
-#else
-static int irq_choose_cpu(const struct cpumask *mask)
-{
-        return hard_smp_processor_id();
-}
-#endif
-
 /* Find an mpic associated with a given linux interrupt */
 static struct mpic *mpic_find(unsigned int irq)
 {
@@ -849,7 +813,7 @@ static void mpic_unmask_tm(struct irq_data *d)
         struct mpic *mpic = mpic_from_irq_data(d);
         unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 
-        DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src);
+        DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
         mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
         mpic_tm_read(src);
 }
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index deda60a7f996..2ec4f3bb8160 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -650,12 +650,74 @@ struct ppc4xx_pciex_hwops
         int (*core_init)(struct device_node *np);
         int (*port_init_hw)(struct ppc4xx_pciex_port *port);
         int (*setup_utl)(struct ppc4xx_pciex_port *port);
+        void (*check_link)(struct ppc4xx_pciex_port *port);
 };
 
 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
 
 #ifdef CONFIG_44x
 
+static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
+                                           unsigned int sdr_offset,
+                                           unsigned int mask,
+                                           unsigned int value,
+                                           int timeout_ms)
+{
+        u32 val;
+
+        while(timeout_ms--) {
+                val = mfdcri(SDR0, port->sdr_base + sdr_offset);
+                if ((val & mask) == value) {
+                        pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
+                                 port->index, sdr_offset, timeout_ms, val);
+                        return 0;
+                }
+                msleep(1);
+        }
+        return -1;
+}
+
+static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
+{
+        /* Wait for reset to complete */
+        if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
+                printk(KERN_WARNING "PCIE%d: PGRST failed\n",
+                       port->index);
+                return -1;
+        }
+        return 0;
+}
+
+static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
+{
+        printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
+
+        /* Check for card presence detect if supported, if not, just wait for
+         * link unconditionally.
+         *
+         * note that we don't fail if there is no link, we just filter out
+         * config space accesses. That way, it will be easier to implement
+         * hotplug later on.
+         */
+        if (!port->has_ibpre ||
+            !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
+                                      1 << 28, 1 << 28, 100)) {
+                printk(KERN_INFO
+                       "PCIE%d: Device detected, waiting for link...\n",
+                       port->index);
+                if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
+                                             0x1000, 0x1000, 2000))
+                        printk(KERN_WARNING
+                               "PCIE%d: Link up failed\n", port->index);
+                else {
+                        printk(KERN_INFO
+                               "PCIE%d: link is up !\n", port->index);
+                        port->link = 1;
+                }
+        } else
+                printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
+}
+
 /* Check various reset bits of the 440SPe PCIe core */
 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
 {
@@ -806,7 +868,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
         dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
                         (1 << 24) | (1 << 16), 1 << 12);
 
-        return 0;
+        return ppc4xx_pciex_port_reset_sdr(port);
 }
 
 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
@@ -856,6 +918,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
         .core_init      = ppc440spe_pciex_core_init,
         .port_init_hw   = ppc440speA_pciex_init_port_hw,
         .setup_utl      = ppc440speA_pciex_init_utl,
+        .check_link     = ppc4xx_pciex_check_link_sdr,
 };
 
 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
@@ -863,6 +926,7 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
         .core_init      = ppc440spe_pciex_core_init,
         .port_init_hw   = ppc440speB_pciex_init_port_hw,
         .setup_utl      = ppc440speB_pciex_init_utl,
+        .check_link     = ppc4xx_pciex_check_link_sdr,
 };
 
 static int __init ppc460ex_pciex_core_init(struct device_node *np)
@@ -944,7 +1008,7 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 
         port->has_ibpre = 1;
 
-        return 0;
+        return ppc4xx_pciex_port_reset_sdr(port);
 }
 
 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -972,6 +1036,7 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
         .core_init      = ppc460ex_pciex_core_init,
         .port_init_hw   = ppc460ex_pciex_init_port_hw,
         .setup_utl      = ppc460ex_pciex_init_utl,
+        .check_link     = ppc4xx_pciex_check_link_sdr,
 };
 
 static int __init ppc460sx_pciex_core_init(struct device_node *np)
@@ -1075,7 +1140,7 @@ static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 
         port->has_ibpre = 1;
 
-        return 0;
+        return ppc4xx_pciex_port_reset_sdr(port);
 }
 
 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -1089,6 +1154,7 @@ static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
         .core_init      = ppc460sx_pciex_core_init,
         .port_init_hw   = ppc460sx_pciex_init_port_hw,
         .setup_utl      = ppc460sx_pciex_init_utl,
+        .check_link     = ppc4xx_pciex_check_link_sdr,
 };
 
 #endif /* CONFIG_44x */
@@ -1154,7 +1220,7 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 
         port->has_ibpre = 1;
 
-        return 0;
+        return ppc4xx_pciex_port_reset_sdr(port);
 }
 
 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -1183,11 +1249,11 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
         .core_init      = ppc405ex_pciex_core_init,
         .port_init_hw   = ppc405ex_pciex_init_port_hw,
         .setup_utl      = ppc405ex_pciex_init_utl,
+        .check_link     = ppc4xx_pciex_check_link_sdr,
 };
 
 #endif /* CONFIG_40x */
 
-
 /* Check that the core has been initied and if not, do it */
 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
 {
@@ -1261,26 +1327,6 @@ static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port
         dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
 }
 
-static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
-                                           unsigned int sdr_offset,
-                                           unsigned int mask,
-                                           unsigned int value,
-                                           int timeout_ms)
-{
-        u32 val;
-
-        while(timeout_ms--) {
-                val = mfdcri(SDR0, port->sdr_base + sdr_offset);
-                if ((val & mask) == value) {
-                        pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
-                                 port->index, sdr_offset, timeout_ms, val);
-                        return 0;
-                }
-                msleep(1);
-        }
-        return -1;
-}
-
 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
 {
         int rc = 0;
@@ -1291,40 +1337,8 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
         if (rc != 0)
                 return rc;
 
-        printk(KERN_INFO "PCIE%d: Checking link...\n",
-               port->index);
-
-        /* Wait for reset to complete */
-        if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
-                printk(KERN_WARNING "PCIE%d: PGRST failed\n",
-                       port->index);
-                return -1;
-        }
-
-        /* Check for card presence detect if supported, if not, just wait for
-         * link unconditionally.
-         *
-         * note that we don't fail if there is no link, we just filter out
-         * config space accesses. That way, it will be easier to implement
-         * hotplug later on.
-         */
-        if (!port->has_ibpre ||
-            !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
-                                      1 << 28, 1 << 28, 100)) {
-                printk(KERN_INFO
-                       "PCIE%d: Device detected, waiting for link...\n",
-                       port->index);
-                if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
-                                             0x1000, 0x1000, 2000))
-                        printk(KERN_WARNING
-                               "PCIE%d: Link up failed\n", port->index);
-                else {
-                        printk(KERN_INFO
-                               "PCIE%d: link is up !\n", port->index);
-                        port->link = 1;
-                }
-        } else
-                printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
+        if (ppc4xx_pciex_hwops->check_link)
+                ppc4xx_pciex_hwops->check_link(port);
 
         /*
          * Initialize mapping: disable all regions and configure
@@ -1347,14 +1361,17 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
         /*
          * Check for VC0 active and assert RDY.
          */
-        if (port->link &&
-            ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
-                                     1 << 16, 1 << 16, 5000)) {
-                printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
-                port->link = 0;
+        if (port->sdr_base) {
+                if (port->link &&
+                    ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
+                                             1 << 16, 1 << 16, 5000)) {
+                        printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
+                        port->link = 0;
+                }
+
+                dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
         }
 
-        dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
         msleep(100);
 
         return 0;