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authorJohn David Anglin <dave.anglin@bell.net>2014-05-11 18:40:50 -0400
committerHelge Deller <deller@gmx.de>2014-05-15 15:12:26 -0400
commitc776cd89fc705fc8b5c2e5ad906bf5d791620fed (patch)
treec6f26e9791042801f87cd36d87ebb0d527b344b1 /arch/parisc/kernel
parentfef47e2a2e1e75fe50a10f634a80f16808348cc6 (diff)
parisc: Improve LWS-CAS performance
The attached change significantly improves the performance of the LWS-CAS code in syscall.S. This allows a number of packages to build (e.g., zeromq3, gtest and libxs) that previously failed because slow LWS-CAS performance under contention. In particular, interrupts taken while the lock was taken degraded performance significantly. The change does the following: 1) Disables interrupts around the CAS operation, and 2) Changes the loads and stores to use the ordered completer, "o", on PA 2.0. "o" and "ma" with a zero offset are equivalent. The latter is accepted on both PA 1.X and 2.0. The use of ordered loads and stores probably makes no difference on all existing hardware, but it seemed pedantically correct. In particular, the CAS operation must complete before LDCW lock is released. As written before, a processor could reorder the operations. I don't believe the period interrupts are disabled is long enough to significantly increase interrupt latency. For example, the TLB insert code is longer. Worst case is a memory fault in the CAS operation. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: stable@vger.kernel.org # 3.13+ Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc/kernel')
-rw-r--r--arch/parisc/kernel/syscall.S12
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index a63bb179f79a..838786011037 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -589,10 +589,13 @@ cas_nocontend:
589# endif 589# endif
590/* ENABLE_LWS_DEBUG */ 590/* ENABLE_LWS_DEBUG */
591 591
592 rsm PSW_SM_I, %r0 /* Disable interrupts */
593 /* COW breaks can cause contention on UP systems */
592 LDCW 0(%sr2,%r20), %r28 /* Try to acquire the lock */ 594 LDCW 0(%sr2,%r20), %r28 /* Try to acquire the lock */
593 cmpb,<>,n %r0, %r28, cas_action /* Did we get it? */ 595 cmpb,<>,n %r0, %r28, cas_action /* Did we get it? */
594cas_wouldblock: 596cas_wouldblock:
595 ldo 2(%r0), %r28 /* 2nd case */ 597 ldo 2(%r0), %r28 /* 2nd case */
598 ssm PSW_SM_I, %r0
596 b lws_exit /* Contended... */ 599 b lws_exit /* Contended... */
597 ldo -EAGAIN(%r0), %r21 /* Spin in userspace */ 600 ldo -EAGAIN(%r0), %r21 /* Spin in userspace */
598 601
@@ -619,15 +622,17 @@ cas_action:
619 stw %r1, 4(%sr2,%r20) 622 stw %r1, 4(%sr2,%r20)
620#endif 623#endif
621 /* The load and store could fail */ 624 /* The load and store could fail */
6221: ldw 0(%sr3,%r26), %r28 6251: ldw,ma 0(%sr3,%r26), %r28
623 sub,<> %r28, %r25, %r0 626 sub,<> %r28, %r25, %r0
6242: stw %r24, 0(%sr3,%r26) 6272: stw,ma %r24, 0(%sr3,%r26)
625 /* Free lock */ 628 /* Free lock */
626 stw %r20, 0(%sr2,%r20) 629 stw,ma %r20, 0(%sr2,%r20)
627#if ENABLE_LWS_DEBUG 630#if ENABLE_LWS_DEBUG
628 /* Clear thread register indicator */ 631 /* Clear thread register indicator */
629 stw %r0, 4(%sr2,%r20) 632 stw %r0, 4(%sr2,%r20)
630#endif 633#endif
634 /* Enable interrupts */
635 ssm PSW_SM_I, %r0
631 /* Return to userspace, set no error */ 636 /* Return to userspace, set no error */
632 b lws_exit 637 b lws_exit
633 copy %r0, %r21 638 copy %r0, %r21
@@ -639,6 +644,7 @@ cas_action:
639#if ENABLE_LWS_DEBUG 644#if ENABLE_LWS_DEBUG
640 stw %r0, 4(%sr2,%r20) 645 stw %r0, 4(%sr2,%r20)
641#endif 646#endif
647 ssm PSW_SM_I, %r0
642 b lws_exit 648 b lws_exit
643 ldo -EFAULT(%r0),%r21 /* set errno */ 649 ldo -EFAULT(%r0),%r21 /* set errno */
644 nop 650 nop