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authorJohn David Anglin <dave.anglin@bell.net>2015-07-01 17:18:37 -0400
committerHelge Deller <deller@gmx.de>2015-07-10 15:47:47 -0400
commit01ab60570427caa24b9debc369e452e86cd9beb4 (patch)
tree473a38189494252e70a98a17bc342015ee0c681f /arch/parisc/kernel/entry.S
parentcb908ed3495496b9973a2b9ed1a60f43933fdf01 (diff)
parisc: Fix some PTE/TLB race conditions and optimize __flush_tlb_range based on timing results
The increased use of pdtlb/pitlb instructions seemed to increase the frequency of random segmentation faults building packages. Further, we had a number of cases where TLB inserts would repeatedly fail and all forward progress would stop. The Haskell ghc package caused a lot of trouble in this area. The final indication of a race in pte handling was this syslog entry on sibaris (C8000): swap_free: Unused swap offset entry 00000004 BUG: Bad page map in process mysqld pte:00000100 pmd:019bbec5 addr:00000000ec464000 vm_flags:00100073 anon_vma:0000000221023828 mapping: (null) index:ec464 CPU: 1 PID: 9176 Comm: mysqld Not tainted 4.0.0-2-parisc64-smp #1 Debian 4.0.5-1 Backtrace: [<0000000040173eb0>] show_stack+0x20/0x38 [<0000000040444424>] dump_stack+0x9c/0x110 [<00000000402a0d38>] print_bad_pte+0x1a8/0x278 [<00000000402a28b8>] unmap_single_vma+0x3d8/0x770 [<00000000402a4090>] zap_page_range+0xf0/0x198 [<00000000402ba2a4>] SyS_madvise+0x404/0x8c0 Note that the pte value is 0 except for the accessed bit 0x100. This bit shouldn't be set without the present bit. It should be noted that the madvise system call is probably a trigger for many of the random segmentation faults. In looking at the kernel code, I found the following problems: 1) The pte_clear define didn't take TLB lock when clearing a pte. 2) We didn't test pte present bit inside lock in exception support. 3) The pte and tlb locks needed to merged in order to ensure consistency between page table and TLB. This also has the effect of serializing TLB broadcasts on SMP systems. The attached change implements the above and a few other tweaks to try to improve performance. Based on the timing code, TLB purges are very slow (e.g., ~ 209 cycles per page on rp3440). Thus, I think it beneficial to test the split_tlb variable to avoid duplicate purges. Probably, all PA 2.0 machines have combined TLBs. I dropped using __flush_tlb_range in flush_tlb_mm as I realized all applications and most threads have a stack size that is too large to make this useful. I added some comments to this effect. Since implementing 1 through 3, I haven't had any random segmentation faults on mx3210 (rp3440) in about one week of building code and running as a Debian buildd. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: stable@vger.kernel.org # v3.18+ Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc/kernel/entry.S')
-rw-r--r--arch/parisc/kernel/entry.S163
1 files changed, 79 insertions, 84 deletions
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 75819617f93b..c5ef4081b01d 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -45,7 +45,7 @@
45 .level 2.0 45 .level 2.0
46#endif 46#endif
47 47
48 .import pa_dbit_lock,data 48 .import pa_tlb_lock,data
49 49
50 /* space_to_prot macro creates a prot id from a space id */ 50 /* space_to_prot macro creates a prot id from a space id */
51 51
@@ -420,8 +420,8 @@
420 SHLREG %r9,PxD_VALUE_SHIFT,\pmd 420 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
421 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index 421 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
422 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */ 422 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
423 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd 423 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
424 LDREG %r0(\pmd),\pte /* pmd is now pte */ 424 LDREG %r0(\pmd),\pte
425 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault 425 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
426 .endm 426 .endm
427 427
@@ -453,57 +453,53 @@
453 L2_ptep \pgd,\pte,\index,\va,\fault 453 L2_ptep \pgd,\pte,\index,\va,\fault
454 .endm 454 .endm
455 455
456 /* Acquire pa_dbit_lock lock. */ 456 /* Acquire pa_tlb_lock lock and recheck page is still present. */
457 .macro dbit_lock spc,tmp,tmp1 457 .macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
458#ifdef CONFIG_SMP 458#ifdef CONFIG_SMP
459 cmpib,COND(=),n 0,\spc,2f 459 cmpib,COND(=),n 0,\spc,2f
460 load32 PA(pa_dbit_lock),\tmp 460 load32 PA(pa_tlb_lock),\tmp
4611: LDCW 0(\tmp),\tmp1 4611: LDCW 0(\tmp),\tmp1
462 cmpib,COND(=) 0,\tmp1,1b 462 cmpib,COND(=) 0,\tmp1,1b
463 nop 463 nop
464 LDREG 0(\ptp),\pte
465 bb,<,n \pte,_PAGE_PRESENT_BIT,2f
466 b \fault
467 stw \spc,0(\tmp)
4642: 4682:
465#endif 469#endif
466 .endm 470 .endm
467 471
468 /* Release pa_dbit_lock lock without reloading lock address. */ 472 /* Release pa_tlb_lock lock without reloading lock address. */
469 .macro dbit_unlock0 spc,tmp 473 .macro tlb_unlock0 spc,tmp
470#ifdef CONFIG_SMP 474#ifdef CONFIG_SMP
471 or,COND(=) %r0,\spc,%r0 475 or,COND(=) %r0,\spc,%r0
472 stw \spc,0(\tmp) 476 stw \spc,0(\tmp)
473#endif 477#endif
474 .endm 478 .endm
475 479
476 /* Release pa_dbit_lock lock. */ 480 /* Release pa_tlb_lock lock. */
477 .macro dbit_unlock1 spc,tmp 481 .macro tlb_unlock1 spc,tmp
478#ifdef CONFIG_SMP 482#ifdef CONFIG_SMP
479 load32 PA(pa_dbit_lock),\tmp 483 load32 PA(pa_tlb_lock),\tmp
480 dbit_unlock0 \spc,\tmp 484 tlb_unlock0 \spc,\tmp
481#endif 485#endif
482 .endm 486 .endm
483 487
484 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and 488 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
485 * don't needlessly dirty the cache line if it was already set */ 489 * don't needlessly dirty the cache line if it was already set */
486 .macro update_ptep spc,ptep,pte,tmp,tmp1 490 .macro update_accessed ptp,pte,tmp,tmp1
487#ifdef CONFIG_SMP
488 or,COND(=) %r0,\spc,%r0
489 LDREG 0(\ptep),\pte
490#endif
491 ldi _PAGE_ACCESSED,\tmp1 491 ldi _PAGE_ACCESSED,\tmp1
492 or \tmp1,\pte,\tmp 492 or \tmp1,\pte,\tmp
493 and,COND(<>) \tmp1,\pte,%r0 493 and,COND(<>) \tmp1,\pte,%r0
494 STREG \tmp,0(\ptep) 494 STREG \tmp,0(\ptp)
495 .endm 495 .endm
496 496
497 /* Set the dirty bit (and accessed bit). No need to be 497 /* Set the dirty bit (and accessed bit). No need to be
498 * clever, this is only used from the dirty fault */ 498 * clever, this is only used from the dirty fault */
499 .macro update_dirty spc,ptep,pte,tmp 499 .macro update_dirty ptp,pte,tmp
500#ifdef CONFIG_SMP
501 or,COND(=) %r0,\spc,%r0
502 LDREG 0(\ptep),\pte
503#endif
504 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp 500 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
505 or \tmp,\pte,\pte 501 or \tmp,\pte,\pte
506 STREG \pte,0(\ptep) 502 STREG \pte,0(\ptp)
507 .endm 503 .endm
508 504
509 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE) 505 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
@@ -1148,14 +1144,14 @@ dtlb_miss_20w:
1148 1144
1149 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w 1145 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1150 1146
1151 dbit_lock spc,t0,t1 1147 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20w
1152 update_ptep spc,ptp,pte,t0,t1 1148 update_accessed ptp,pte,t0,t1
1153 1149
1154 make_insert_tlb spc,pte,prot 1150 make_insert_tlb spc,pte,prot
1155 1151
1156 idtlbt pte,prot 1152 idtlbt pte,prot
1157 dbit_unlock1 spc,t0
1158 1153
1154 tlb_unlock1 spc,t0
1159 rfir 1155 rfir
1160 nop 1156 nop
1161 1157
@@ -1174,14 +1170,14 @@ nadtlb_miss_20w:
1174 1170
1175 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w 1171 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1176 1172
1177 dbit_lock spc,t0,t1 1173 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20w
1178 update_ptep spc,ptp,pte,t0,t1 1174 update_accessed ptp,pte,t0,t1
1179 1175
1180 make_insert_tlb spc,pte,prot 1176 make_insert_tlb spc,pte,prot
1181 1177
1182 idtlbt pte,prot 1178 idtlbt pte,prot
1183 dbit_unlock1 spc,t0
1184 1179
1180 tlb_unlock1 spc,t0
1185 rfir 1181 rfir
1186 nop 1182 nop
1187 1183
@@ -1202,20 +1198,20 @@ dtlb_miss_11:
1202 1198
1203 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11 1199 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1204 1200
1205 dbit_lock spc,t0,t1 1201 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_11
1206 update_ptep spc,ptp,pte,t0,t1 1202 update_accessed ptp,pte,t0,t1
1207 1203
1208 make_insert_tlb_11 spc,pte,prot 1204 make_insert_tlb_11 spc,pte,prot
1209 1205
1210 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ 1206 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1211 mtsp spc,%sr1 1207 mtsp spc,%sr1
1212 1208
1213 idtlba pte,(%sr1,va) 1209 idtlba pte,(%sr1,va)
1214 idtlbp prot,(%sr1,va) 1210 idtlbp prot,(%sr1,va)
1215 1211
1216 mtsp t0, %sr1 /* Restore sr1 */ 1212 mtsp t1, %sr1 /* Restore sr1 */
1217 dbit_unlock1 spc,t0
1218 1213
1214 tlb_unlock1 spc,t0
1219 rfir 1215 rfir
1220 nop 1216 nop
1221 1217
@@ -1235,21 +1231,20 @@ nadtlb_miss_11:
1235 1231
1236 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11 1232 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1237 1233
1238 dbit_lock spc,t0,t1 1234 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_11
1239 update_ptep spc,ptp,pte,t0,t1 1235 update_accessed ptp,pte,t0,t1
1240 1236
1241 make_insert_tlb_11 spc,pte,prot 1237 make_insert_tlb_11 spc,pte,prot
1242 1238
1243 1239 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1244 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1245 mtsp spc,%sr1 1240 mtsp spc,%sr1
1246 1241
1247 idtlba pte,(%sr1,va) 1242 idtlba pte,(%sr1,va)
1248 idtlbp prot,(%sr1,va) 1243 idtlbp prot,(%sr1,va)
1249 1244
1250 mtsp t0, %sr1 /* Restore sr1 */ 1245 mtsp t1, %sr1 /* Restore sr1 */
1251 dbit_unlock1 spc,t0
1252 1246
1247 tlb_unlock1 spc,t0
1253 rfir 1248 rfir
1254 nop 1249 nop
1255 1250
@@ -1269,16 +1264,16 @@ dtlb_miss_20:
1269 1264
1270 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20 1265 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1271 1266
1272 dbit_lock spc,t0,t1 1267 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20
1273 update_ptep spc,ptp,pte,t0,t1 1268 update_accessed ptp,pte,t0,t1
1274 1269
1275 make_insert_tlb spc,pte,prot 1270 make_insert_tlb spc,pte,prot
1276 1271
1277 f_extend pte,t0 1272 f_extend pte,t1
1278 1273
1279 idtlbt pte,prot 1274 idtlbt pte,prot
1280 dbit_unlock1 spc,t0
1281 1275
1276 tlb_unlock1 spc,t0
1282 rfir 1277 rfir
1283 nop 1278 nop
1284 1279
@@ -1297,16 +1292,16 @@ nadtlb_miss_20:
1297 1292
1298 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20 1293 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1299 1294
1300 dbit_lock spc,t0,t1 1295 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20
1301 update_ptep spc,ptp,pte,t0,t1 1296 update_accessed ptp,pte,t0,t1
1302 1297
1303 make_insert_tlb spc,pte,prot 1298 make_insert_tlb spc,pte,prot
1304 1299
1305 f_extend pte,t0 1300 f_extend pte,t1
1306 1301
1307 idtlbt pte,prot 1302 idtlbt pte,prot
1308 dbit_unlock1 spc,t0
1309 1303
1304 tlb_unlock1 spc,t0
1310 rfir 1305 rfir
1311 nop 1306 nop
1312 1307
@@ -1406,14 +1401,14 @@ itlb_miss_20w:
1406 1401
1407 L3_ptep ptp,pte,t0,va,itlb_fault 1402 L3_ptep ptp,pte,t0,va,itlb_fault
1408 1403
1409 dbit_lock spc,t0,t1 1404 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1410 update_ptep spc,ptp,pte,t0,t1 1405 update_accessed ptp,pte,t0,t1
1411 1406
1412 make_insert_tlb spc,pte,prot 1407 make_insert_tlb spc,pte,prot
1413 1408
1414 iitlbt pte,prot 1409 iitlbt pte,prot
1415 dbit_unlock1 spc,t0
1416 1410
1411 tlb_unlock1 spc,t0
1417 rfir 1412 rfir
1418 nop 1413 nop
1419 1414
@@ -1430,14 +1425,14 @@ naitlb_miss_20w:
1430 1425
1431 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w 1426 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1432 1427
1433 dbit_lock spc,t0,t1 1428 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20w
1434 update_ptep spc,ptp,pte,t0,t1 1429 update_accessed ptp,pte,t0,t1
1435 1430
1436 make_insert_tlb spc,pte,prot 1431 make_insert_tlb spc,pte,prot
1437 1432
1438 iitlbt pte,prot 1433 iitlbt pte,prot
1439 dbit_unlock1 spc,t0
1440 1434
1435 tlb_unlock1 spc,t0
1441 rfir 1436 rfir
1442 nop 1437 nop
1443 1438
@@ -1458,20 +1453,20 @@ itlb_miss_11:
1458 1453
1459 L2_ptep ptp,pte,t0,va,itlb_fault 1454 L2_ptep ptp,pte,t0,va,itlb_fault
1460 1455
1461 dbit_lock spc,t0,t1 1456 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1462 update_ptep spc,ptp,pte,t0,t1 1457 update_accessed ptp,pte,t0,t1
1463 1458
1464 make_insert_tlb_11 spc,pte,prot 1459 make_insert_tlb_11 spc,pte,prot
1465 1460
1466 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ 1461 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1467 mtsp spc,%sr1 1462 mtsp spc,%sr1
1468 1463
1469 iitlba pte,(%sr1,va) 1464 iitlba pte,(%sr1,va)
1470 iitlbp prot,(%sr1,va) 1465 iitlbp prot,(%sr1,va)
1471 1466
1472 mtsp t0, %sr1 /* Restore sr1 */ 1467 mtsp t1, %sr1 /* Restore sr1 */
1473 dbit_unlock1 spc,t0
1474 1468
1469 tlb_unlock1 spc,t0
1475 rfir 1470 rfir
1476 nop 1471 nop
1477 1472
@@ -1482,20 +1477,20 @@ naitlb_miss_11:
1482 1477
1483 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11 1478 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1484 1479
1485 dbit_lock spc,t0,t1 1480 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_11
1486 update_ptep spc,ptp,pte,t0,t1 1481 update_accessed ptp,pte,t0,t1
1487 1482
1488 make_insert_tlb_11 spc,pte,prot 1483 make_insert_tlb_11 spc,pte,prot
1489 1484
1490 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */ 1485 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1491 mtsp spc,%sr1 1486 mtsp spc,%sr1
1492 1487
1493 iitlba pte,(%sr1,va) 1488 iitlba pte,(%sr1,va)
1494 iitlbp prot,(%sr1,va) 1489 iitlbp prot,(%sr1,va)
1495 1490
1496 mtsp t0, %sr1 /* Restore sr1 */ 1491 mtsp t1, %sr1 /* Restore sr1 */
1497 dbit_unlock1 spc,t0
1498 1492
1493 tlb_unlock1 spc,t0
1499 rfir 1494 rfir
1500 nop 1495 nop
1501 1496
@@ -1516,16 +1511,16 @@ itlb_miss_20:
1516 1511
1517 L2_ptep ptp,pte,t0,va,itlb_fault 1512 L2_ptep ptp,pte,t0,va,itlb_fault
1518 1513
1519 dbit_lock spc,t0,t1 1514 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1520 update_ptep spc,ptp,pte,t0,t1 1515 update_accessed ptp,pte,t0,t1
1521 1516
1522 make_insert_tlb spc,pte,prot 1517 make_insert_tlb spc,pte,prot
1523 1518
1524 f_extend pte,t0 1519 f_extend pte,t1
1525 1520
1526 iitlbt pte,prot 1521 iitlbt pte,prot
1527 dbit_unlock1 spc,t0
1528 1522
1523 tlb_unlock1 spc,t0
1529 rfir 1524 rfir
1530 nop 1525 nop
1531 1526
@@ -1536,16 +1531,16 @@ naitlb_miss_20:
1536 1531
1537 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20 1532 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1538 1533
1539 dbit_lock spc,t0,t1 1534 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20
1540 update_ptep spc,ptp,pte,t0,t1 1535 update_accessed ptp,pte,t0,t1
1541 1536
1542 make_insert_tlb spc,pte,prot 1537 make_insert_tlb spc,pte,prot
1543 1538
1544 f_extend pte,t0 1539 f_extend pte,t1
1545 1540
1546 iitlbt pte,prot 1541 iitlbt pte,prot
1547 dbit_unlock1 spc,t0
1548 1542
1543 tlb_unlock1 spc,t0
1549 rfir 1544 rfir
1550 nop 1545 nop
1551 1546
@@ -1568,14 +1563,14 @@ dbit_trap_20w:
1568 1563
1569 L3_ptep ptp,pte,t0,va,dbit_fault 1564 L3_ptep ptp,pte,t0,va,dbit_fault
1570 1565
1571 dbit_lock spc,t0,t1 1566 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1572 update_dirty spc,ptp,pte,t1 1567 update_dirty ptp,pte,t1
1573 1568
1574 make_insert_tlb spc,pte,prot 1569 make_insert_tlb spc,pte,prot
1575 1570
1576 idtlbt pte,prot 1571 idtlbt pte,prot
1577 dbit_unlock0 spc,t0
1578 1572
1573 tlb_unlock0 spc,t0
1579 rfir 1574 rfir
1580 nop 1575 nop
1581#else 1576#else
@@ -1588,8 +1583,8 @@ dbit_trap_11:
1588 1583
1589 L2_ptep ptp,pte,t0,va,dbit_fault 1584 L2_ptep ptp,pte,t0,va,dbit_fault
1590 1585
1591 dbit_lock spc,t0,t1 1586 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1592 update_dirty spc,ptp,pte,t1 1587 update_dirty ptp,pte,t1
1593 1588
1594 make_insert_tlb_11 spc,pte,prot 1589 make_insert_tlb_11 spc,pte,prot
1595 1590
@@ -1600,8 +1595,8 @@ dbit_trap_11:
1600 idtlbp prot,(%sr1,va) 1595 idtlbp prot,(%sr1,va)
1601 1596
1602 mtsp t1, %sr1 /* Restore sr1 */ 1597 mtsp t1, %sr1 /* Restore sr1 */
1603 dbit_unlock0 spc,t0
1604 1598
1599 tlb_unlock0 spc,t0
1605 rfir 1600 rfir
1606 nop 1601 nop
1607 1602
@@ -1612,16 +1607,16 @@ dbit_trap_20:
1612 1607
1613 L2_ptep ptp,pte,t0,va,dbit_fault 1608 L2_ptep ptp,pte,t0,va,dbit_fault
1614 1609
1615 dbit_lock spc,t0,t1 1610 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1616 update_dirty spc,ptp,pte,t1 1611 update_dirty ptp,pte,t1
1617 1612
1618 make_insert_tlb spc,pte,prot 1613 make_insert_tlb spc,pte,prot
1619 1614
1620 f_extend pte,t1 1615 f_extend pte,t1
1621 1616
1622 idtlbt pte,prot 1617 idtlbt pte,prot
1623 dbit_unlock0 spc,t0
1624 1618
1619 tlb_unlock0 spc,t0
1625 rfir 1620 rfir
1626 nop 1621 nop
1627#endif 1622#endif