aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2013-09-26 12:16:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-10-29 16:25:17 -0400
commita6e95a86e02e4a60b4355c84d19dba2baf3d87ba (patch)
tree49cf0fb42b16d15ffb9d3944e3319f3403dccf9a /arch/mips
parent1d7bf993e0731b4ac790667c196b2a2d787f95c3 (diff)
MIPS: PowerTV: Remove support code.
Nobody seems to care about this platform anymore and my attempts to find somebody willing to provide some tlc for PowerTV have failed so far. So let's nuke the bloody thing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5910/
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig21
-rw-r--r--arch/mips/configs/powertv_defconfig136
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h120
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_reg_map.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h125
-rw-r--r--arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h60
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h107
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h253
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h167
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h27
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/csrc-powertv.c151
-rw-r--r--arch/mips/powertv/Kconfig12
-rw-r--r--arch/mips/powertv/Makefile29
-rw-r--r--arch/mips/powertv/Platform7
-rw-r--r--arch/mips/powertv/asic/Makefile21
-rw-r--r--arch/mips/powertv/asic/asic-calliope.c101
-rw-r--r--arch/mips/powertv/asic/asic-cronus.c101
-rw-r--r--arch/mips/powertv/asic/asic-gaia.c96
-rw-r--r--arch/mips/powertv/asic/asic-zeus.c101
-rw-r--r--arch/mips/powertv/asic/asic_devices.c549
-rw-r--r--arch/mips/powertv/asic/asic_int.c125
-rw-r--r--arch/mips/powertv/asic/irq_asic.c115
-rw-r--r--arch/mips/powertv/asic/prealloc-calliope.c385
-rw-r--r--arch/mips/powertv/asic/prealloc-cronus.c340
-rw-r--r--arch/mips/powertv/asic/prealloc-cronuslite.c174
-rw-r--r--arch/mips/powertv/asic/prealloc-gaia.c589
-rw-r--r--arch/mips/powertv/asic/prealloc-zeus.c304
-rw-r--r--arch/mips/powertv/asic/prealloc.h70
-rw-r--r--arch/mips/powertv/init.c90
-rw-r--r--arch/mips/powertv/init.h28
-rw-r--r--arch/mips/powertv/ioremap.c136
-rw-r--r--arch/mips/powertv/memory.c353
-rw-r--r--arch/mips/powertv/pci/Makefile19
-rw-r--r--arch/mips/powertv/pci/fixup-powertv.c37
-rw-r--r--arch/mips/powertv/pci/powertv-pci.h31
-rw-r--r--arch/mips/powertv/powertv-clock.h26
-rw-r--r--arch/mips/powertv/powertv-usb.c404
-rw-r--r--arch/mips/powertv/powertv_setup.c319
-rw-r--r--arch/mips/powertv/reset.c35
-rw-r--r--arch/mips/powertv/reset.h26
-rw-r--r--arch/mips/powertv/time.c36
45 files changed, 0 insertions, 5972 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index d9d81c219253..6e239123d6fe 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -20,7 +20,6 @@ platforms += mti-sead3
20platforms += netlogic 20platforms += netlogic
21platforms += pmcs-msp71xx 21platforms += pmcs-msp71xx
22platforms += pnx833x 22platforms += pnx833x
23platforms += powertv
24platforms += ralink 23platforms += ralink
25platforms += rb532 24platforms += rb532
26platforms += sgi-ip22 25platforms += sgi-ip22
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d2440478787b..17cc7ff8458c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -415,23 +415,6 @@ config PMC_MSP
415 of integrated peripherals, interfaces and DSPs in addition to 415 of integrated peripherals, interfaces and DSPs in addition to
416 a variety of MIPS cores. 416 a variety of MIPS cores.
417 417
418config POWERTV
419 bool "Cisco PowerTV"
420 select BOOT_ELF32
421 select CEVT_R4K
422 select CPU_MIPSR2_IRQ_VI
423 select CPU_MIPSR2_IRQ_EI
424 select CSRC_POWERTV
425 select DMA_NONCOHERENT
426 select HW_HAS_PCI
427 select SYS_HAS_CPU_MIPS32_R2
428 select SYS_SUPPORTS_32BIT_KERNEL
429 select SYS_SUPPORTS_BIG_ENDIAN
430 select SYS_SUPPORTS_HIGHMEM
431 select USB_OHCI_LITTLE_ENDIAN
432 help
433 This enables support for the Cisco PowerTV Platform.
434
435config RALINK 418config RALINK
436 bool "Ralink based machines" 419 bool "Ralink based machines"
437 select CEVT_R4K 420 select CEVT_R4K
@@ -814,7 +797,6 @@ source "arch/mips/jz4740/Kconfig"
814source "arch/mips/lantiq/Kconfig" 797source "arch/mips/lantiq/Kconfig"
815source "arch/mips/lasat/Kconfig" 798source "arch/mips/lasat/Kconfig"
816source "arch/mips/pmcs-msp71xx/Kconfig" 799source "arch/mips/pmcs-msp71xx/Kconfig"
817source "arch/mips/powertv/Kconfig"
818source "arch/mips/ralink/Kconfig" 800source "arch/mips/ralink/Kconfig"
819source "arch/mips/sgi-ip27/Kconfig" 801source "arch/mips/sgi-ip27/Kconfig"
820source "arch/mips/sibyte/Kconfig" 802source "arch/mips/sibyte/Kconfig"
@@ -893,9 +875,6 @@ config CSRC_BCM1480
893config CSRC_IOASIC 875config CSRC_IOASIC
894 bool 876 bool
895 877
896config CSRC_POWERTV
897 bool
898
899config CSRC_R4K 878config CSRC_R4K
900 bool 879 bool
901 880
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
deleted file mode 100644
index 7fda0ce5f692..000000000000
--- a/arch/mips/configs/powertv_defconfig
+++ /dev/null
@@ -1,136 +0,0 @@
1CONFIG_POWERTV=y
2CONFIG_BOOTLOADER_FAMILY="R2"
3CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y
5CONFIG_HZ_1000=y
6CONFIG_PREEMPT=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9CONFIG_CROSS_COMPILE=""
10# CONFIG_SWAP is not set
11CONFIG_SYSVIPC=y
12CONFIG_LOG_BUF_SHIFT=16
13CONFIG_RELAY=y
14CONFIG_BLK_DEV_INITRD=y
15# CONFIG_RD_GZIP is not set
16# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
17CONFIG_EXPERT=y
18# CONFIG_SYSCTL_SYSCALL is not set
19CONFIG_KALLSYMS_ALL=y
20# CONFIG_PCSPKR_PLATFORM is not set
21# CONFIG_EPOLL is not set
22# CONFIG_SIGNALFD is not set
23# CONFIG_EVENTFD is not set
24# CONFIG_VM_EVENT_COUNTERS is not set
25# CONFIG_SLUB_DEBUG is not set
26CONFIG_MODULES=y
27CONFIG_MODULE_UNLOAD=y
28CONFIG_MODVERSIONS=y
29CONFIG_MODULE_SRCVERSION_ALL=y
30# CONFIG_BLK_DEV_BSG is not set
31# CONFIG_IOSCHED_DEADLINE is not set
32# CONFIG_IOSCHED_CFQ is not set
33CONFIG_PCI=y
34CONFIG_NET=y
35CONFIG_PACKET=y
36CONFIG_UNIX=y
37CONFIG_INET=y
38CONFIG_IP_MULTICAST=y
39CONFIG_IP_ADVANCED_ROUTER=y
40CONFIG_IP_PNP=y
41CONFIG_SYN_COOKIES=y
42# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET_XFRM_MODE_BEET is not set
45# CONFIG_INET_LRO is not set
46# CONFIG_INET_DIAG is not set
47CONFIG_IPV6=y
48CONFIG_IPV6_PRIVACY=y
49CONFIG_INET6_AH=y
50CONFIG_INET6_ESP=y
51CONFIG_INET6_IPCOMP=y
52# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
53# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
54# CONFIG_INET6_XFRM_MODE_BEET is not set
55# CONFIG_IPV6_SIT is not set
56CONFIG_IPV6_TUNNEL=y
57CONFIG_NETFILTER=y
58# CONFIG_BRIDGE_NETFILTER is not set
59CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
60CONFIG_IP_NF_IPTABLES=y
61CONFIG_IP_NF_FILTER=y
62CONFIG_IP_NF_ARPTABLES=y
63CONFIG_IP_NF_ARPFILTER=y
64CONFIG_IP6_NF_IPTABLES=y
65CONFIG_IP6_NF_FILTER=y
66CONFIG_BRIDGE=y
67CONFIG_NET_SCHED=y
68CONFIG_NET_SCH_TBF=y
69CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
70CONFIG_MTD=y
71CONFIG_MTD_PARTITIONS=y
72CONFIG_MTD_CMDLINE_PARTS=y
73CONFIG_MTD_CHAR=y
74CONFIG_MTD_BLOCK=y
75CONFIG_MTD_NAND=y
76CONFIG_BLK_DEV_LOOP=y
77CONFIG_BLK_DEV_RAM=y
78CONFIG_BLK_DEV_RAM_SIZE=32768
79# CONFIG_MISC_DEVICES is not set
80# CONFIG_SCSI_PROC_FS is not set
81CONFIG_BLK_DEV_SD=y
82# CONFIG_SCSI_LOWLEVEL is not set
83CONFIG_ATA=y
84CONFIG_NETDEVICES=y
85CONFIG_NET_ETHERNET=y
86# CONFIG_WLAN is not set
87CONFIG_USB_RTL8150=y
88# CONFIG_INPUT_MOUSEDEV is not set
89CONFIG_INPUT_EVDEV=y
90# CONFIG_INPUT_KEYBOARD is not set
91# CONFIG_INPUT_MOUSE is not set
92# CONFIG_SERIO is not set
93# CONFIG_VT is not set
94# CONFIG_DEVKMEM is not set
95# CONFIG_LEGACY_PTYS is not set
96# CONFIG_HW_RANDOM is not set
97# CONFIG_HWMON is not set
98# CONFIG_MFD_SUPPORT is not set
99# CONFIG_VGA_ARB is not set
100CONFIG_USB_HIDDEV=y
101CONFIG_USB=y
102CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
103CONFIG_USB_DEVICEFS=y
104# CONFIG_USB_DEVICE_CLASS is not set
105CONFIG_USB_EHCI_HCD=y
106# CONFIG_USB_EHCI_TT_NEWSCHED is not set
107CONFIG_USB_OHCI_HCD=y
108CONFIG_USB_STORAGE=y
109CONFIG_USB_SERIAL=y
110CONFIG_USB_SERIAL_CONSOLE=y
111CONFIG_USB_SERIAL_CP210X=y
112CONFIG_EXT2_FS=y
113CONFIG_EXT3_FS=y
114# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
115# CONFIG_EXT3_FS_XATTR is not set
116# CONFIG_DNOTIFY is not set
117CONFIG_FUSE_FS=y
118CONFIG_PROC_KCORE=y
119CONFIG_TMPFS=y
120CONFIG_JFFS2_FS=y
121CONFIG_CRAMFS=y
122CONFIG_NFS_FS=y
123CONFIG_NFS_V3=y
124CONFIG_ROOT_NFS=y
125CONFIG_PRINTK_TIME=y
126CONFIG_DEBUG_FS=y
127CONFIG_DEBUG_KERNEL=y
128CONFIG_DETECT_HUNG_TASK=y
129# CONFIG_SCHED_DEBUG is not set
130# CONFIG_DEBUG_PREEMPT is not set
131CONFIG_DEBUG_INFO=y
132# CONFIG_RCU_CPU_STALL_DETECTOR is not set
133# CONFIG_EARLY_PRINTK is not set
134CONFIG_CMDLINE_BOOL=y
135# CONFIG_CRYPTO_ANSI_CPRNG is not set
136# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
deleted file mode 100644
index b341108d12f1..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <asm/mach-powertv/asic_regs.h>
25
26#define DVR_CAPABLE (1<<0)
27#define PCIE_CAPABLE (1<<1)
28#define FFS_CAPABLE (1<<2)
29#define DISPLAY_CAPABLE (1<<3)
30
31/* Platform Family types
32 * For compitability, the new value must be added in the end */
33enum family_type {
34 FAMILY_8500,
35 FAMILY_8500RNG,
36 FAMILY_4500,
37 FAMILY_1500,
38 FAMILY_8600,
39 FAMILY_4600,
40 FAMILY_4600VZA,
41 FAMILY_8600VZB,
42 FAMILY_1500VZE,
43 FAMILY_1500VZF,
44 FAMILY_8700,
45 FAMILIES
46};
47
48/* Register maps for each ASIC */
49extern const struct register_map calliope_register_map;
50extern const struct register_map cronus_register_map;
51extern const struct register_map gaia_register_map;
52extern const struct register_map zeus_register_map;
53
54extern struct resource dvr_cronus_resources[];
55extern struct resource dvr_gaia_resources[];
56extern struct resource dvr_zeus_resources[];
57extern struct resource non_dvr_calliope_resources[];
58extern struct resource non_dvr_cronus_resources[];
59extern struct resource non_dvr_cronuslite_resources[];
60extern struct resource non_dvr_gaia_resources[];
61extern struct resource non_dvr_vz_calliope_resources[];
62extern struct resource non_dvr_vze_calliope_resources[];
63extern struct resource non_dvr_vzf_calliope_resources[];
64extern struct resource non_dvr_zeus_resources[];
65
66extern void powertv_platform_init(void);
67extern void platform_alloc_bootmem(void);
68extern enum asic_type platform_get_asic(void);
69extern enum family_type platform_get_family(void);
70extern int platform_supports_dvr(void);
71extern int platform_supports_ffs(void);
72extern int platform_supports_pcie(void);
73extern int platform_supports_display(void);
74extern void configure_platform(void);
75
76/* Platform Resources */
77#define ASIC_RESOURCE_GET_EXISTS 1
78extern struct resource *asic_resource_get(const char *name);
79extern void platform_release_memory(void *baddr, int size);
80
81/* USB configuration */
82struct usb_hcd; /* Forward reference */
83extern void platform_configure_usb_ehci(void);
84extern void platform_unconfigure_usb_ehci(void);
85extern void platform_configure_usb_ohci(void);
86extern void platform_unconfigure_usb_ohci(void);
87
88/* Resource for ASIC registers */
89extern struct resource asic_resource;
90extern int platform_usb_devices_init(struct platform_device **echi_dev,
91 struct platform_device **ohci_dev);
92
93/* Reboot Cause */
94extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
95extern void set_locked_reboot_cause(char code, unsigned int data,
96 unsigned int data2);
97
98enum sys_reboot_type {
99 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
100 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
101 * mode */
102 sys_user_reboot = 0x02, /* Reboot initiated by user */
103 sys_system_reboot = 0x03, /* Reboot initiated by OS */
104 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
105 sys_silent_reboot = 0x05, /* Silent reboot */
106 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
107 sys_power_up_reboot = 0x07, /* Power on bootup. Older
108 * drivers may report as
109 * userReboot. */
110 sys_code_change = 0x08, /* Reboot to take code change.
111 * Older drivers may report as
112 * userReboot. */
113 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
114 * reset button reset. Older
115 * drivers may report as
116 * userReboot. */
117 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
118};
119
120#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
deleted file mode 100644
index 20348e817b09..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * asic_reg_map.h
3 *
4 * A macro-enclosed list of the elements for the register_map structure for
5 * use in defining and manipulating the structure.
6 *
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
25REGISTER_MAP_ELEMENT(eic_cfg_bits)
26REGISTER_MAP_ELEMENT(eic_ready_status)
27REGISTER_MAP_ELEMENT(chipver3)
28REGISTER_MAP_ELEMENT(chipver2)
29REGISTER_MAP_ELEMENT(chipver1)
30REGISTER_MAP_ELEMENT(chipver0)
31REGISTER_MAP_ELEMENT(uart1_intstat)
32REGISTER_MAP_ELEMENT(uart1_inten)
33REGISTER_MAP_ELEMENT(uart1_config1)
34REGISTER_MAP_ELEMENT(uart1_config2)
35REGISTER_MAP_ELEMENT(uart1_divisorhi)
36REGISTER_MAP_ELEMENT(uart1_divisorlo)
37REGISTER_MAP_ELEMENT(uart1_data)
38REGISTER_MAP_ELEMENT(uart1_status)
39REGISTER_MAP_ELEMENT(int_stat_3)
40REGISTER_MAP_ELEMENT(int_stat_2)
41REGISTER_MAP_ELEMENT(int_stat_1)
42REGISTER_MAP_ELEMENT(int_stat_0)
43REGISTER_MAP_ELEMENT(int_config)
44REGISTER_MAP_ELEMENT(int_int_scan)
45REGISTER_MAP_ELEMENT(ien_int_3)
46REGISTER_MAP_ELEMENT(ien_int_2)
47REGISTER_MAP_ELEMENT(ien_int_1)
48REGISTER_MAP_ELEMENT(ien_int_0)
49REGISTER_MAP_ELEMENT(int_level_3_3)
50REGISTER_MAP_ELEMENT(int_level_3_2)
51REGISTER_MAP_ELEMENT(int_level_3_1)
52REGISTER_MAP_ELEMENT(int_level_3_0)
53REGISTER_MAP_ELEMENT(int_level_2_3)
54REGISTER_MAP_ELEMENT(int_level_2_2)
55REGISTER_MAP_ELEMENT(int_level_2_1)
56REGISTER_MAP_ELEMENT(int_level_2_0)
57REGISTER_MAP_ELEMENT(int_level_1_3)
58REGISTER_MAP_ELEMENT(int_level_1_2)
59REGISTER_MAP_ELEMENT(int_level_1_1)
60REGISTER_MAP_ELEMENT(int_level_1_0)
61REGISTER_MAP_ELEMENT(int_level_0_3)
62REGISTER_MAP_ELEMENT(int_level_0_2)
63REGISTER_MAP_ELEMENT(int_level_0_1)
64REGISTER_MAP_ELEMENT(int_level_0_0)
65REGISTER_MAP_ELEMENT(int_docsis_en)
66REGISTER_MAP_ELEMENT(mips_pll_setup)
67REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
68REGISTER_MAP_ELEMENT(test_bus)
69REGISTER_MAP_ELEMENT(crt_spare)
70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71REGISTER_MAP_ELEMENT(usb2_strap)
72REGISTER_MAP_ELEMENT(ehci_hcapbase)
73REGISTER_MAP_ELEMENT(ohci_hc_revision)
74REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75REGISTER_MAP_ELEMENT(usb2_control)
76REGISTER_MAP_ELEMENT(usb2_stbus_obc)
77REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79REGISTER_MAP_ELEMENT(pcie_regs)
80REGISTER_MAP_ELEMENT(tim_ch)
81REGISTER_MAP_ELEMENT(tim_cl)
82REGISTER_MAP_ELEMENT(gpio_dout)
83REGISTER_MAP_ELEMENT(gpio_din)
84REGISTER_MAP_ELEMENT(gpio_dir)
85REGISTER_MAP_ELEMENT(watchdog)
86REGISTER_MAP_ELEMENT(front_panel)
87REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89REGISTER_MAP_ELEMENT(crt_ext_ctl)
90REGISTER_MAP_ELEMENT(register_maps)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
deleted file mode 100644
index 06712abb3e55..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASIC_GAIA,
31 ASICS /* Number of supported ASICs */
32};
33
34/* hardcoded values read from Chip Version registers */
35#define CRONUS_10 0x0B4C1C20
36#define CRONUS_11 0x0B4C1C21
37#define CRONUSLITE_10 0x0B4C1C40
38
39#define NAND_FLASH_BASE 0x03000000
40#define CALLIOPE_IO_BASE 0x08000000
41#define GAIA_IO_BASE 0x09000000
42#define CRONUS_IO_BASE 0x09000000
43#define ZEUS_IO_BASE 0x09000000
44
45#define ASIC_IO_SIZE 0x01000000
46
47/* Definitions for backward compatibility */
48#define UART1_INTSTAT uart1_intstat
49#define UART1_INTEN uart1_inten
50#define UART1_CONFIG1 uart1_config1
51#define UART1_CONFIG2 uart1_config2
52#define UART1_DIVISORHI uart1_divisorhi
53#define UART1_DIVISORLO uart1_divisorlo
54#define UART1_DATA uart1_data
55#define UART1_STATUS uart1_status
56
57/* ASIC register enumeration */
58union register_map_entry {
59 unsigned long phys;
60 u32 *virt;
61};
62
63#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
64struct register_map {
65#include <asm/mach-powertv/asic_reg_map.h>
66};
67#undef REGISTER_MAP_ELEMENT
68
69/**
70 * register_map_offset_phys - add an offset to the physical address
71 * @map: Pointer to the &struct register_map
72 * @offset: Value to add
73 *
74 * Only adds the base to non-zero physical addresses
75 */
76static inline void register_map_offset_phys(struct register_map *map,
77 unsigned long offset)
78{
79#define REGISTER_MAP_ELEMENT(x) do { \
80 if (map->x.phys != 0) \
81 map->x.phys += offset; \
82 } while (false);
83
84#include <asm/mach-powertv/asic_reg_map.h>
85#undef REGISTER_MAP_ELEMENT
86}
87
88/**
89 * register_map_virtualize - Convert &register_map to virtual addresses
90 * @map: Pointer to &register_map to virtualize
91 */
92static inline void register_map_virtualize(struct register_map *map)
93{
94#define REGISTER_MAP_ELEMENT(x) do { \
95 map->x.virt = (!map->x.phys) ? NULL : \
96 UNCAC_ADDR(phys_to_virt(map->x.phys)); \
97 } while (false);
98
99#include <asm/mach-powertv/asic_reg_map.h>
100#undef REGISTER_MAP_ELEMENT
101}
102
103extern struct register_map _asic_register_map;
104extern unsigned long asic_phy_base;
105
106/*
107 * Macros to interface to registers through their ioremapped address
108 * asic_reg_phys_addr Returns the physical address of the given register
109 * asic_reg_addr Returns the iomapped virtual address of the given
110 * register.
111 */
112#define asic_reg_addr(x) (_asic_register_map.x.virt)
113#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
114 (unsigned long) asic_reg_addr(x))))
115
116/*
117 * The asic_reg macro is gone. It should be replaced by either asic_read or
118 * asic_write, as appropriate.
119 */
120
121#define asic_read(x) readl(asic_reg_addr(x))
122#define asic_write(v, x) writel(v, asic_reg_addr(x))
123
124extern void asic_irq_init(void);
125#endif
diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
deleted file mode 100644
index 58c76ec32a19..000000000000
--- a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (C) 2010 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
20#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
21#define cpu_has_tlb 1
22#define cpu_has_4kex 1
23#define cpu_has_3k_cache 0
24#define cpu_has_4k_cache 1
25#define cpu_has_tx39_cache 0
26#define cpu_has_fpu 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30#define cpu_has_vce 0
31#define cpu_has_cache_cdex_p 0
32#define cpu_has_cache_cdex_s 0
33#define cpu_has_mcheck 1
34#define cpu_has_ejtag 1
35#define cpu_has_llsc 1
36#define cpu_has_mips16 0
37#define cpu_has_mdmx 0
38#define cpu_has_mips3d 0
39#define cpu_has_smartmips 0
40#define cpu_has_vtag_icache 0
41#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 1
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47#define cpu_has_dsp 0
48#define cpu_has_dsp2 0
49#define cpu_has_mipsmt 0
50#define cpu_has_userlocal 0
51#define cpu_has_nofpuex 0
52#define cpu_has_64bits 0
53#define cpu_has_64bit_zero_reg 0
54#define cpu_has_vint 1
55#define cpu_has_veic 1
56#define cpu_has_inclusive_pcaches 0
57
58#define cpu_dcache_line_size() 32
59#define cpu_icache_line_size() 32
60#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
deleted file mode 100644
index 5d4c3fe04722..000000000000
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/device.h>
17#include <asm/mach-powertv/asic.h>
18
19static inline bool is_kseg2(void *addr)
20{
21 return (unsigned long)addr >= KSEG2;
22}
23
24static inline unsigned long virt_to_phys_from_pte(void *addr)
25{
26 pgd_t *pgd;
27 pud_t *pud;
28 pmd_t *pmd;
29 pte_t *ptep, pte;
30
31 unsigned long virt_addr = (unsigned long)addr;
32 unsigned long phys_addr = 0UL;
33
34 /* get the page global directory. */
35 pgd = pgd_offset_k(virt_addr);
36
37 if (!pgd_none(*pgd)) {
38 /* get the page upper directory */
39 pud = pud_offset(pgd, virt_addr);
40 if (!pud_none(*pud)) {
41 /* get the page middle directory */
42 pmd = pmd_offset(pud, virt_addr);
43 if (!pmd_none(*pmd)) {
44 /* get a pointer to the page table entry */
45 ptep = pte_offset(pmd, virt_addr);
46 pte = *ptep;
47 /* check for a valid page */
48 if (pte_present(pte)) {
49 /* get the physical address the page is
50 * referring to */
51 phys_addr = (unsigned long)
52 page_to_phys(pte_page(pte));
53 /* add the offset within the page */
54 phys_addr |= (virt_addr & ~PAGE_MASK);
55 }
56 }
57 }
58 }
59
60 return phys_addr;
61}
62
63static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
64 size_t size)
65{
66 if (is_kseg2(addr))
67 return phys_to_dma(virt_to_phys_from_pte(addr));
68 else
69 return phys_to_dma(virt_to_phys(addr));
70}
71
72static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
73 struct page *page)
74{
75 return phys_to_dma(page_to_phys(page));
76}
77
78static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
79 dma_addr_t dma_addr)
80{
81 return dma_to_phys(dma_addr);
82}
83
84static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
85 size_t size, enum dma_data_direction direction)
86{
87}
88
89static inline int plat_dma_supported(struct device *dev, u64 mask)
90{
91 /*
92 * we fall back to GFP_DMA when the mask isn't all 1s,
93 * so we can't guarantee allocations that must be
94 * within a tighter range than GFP_DMA..
95 */
96 if (mask < DMA_BIT_MASK(24))
97 return 0;
98
99 return 1;
100}
101
102static inline int plat_device_is_coherent(struct device *dev)
103{
104 return 0;
105}
106
107#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
deleted file mode 100644
index 6c463be62156..000000000000
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
deleted file mode 100644
index c86ef094ec37..000000000000
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13#include <linux/log2.h>
14#include <linux/compiler.h>
15
16#include <asm/pgtable-bits.h>
17#include <asm/addrspace.h>
18
19/* We're going to mess with bits, so get sizes */
20#define IOR_BPC 8 /* Bits per char */
21#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t))
22#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t))
23
24/*
25 * Define the granularity of physical/DMA mapping in terms of the number
26 * of bits that defines the offset within a grain. These will be the
27 * least significant bits of the address. The rest of a physical or DMA
28 * address will be used to index into an appropriate table to find the
29 * offset to add to the address to yield the corresponding DMA or physical
30 * address, respectively.
31 */
32#define IOR_LSBITS 22 /* Bits in a grain */
33
34/*
35 * Compute the number of most significant address bits after removing those
36 * used for the offset within a grain and then compute the number of table
37 * entries for the conversion.
38 */
39#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS)
40#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
41
42#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS)
43#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS)
44
45/*
46 * Define data structures used as elements in the arrays for the conversion
47 * between physical and DMA addresses. We do some slightly fancy math to
48 * compute the width of the offset element of the conversion tables so
49 * that we can have the smallest conversion tables. Next, round up the
50 * sizes to the next higher power of two, i.e. the offset element will have
51 * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
52 * bits. Finally, we compute a shift value that puts the most significant
53 * bits of the offset into the most significant bits of the offset element.
54 * This makes it more efficient on processors without barrel shifters and
55 * easier to see the values if the conversion table is dumped in binary.
56 */
57#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n))
58#define IOR_OFFSET_WIDTH(n) \
59 (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
60
61#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
62#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
63
64#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
65#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
66
67struct ior_phys_to_dma {
68 dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
69 __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
70};
71
72struct ior_dma_to_phys {
73 dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
74 __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
75};
76
77extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
78extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
79
80static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
81{
82 return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
83}
84
85static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
86{
87 return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
88}
89
90/* These are not portable and should not be used in drivers. Drivers should
91 * be using ioremap() and friends to map physical addresses to virtual
92 * addresses and dma_map*() and friends to map virtual addresses into DMA
93 * addresses and back.
94 */
95static inline dma_addr_t phys_to_dma(phys_addr_t phys)
96{
97 return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
98}
99
100static inline phys_addr_t dma_to_phys(dma_addr_t dma)
101{
102 return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
103}
104
105extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
106 dma_addr_t size);
107
108/*
109 * Allow physical addresses to be fixed up to help peripherals located
110 * outside the low 32-bit range -- generic pass-through version.
111 */
112static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
113{
114 return phys_addr;
115}
116
117/*
118 * Handle the special case of addresses the area aliased into the first
119 * 512 MiB of the processor's physical address space. These turn into either
120 * kseg0 or kseg1 addresses, depending on flags.
121 */
122static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
123 unsigned long flags)
124{
125 phys_addr_t start_offset;
126 void __iomem *result = NULL;
127
128 /* Start by checking to see whether this is an aliased address */
129 start_offset = _dma_to_phys_offset_raw(start);
130
131 /*
132 * If:
133 * o the memory is aliased into the first 512 MiB, and
134 * o the start and end are in the same RAM bank, and
135 * o we don't have a zero size or wrap around, and
136 * o we are supposed to create an uncached mapping,
137 * handle this is a kseg0 or kseg1 address
138 */
139 if (start_offset != 0) {
140 phys_addr_t last;
141 dma_addr_t dma_to_phys_offset;
142
143 last = start + size - 1;
144 dma_to_phys_offset =
145 _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
146
147 if (dma_to_phys_offset == start_offset &&
148 size != 0 && start <= last) {
149 phys_t adjusted_start;
150 adjusted_start = start + start_offset;
151 if (flags == _CACHE_UNCACHED)
152 result = (void __iomem *) (unsigned long)
153 CKSEG1ADDR(adjusted_start);
154 else
155 result = (void __iomem *) (unsigned long)
156 CKSEG0ADDR(adjusted_start);
157 }
158 }
159
160 return result;
161}
162
163static inline int plat_iounmap(const volatile void __iomem *addr)
164{
165 return 0;
166}
167#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
deleted file mode 100644
index 4bd5d0c61a91..000000000000
--- a/arch/mips/include/asm/mach-powertv/irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
deleted file mode 100644
index 6f3e9a0fcf8c..000000000000
--- a/arch/mips/include/asm/mach-powertv/powertv-clock.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
deleted file mode 100644
index c5651c8e58d1..000000000000
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
10 */
11#ifndef __ASM_MACH_POWERTV_WAR_H
12#define __ASM_MACH_POWERTV_WAR_H
13
14#define R4600_V1_INDEX_ICACHEOP_WAR 0
15#define R4600_V1_HIT_CACHEOP_WAR 0
16#define R4600_V2_HIT_CACHEOP_WAR 0
17#define R5432_CP0_INTERRUPT_WAR 0
18#define BCM1250_M3_WAR 0
19#define SIBYTE_1956_WAR 0
20#define MIPS4K_ICACHE_REFILL_WAR 1
21#define MIPS_CACHE_SYNC_WAR 1
22#define TX49XX_ICACHE_INDEX_INV_WAR 0
23#define ICACHE_REFILLS_WORKAROUND_WAR 1
24#define R10000_LLSC_WAR 0
25#define MIPS34K_MISSED_ITLB_WAR 0
26
27#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 81773a4508f4..1c1b71752c84 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
26obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 26obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
27obj-$(CONFIG_CSRC_GIC) += csrc-gic.o 27obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
28obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 28obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
29obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
30obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 29obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
31obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 30obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
32obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 31obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
deleted file mode 100644
index abd99ea911ae..000000000000
--- a/arch/mips/kernel/csrc-powertv.c
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Copyright (C) 2008 Scientific-Atlanta, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18/*
19 * The file comes from kernel/csrc-r4k.c
20 */
21#include <linux/clocksource.h>
22#include <linux/init.h>
23
24#include <asm/time.h> /* Not included in linux/time.h */
25
26#include <asm/mach-powertv/asic_regs.h>
27#include "powertv-clock.h"
28
29/* MIPS PLL Register Definitions */
30#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF)
31#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF)
32#define PLL_GET_P(x) (((x) >> 24) & 0x00000007)
33
34/*
35 * returns: Clock frequency in kHz
36 */
37unsigned int __init mips_get_pll_freq(void)
38{
39 unsigned int pll_reg, m, n, p;
40 unsigned int fin = 54000; /* Base frequency in kHz */
41 unsigned int fout;
42
43 /* Read PLL register setting */
44 pll_reg = asic_read(mips_pll_setup);
45 m = PLL_GET_M(pll_reg);
46 n = PLL_GET_N(pll_reg);
47 p = PLL_GET_P(pll_reg);
48 pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p);
49
50 /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
51 fout = ((2 * n * fin) / (m * (0x01 << p)));
52
53 pr_info("MIPS Clock Freq=%d kHz\n", fout);
54
55 return fout;
56}
57
58static cycle_t c0_hpt_read(struct clocksource *cs)
59{
60 return read_c0_count();
61}
62
63static struct clocksource clocksource_mips = {
64 .name = "powertv-counter",
65 .read = c0_hpt_read,
66 .mask = CLOCKSOURCE_MASK(32),
67 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
68};
69
70static void __init powertv_c0_hpt_clocksource_init(void)
71{
72 unsigned int pll_freq = mips_get_pll_freq();
73
74 pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
75 (pll_freq % 1000) * 100 / 1000);
76
77 mips_hpt_frequency = pll_freq / 2 * 1000;
78
79 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
80
81 clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
82}
83
84/**
85 * struct tim_c - free running counter
86 * @hi: High 16 bits of the counter
87 * @lo: Low 32 bits of the counter
88 *
89 * Lays out the structure of the free running counter in memory. This counter
90 * increments at a rate of 27 MHz/8 on all platforms.
91 */
92struct tim_c {
93 unsigned int hi;
94 unsigned int lo;
95};
96
97static struct tim_c *tim_c;
98
99static cycle_t tim_c_read(struct clocksource *cs)
100{
101 unsigned int hi;
102 unsigned int next_hi;
103 unsigned int lo;
104
105 hi = readl(&tim_c->hi);
106
107 for (;;) {
108 lo = readl(&tim_c->lo);
109 next_hi = readl(&tim_c->hi);
110 if (next_hi == hi)
111 break;
112 hi = next_hi;
113 }
114
115pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
116 return ((u64) hi << 32) | lo;
117}
118
119#define TIM_C_SIZE 48 /* # bits in the timer */
120
121static struct clocksource clocksource_tim_c = {
122 .name = "powertv-tim_c",
123 .read = tim_c_read,
124 .mask = CLOCKSOURCE_MASK(TIM_C_SIZE),
125 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
126};
127
128/**
129 * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
130 *
131 * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
132 * 1 / (27,000,000/8) seconds.
133 */
134static void __init powertv_tim_c_clocksource_init(void)
135{
136 const unsigned long counts_per_second = 27000000 / 8;
137
138 clocksource_tim_c.rating = 200;
139
140 clocksource_register_hz(&clocksource_tim_c, counts_per_second);
141 tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
142}
143
144/**
145 powertv_clocksource_init - initialize all clocksources
146 */
147void __init powertv_clocksource_init(void)
148{
149 powertv_c0_hpt_clocksource_init();
150 powertv_tim_c_clocksource_init();
151}
diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig
deleted file mode 100644
index dd91fbacbcba..000000000000
--- a/arch/mips/powertv/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
1config BOOTLOADER_FAMILY
2 string "POWERTV Bootloader Family string"
3 default "85"
4 depends on POWERTV
5 help
6 This value should be specified when the bootloader driver is disabled
7 and must be exactly two characters long. Families supported are:
8 R1 - RNG-100 R2 - RNG-200
9 A1 - Class A B1 - Class B
10 E1 - Class E F1 - Class F
11 44 - 45xx 46 - 46xx
12 85 - 85xx 86 - 86xx
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
deleted file mode 100644
index 39ca9f8d63ae..000000000000
--- a/arch/mips/powertv/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
1#
2# Carsten Langgaard, carstenl@mips.com
3# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4#
5# Carsten Langgaard, carstenl@mips.com
6# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
7# Portions copyright (C) 2009 Cisco Systems, Inc.
8#
9# This program is free software; you can distribute it and/or modify it
10# under the terms of the GNU General Public License (Version 2) as
11# published by the Free Software Foundation.
12#
13# This program is distributed in the hope it will be useful, but WITHOUT
14# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16# for more details.
17#
18# You should have received a copy of the GNU General Public License along
19# with this program; if not, write to the Free Software Foundation, Inc.,
20# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21#
22# Makefile for the Cisco PowerTV-specific kernel interface routines
23# under Linux.
24#
25
26obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \
27 asic/ pci/
28
29obj-$(CONFIG_USB) += powertv-usb.o
diff --git a/arch/mips/powertv/Platform b/arch/mips/powertv/Platform
deleted file mode 100644
index 4eb5af1d8eea..000000000000
--- a/arch/mips/powertv/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Cisco PowerTV Platform
3#
4platform-$(CONFIG_POWERTV) += powertv/
5cflags-$(CONFIG_POWERTV) += \
6 -I$(srctree)/arch/mips/include/asm/mach-powertv
7load-$(CONFIG_POWERTV) += 0xffffffff90800000
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
deleted file mode 100644
index 35dcc53eb25f..000000000000
--- a/arch/mips/powertv/asic/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \
20 asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \
21 prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
deleted file mode 100644
index 2f539b43f56b..000000000000
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Locations of devices in the Calliope ASIC.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
30
31const struct register_map calliope_register_map __initconst = {
32 .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
33 .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
34 .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
35
36 .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
37 .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
38 .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
39 .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
43 .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
44 .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
45 .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
46 .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
47 .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
48 .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
49 .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
50
51 .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
52 .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
53 .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
54 .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
55 .int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
56 .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
57 .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
58 .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
59 .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
60 .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
61 .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
62 .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
63 .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
64 .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
65 .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
66 .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
67 .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
68 .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
69 .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
70 .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
71 .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
72 .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
73 .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
74 .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
75 .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
76 .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
78
79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
80 .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)},
81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
84 .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
85 .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
86 .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
87 .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
88 .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
89 .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
90 .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
91 .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
92
93 .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
94 .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
95 .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
96 .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
97 .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
98 .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
99 .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
100 .front_panel = {.phys = 0x000000}, /* -not used- */
101};
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
deleted file mode 100644
index 7f8f3429b35a..000000000000
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Locations of devices in the Cronus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
30
31const struct register_map cronus_register_map __initconst = {
32 .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
33 .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
34 .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
35
36 .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)},
37 .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)},
38 .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)},
39 .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)},
43 .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)},
44 .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)},
45 .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)},
46 .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)},
47 .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)},
48 .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)},
49 .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)},
50
51 .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)},
52 .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)},
53 .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)},
54 .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)},
55 .int_config = {.phys = CRONUS_ADDR(0x2A2810)},
56 .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)},
57 .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)},
58 .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)},
59 .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)},
60 .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)},
61 .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)},
62 .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)},
63 .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)},
64 .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)},
65 .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)},
66 .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)},
67 .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)},
68 .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)},
69 .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)},
70 .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)},
71 .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)},
72 .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)},
73 .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)},
74 .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)},
75 .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)},
76 .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)},
77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
78
79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
80 .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)},
81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)},
87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
90 .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)},
91 .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)},
92
93 .pcie_regs = {.phys = CRONUS_ADDR(0x220000)},
94 .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)},
95 .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)},
96 .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)},
97 .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)},
98 .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)},
99 .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)},
100 .front_panel = {.phys = CRONUS_ADDR(0x2A3800)},
101};
diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c
deleted file mode 100644
index 1265b49012e6..000000000000
--- a/arch/mips/powertv/asic/asic-gaia.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Locations of devices in the Gaia ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#include <linux/init.h>
24#include <asm/mach-powertv/asic.h>
25
26const struct register_map gaia_register_map __initconst = {
27 .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000},
28 .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038},
29 .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
30
31 .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800},
32 .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804},
33 .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808},
34 .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C},
35
36 /* The registers of IRBlaster */
37 .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800},
38 .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804},
39 .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808},
40 .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C},
41 .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810},
42 .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814},
43 .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818},
44 .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C},
45
46 .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800},
47 .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804},
48 .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808},
49 .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C},
50 .int_config = {.phys = GAIA_IO_BASE + 0x2A2810},
51 .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818},
52 .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830},
53 .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834},
54 .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838},
55 .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C},
56 .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880},
57 .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884},
58 .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888},
59 .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C},
60 .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890},
61 .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894},
62 .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898},
63 .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C},
64 .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0},
65 .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4},
66 .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8},
67 .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC},
68 .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0},
69 .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4},
70 .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8},
71 .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC},
72 .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4},
73
74 .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000},
75 .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024},
76 .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC},
77 .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108},
78 .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C},
79 .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014},
80 .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00},
81 .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00},
82 .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004},
83 .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C},
84 .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00},
85 .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04},
86 .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08},
87
88 .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000},
89 .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10},
90 .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14},
91 .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20},
92 .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24},
93 .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C},
94 .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30},
95 .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800},
96};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
deleted file mode 100644
index 14e7de137e03..000000000000
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Locations of devices in the Zeus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x))
30
31const struct register_map zeus_register_map __initconst = {
32 .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
33 .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
34 .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
35
36 .chipver3 = {.phys = ZEUS_ADDR(0x280800)},
37 .chipver2 = {.phys = ZEUS_ADDR(0x280804)},
38 .chipver1 = {.phys = ZEUS_ADDR(0x280808)},
39 .chipver0 = {.phys = ZEUS_ADDR(0x28080c)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = ZEUS_ADDR(0x281800)},
43 .uart1_inten = {.phys = ZEUS_ADDR(0x281804)},
44 .uart1_config1 = {.phys = ZEUS_ADDR(0x281808)},
45 .uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)},
46 .uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)},
47 .uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)},
48 .uart1_data = {.phys = ZEUS_ADDR(0x281818)},
49 .uart1_status = {.phys = ZEUS_ADDR(0x28181C)},
50
51 .int_stat_3 = {.phys = ZEUS_ADDR(0x282800)},
52 .int_stat_2 = {.phys = ZEUS_ADDR(0x282804)},
53 .int_stat_1 = {.phys = ZEUS_ADDR(0x282808)},
54 .int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)},
55 .int_config = {.phys = ZEUS_ADDR(0x282810)},
56 .int_int_scan = {.phys = ZEUS_ADDR(0x282818)},
57 .ien_int_3 = {.phys = ZEUS_ADDR(0x282830)},
58 .ien_int_2 = {.phys = ZEUS_ADDR(0x282834)},
59 .ien_int_1 = {.phys = ZEUS_ADDR(0x282838)},
60 .ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)},
61 .int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)},
62 .int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)},
63 .int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)},
64 .int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)},
65 .int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)},
66 .int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)},
67 .int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)},
68 .int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)},
69 .int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)},
70 .int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)},
71 .int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)},
72 .int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)},
73 .int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)},
74 .int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)},
75 .int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)},
76 .int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)},
77 .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
78
79 .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
80 .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)},
81 .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
82 .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
83 .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
84 .usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)},
85 .ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)},
86 .ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)},
87 .bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)},
88 .usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)},
89 .usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)},
90 .usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)},
91 .usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)},
92
93 .pcie_regs = {.phys = ZEUS_ADDR(0x200000)},
94 .tim_ch = {.phys = ZEUS_ADDR(0x282C10)},
95 .tim_cl = {.phys = ZEUS_ADDR(0x282C14)},
96 .gpio_dout = {.phys = ZEUS_ADDR(0x282c20)},
97 .gpio_din = {.phys = ZEUS_ADDR(0x282c24)},
98 .gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)},
99 .watchdog = {.phys = ZEUS_ADDR(0x282c30)},
100 .front_panel = {.phys = ZEUS_ADDR(0x283800)},
101};
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
deleted file mode 100644
index 8380605d597d..000000000000
--- a/arch/mips/powertv/asic/asic_devices.c
+++ /dev/null
@@ -1,549 +0,0 @@
1/*
2 *
3 * Description: Defines the platform resources for Gaia-based settops.
4 *
5 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 * NOTE: The bootloader allocates persistent memory at an address which is
22 * 16 MiB below the end of the highest address in KSEG0. All fixed
23 * address memory reservations must avoid this region.
24 */
25
26#include <linux/device.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/resource.h>
30#include <linux/serial_reg.h>
31#include <linux/io.h>
32#include <linux/bootmem.h>
33#include <linux/mm.h>
34#include <linux/platform_device.h>
35#include <linux/module.h>
36#include <asm/page.h>
37#include <linux/swap.h>
38#include <linux/highmem.h>
39#include <linux/dma-mapping.h>
40
41#include <asm/mach-powertv/asic.h>
42#include <asm/mach-powertv/asic_regs.h>
43#include <asm/mach-powertv/interrupts.h>
44
45#ifdef CONFIG_BOOTLOADER_DRIVER
46#include <asm/mach-powertv/kbldr.h>
47#endif
48#include <asm/bootinfo.h>
49
50#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
51
52/*
53 * Forward Prototypes
54 */
55static void pmem_setup_resource(void);
56
57/*
58 * Global Variables
59 */
60enum asic_type asic;
61
62unsigned int platform_features;
63unsigned int platform_family;
64struct register_map _asic_register_map;
65EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */
66unsigned long asic_phy_base;
67unsigned long asic_base;
68EXPORT_SYMBOL(asic_base); /* Exported for testing */
69struct resource *gp_resources;
70
71/*
72 * Don't recommend to use it directly, it is usually used by kernel internally.
73 * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
74 */
75unsigned long phys_to_dma_offset;
76EXPORT_SYMBOL(phys_to_dma_offset);
77
78/*
79 *
80 * IO Resource Definition
81 *
82 */
83
84struct resource asic_resource = {
85 .name = "ASIC Resource",
86 .start = 0,
87 .end = ASIC_IO_SIZE,
88 .flags = IORESOURCE_MEM,
89};
90
91/*
92 * Allow override of bootloader-specified model
93 * Returns zero on success, a negative errno value on failure. This parameter
94 * allows overriding of the bootloader-specified model.
95 */
96static char __initdata cmdline[COMMAND_LINE_SIZE];
97
98#define FORCEFAMILY_PARAM "forcefamily"
99
100/*
101 * check_forcefamily - check for, and parse, forcefamily command line parameter
102 * @forced_family: Pointer to two-character array in which to store the
103 * value of the forcedfamily parameter, if any.
104 */
105static __init int check_forcefamily(unsigned char forced_family[2])
106{
107 const char *p;
108
109 forced_family[0] = '\0';
110 forced_family[1] = '\0';
111
112 /* Check the command line for a forcefamily directive */
113 strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
114 p = strstr(cmdline, FORCEFAMILY_PARAM);
115 if (p && (p != cmdline) && (*(p - 1) != ' '))
116 p = strstr(p, " " FORCEFAMILY_PARAM "=");
117
118 if (p) {
119 p += strlen(FORCEFAMILY_PARAM "=");
120
121 if (*p == '\0' || *(p + 1) == '\0' ||
122 (*(p + 2) != '\0' && *(p + 2) != ' '))
123 pr_err(FORCEFAMILY_PARAM " must be exactly two "
124 "characters long, ignoring value\n");
125
126 else {
127 forced_family[0] = *p;
128 forced_family[1] = *(p + 1);
129 }
130 }
131
132 return 0;
133}
134
135/*
136 * platform_set_family - determine major platform family type.
137 *
138 * Returns family type; -1 if none
139 * Returns the family type; -1 if none
140 *
141 */
142static __init noinline void platform_set_family(void)
143{
144 unsigned char forced_family[2];
145 unsigned short bootldr_family;
146
147 if (check_forcefamily(forced_family) == 0)
148 bootldr_family = BOOTLDRFAMILY(forced_family[0],
149 forced_family[1]);
150 else
151 bootldr_family = (unsigned short) BOOTLDRFAMILY(
152 CONFIG_BOOTLOADER_FAMILY[0],
153 CONFIG_BOOTLOADER_FAMILY[1]);
154
155 pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
156
157 switch (bootldr_family) {
158 case BOOTLDRFAMILY('R', '1'):
159 platform_family = FAMILY_1500;
160 break;
161 case BOOTLDRFAMILY('4', '4'):
162 platform_family = FAMILY_4500;
163 break;
164 case BOOTLDRFAMILY('4', '6'):
165 platform_family = FAMILY_4600;
166 break;
167 case BOOTLDRFAMILY('A', '1'):
168 platform_family = FAMILY_4600VZA;
169 break;
170 case BOOTLDRFAMILY('8', '5'):
171 platform_family = FAMILY_8500;
172 break;
173 case BOOTLDRFAMILY('R', '2'):
174 platform_family = FAMILY_8500RNG;
175 break;
176 case BOOTLDRFAMILY('8', '6'):
177 platform_family = FAMILY_8600;
178 break;
179 case BOOTLDRFAMILY('B', '1'):
180 platform_family = FAMILY_8600VZB;
181 break;
182 case BOOTLDRFAMILY('E', '1'):
183 platform_family = FAMILY_1500VZE;
184 break;
185 case BOOTLDRFAMILY('F', '1'):
186 platform_family = FAMILY_1500VZF;
187 break;
188 case BOOTLDRFAMILY('8', '7'):
189 platform_family = FAMILY_8700;
190 break;
191 default:
192 platform_family = -1;
193 }
194}
195
196unsigned int platform_get_family(void)
197{
198 return platform_family;
199}
200EXPORT_SYMBOL(platform_get_family);
201
202/*
203 * platform_get_asic - determine the ASIC type.
204 *
205 * Returns the ASIC type, or ASIC_UNKNOWN if unknown
206 *
207 */
208enum asic_type platform_get_asic(void)
209{
210 return asic;
211}
212EXPORT_SYMBOL(platform_get_asic);
213
214/*
215 * set_register_map - set ASIC register configuration
216 * @phys_base: Physical address of the base of the ASIC registers
217 * @map: Description of key ASIC registers
218 */
219static void __init set_register_map(unsigned long phys_base,
220 const struct register_map *map)
221{
222 asic_phy_base = phys_base;
223 _asic_register_map = *map;
224 register_map_virtualize(&_asic_register_map);
225 asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE);
226}
227
228/**
229 * configure_platform - configuration based on platform type.
230 */
231void __init configure_platform(void)
232{
233 platform_set_family();
234
235 switch (platform_family) {
236 case FAMILY_1500:
237 case FAMILY_1500VZE:
238 case FAMILY_1500VZF:
239 platform_features = FFS_CAPABLE;
240 asic = ASIC_CALLIOPE;
241 set_register_map(CALLIOPE_IO_BASE, &calliope_register_map);
242
243 if (platform_family == FAMILY_1500VZE) {
244 gp_resources = non_dvr_vze_calliope_resources;
245 pr_info("Platform: 1500/Vz Class E - "
246 "CALLIOPE, NON_DVR_CAPABLE\n");
247 } else if (platform_family == FAMILY_1500VZF) {
248 gp_resources = non_dvr_vzf_calliope_resources;
249 pr_info("Platform: 1500/Vz Class F - "
250 "CALLIOPE, NON_DVR_CAPABLE\n");
251 } else {
252 gp_resources = non_dvr_calliope_resources;
253 pr_info("Platform: 1500/RNG100 - CALLIOPE, "
254 "NON_DVR_CAPABLE\n");
255 }
256 break;
257
258 case FAMILY_4500:
259 platform_features = FFS_CAPABLE | PCIE_CAPABLE |
260 DISPLAY_CAPABLE;
261 asic = ASIC_ZEUS;
262 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
263 gp_resources = non_dvr_zeus_resources;
264
265 pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
266 break;
267
268 case FAMILY_4600:
269 {
270 unsigned int chipversion = 0;
271
272 /* The settop has PCIE but it isn't used, so don't advertise
273 * it*/
274 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
275
276 /* Cronus and Cronus Lite have the same register map */
277 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
278
279 /* ASIC version will determine if this is a real CronusLite or
280 * Castrati(Cronus) */
281 chipversion = asic_read(chipver3) << 24;
282 chipversion |= asic_read(chipver2) << 16;
283 chipversion |= asic_read(chipver1) << 8;
284 chipversion |= asic_read(chipver0);
285
286 if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
287 asic = ASIC_CRONUS;
288 else
289 asic = ASIC_CRONUSLITE;
290
291 gp_resources = non_dvr_cronuslite_resources;
292 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
293 "chipversion=0x%08X\n",
294 (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
295 chipversion);
296 break;
297 }
298 case FAMILY_4600VZA:
299 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
300 asic = ASIC_CRONUS;
301 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
302 gp_resources = non_dvr_cronus_resources;
303
304 pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
305 break;
306
307 case FAMILY_8500:
308 case FAMILY_8500RNG:
309 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
310 DISPLAY_CAPABLE;
311 asic = ASIC_ZEUS;
312 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
313 gp_resources = dvr_zeus_resources;
314
315 pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
316 break;
317
318 case FAMILY_8600:
319 case FAMILY_8600VZB:
320 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
321 DISPLAY_CAPABLE;
322 asic = ASIC_CRONUS;
323 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
324 gp_resources = dvr_cronus_resources;
325
326 pr_info("Platform: 8600/Vz Class B - CRONUS, "
327 "DVR_CAPABLE\n");
328 break;
329
330 case FAMILY_8700:
331 platform_features = FFS_CAPABLE | PCIE_CAPABLE;
332 asic = ASIC_GAIA;
333 set_register_map(GAIA_IO_BASE, &gaia_register_map);
334 gp_resources = dvr_gaia_resources;
335
336 pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n");
337 break;
338
339 default:
340 pr_crit("Platform: UNKNOWN PLATFORM\n");
341 break;
342 }
343
344 switch (asic) {
345 case ASIC_ZEUS:
346 phys_to_dma_offset = 0x30000000;
347 break;
348 case ASIC_CALLIOPE:
349 phys_to_dma_offset = 0x10000000;
350 break;
351 case ASIC_CRONUSLITE:
352 /* Fall through */
353 case ASIC_CRONUS:
354 /*
355 * TODO: We suppose 0x10000000 aliases into 0x20000000-
356 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
357 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
358 */
359 phys_to_dma_offset = 0x10000000;
360 break;
361 default:
362 phys_to_dma_offset = 0x00000000;
363 break;
364 }
365}
366
367/*
368 * RESOURCE ALLOCATION
369 *
370 */
371/*
372 * Allocates/reserves the Platform memory resources early in the boot process.
373 * This ignores any resources that are designated IORESOURCE_IO
374 */
375void __init platform_alloc_bootmem(void)
376{
377 int i;
378 int total = 0;
379
380 /* Get persistent memory data from command line before allocating
381 * resources. This need to happen before normal command line parsing
382 * has been done */
383 pmem_setup_resource();
384
385 /* Loop through looking for resources that want a particular address */
386 for (i = 0; gp_resources[i].flags != 0; i++) {
387 int size = resource_size(&gp_resources[i]);
388 if ((gp_resources[i].start != 0) &&
389 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
390 reserve_bootmem(dma_to_phys(gp_resources[i].start),
391 size, 0);
392 total += resource_size(&gp_resources[i]);
393 pr_info("reserve resource %s at %08x (%u bytes)\n",
394 gp_resources[i].name, gp_resources[i].start,
395 resource_size(&gp_resources[i]));
396 }
397 }
398
399 /* Loop through assigning addresses for those that are left */
400 for (i = 0; gp_resources[i].flags != 0; i++) {
401 int size = resource_size(&gp_resources[i]);
402 if ((gp_resources[i].start == 0) &&
403 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
404 void *mem = alloc_bootmem_pages(size);
405
406 if (mem == NULL)
407 pr_err("Unable to allocate bootmem pages "
408 "for %s\n", gp_resources[i].name);
409
410 else {
411 gp_resources[i].start =
412 phys_to_dma(virt_to_phys(mem));
413 gp_resources[i].end =
414 gp_resources[i].start + size - 1;
415 total += size;
416 pr_info("allocate resource %s at %08x "
417 "(%u bytes)\n",
418 gp_resources[i].name,
419 gp_resources[i].start, size);
420 }
421 }
422 }
423
424 pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
425
426 /* indicate resources that are platform I/O related */
427 for (i = 0; gp_resources[i].flags != 0; i++) {
428 if ((gp_resources[i].start != 0) &&
429 ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
430 pr_info("reserved platform resource %s at %08x\n",
431 gp_resources[i].name, gp_resources[i].start);
432 }
433 }
434}
435
436/*
437 *
438 * PERSISTENT MEMORY (PMEM) CONFIGURATION
439 *
440 */
441static unsigned long pmemaddr __initdata;
442
443static int __init early_param_pmemaddr(char *p)
444{
445 pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
446 return 0;
447}
448early_param("pmemaddr", early_param_pmemaddr);
449
450static long pmemlen __initdata;
451
452static int __init early_param_pmemlen(char *p)
453{
454/* TODO: we can use this code when and if the bootloader ever changes this */
455#if 0
456 pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
457#else
458 pmemlen = 0x20000;
459#endif
460 return 0;
461}
462early_param("pmemlen", early_param_pmemlen);
463
464/*
465 * Set up persistent memory. If we were given values, we patch the array of
466 * resources. Otherwise, persistent memory may be allocated anywhere at all.
467 */
468static void __init pmem_setup_resource(void)
469{
470 struct resource *resource;
471 resource = asic_resource_get("DiagPersistentMemory");
472
473 if (resource && pmemaddr && pmemlen) {
474 /* The address provided by bootloader is in kseg0. Convert to
475 * a bus address. */
476 resource->start = phys_to_dma(pmemaddr - 0x80000000);
477 resource->end = resource->start + pmemlen - 1;
478
479 pr_info("persistent memory: start=0x%x end=0x%x\n",
480 resource->start, resource->end);
481 }
482}
483
484/*
485 *
486 * RESOURCE ACCESS FUNCTIONS
487 *
488 */
489
490/**
491 * asic_resource_get - retrieves parameters for a platform resource.
492 * @name: string to match resource
493 *
494 * Returns a pointer to a struct resource corresponding to the given name.
495 *
496 * CANNOT BE NAMED platform_resource_get, which would be the obvious choice,
497 * as this function name is already declared
498 */
499struct resource *asic_resource_get(const char *name)
500{
501 int i;
502
503 for (i = 0; gp_resources[i].flags != 0; i++) {
504 if (strcmp(gp_resources[i].name, name) == 0)
505 return &gp_resources[i];
506 }
507
508 return NULL;
509}
510EXPORT_SYMBOL(asic_resource_get);
511
512/**
513 * platform_release_memory - release pre-allocated memory
514 * @ptr: pointer to memory to release
515 * @size: size of resource
516 *
517 * This must only be called for memory allocated or reserved via the boot
518 * memory allocator.
519 */
520void platform_release_memory(void *ptr, int size)
521{
522 free_reserved_area(ptr, ptr + size, -1, NULL);
523}
524EXPORT_SYMBOL(platform_release_memory);
525
526/*
527 *
528 * FEATURE AVAILABILITY FUNCTIONS
529 *
530 */
531int platform_supports_dvr(void)
532{
533 return (platform_features & DVR_CAPABLE) != 0;
534}
535
536int platform_supports_ffs(void)
537{
538 return (platform_features & FFS_CAPABLE) != 0;
539}
540
541int platform_supports_pcie(void)
542{
543 return (platform_features & PCIE_CAPABLE) != 0;
544}
545
546int platform_supports_display(void)
547{
548 return (platform_features & DISPLAY_CAPABLE) != 0;
549}
diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
deleted file mode 100644
index f44cd9295cae..000000000000
--- a/arch/mips/powertv/asic/asic_int.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 * Portions copyright (C) 2009 Cisco Systems, Inc.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * Routines for generic manipulation of the interrupts found on the PowerTV
21 * platform.
22 *
23 * The interrupt controller is located in the South Bridge a PIIX4 device
24 * with two internal 82C95 interrupt controllers.
25 */
26#include <linux/init.h>
27#include <linux/irq.h>
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/kernel_stat.h>
31#include <linux/kernel.h>
32#include <linux/random.h>
33
34#include <asm/irq_cpu.h>
35#include <linux/io.h>
36#include <asm/irq_regs.h>
37#include <asm/setup.h>
38#include <asm/mips-boards/generic.h>
39
40#include <asm/mach-powertv/asic_regs.h>
41
42static DEFINE_RAW_SPINLOCK(asic_irq_lock);
43
44static inline int get_int(void)
45{
46 unsigned long flags;
47 int irq;
48
49 raw_spin_lock_irqsave(&asic_irq_lock, flags);
50
51 irq = (asic_read(int_int_scan) >> 4) - 1;
52
53 if (irq == 0 || irq >= NR_IRQS)
54 irq = -1;
55
56 raw_spin_unlock_irqrestore(&asic_irq_lock, flags);
57
58 return irq;
59}
60
61static void asic_irqdispatch(void)
62{
63 int irq;
64
65 irq = get_int();
66 if (irq < 0)
67 return; /* interrupt has already been cleared */
68
69 do_IRQ(irq);
70}
71
72static inline int clz(unsigned long x)
73{
74 __asm__(
75 " .set push \n"
76 " .set mips32 \n"
77 " clz %0, %1 \n"
78 " .set pop \n"
79 : "=r" (x)
80 : "r" (x));
81
82 return x;
83}
84
85/*
86 * Version of ffs that only looks at bits 12..15.
87 */
88static inline unsigned int irq_ffs(unsigned int pending)
89{
90 return fls(pending) - 1 + CAUSEB_IP;
91}
92
93/*
94 * TODO: check how it works under EIC mode.
95 */
96asmlinkage void plat_irq_dispatch(void)
97{
98 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
99 int irq;
100
101 irq = irq_ffs(pending);
102
103 if (irq == CAUSEF_IP3)
104 asic_irqdispatch();
105 else if (irq >= 0)
106 do_IRQ(irq);
107 else
108 spurious_interrupt();
109}
110
111void __init arch_init_irq(void)
112{
113 int i;
114
115 asic_irq_init();
116
117 /*
118 * Initialize interrupt exception vectors.
119 */
120 if (cpu_has_veic || cpu_has_vint) {
121 int nvec = cpu_has_veic ? 64 : 8;
122 for (i = 0; i < nvec; i++)
123 set_vi_handler(i, asic_irqdispatch);
124 }
125}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
deleted file mode 100644
index 9344902dc586..000000000000
--- a/arch/mips/powertv/asic/irq_asic.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Portions copyright (C) 2005-2009 Scientific Atlanta
3 * Portions copyright (C) 2009 Cisco Systems, Inc.
4 *
5 * Modified from arch/mips/kernel/irq-rm7000.c:
6 * Copyright (C) 2003 Ralf Baechle
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/irq.h>
17
18#include <asm/irq_cpu.h>
19#include <asm/mipsregs.h>
20
21#include <asm/mach-powertv/asic_regs.h>
22
23static inline void unmask_asic_irq(struct irq_data *d)
24{
25 unsigned long enable_bit;
26 unsigned int irq = d->irq;
27
28 enable_bit = (1 << (irq & 0x1f));
29
30 switch (irq >> 5) {
31 case 0:
32 asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
33 break;
34 case 1:
35 asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
36 break;
37 case 2:
38 asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
39 break;
40 case 3:
41 asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
42 break;
43 default:
44 BUG();
45 }
46}
47
48static inline void mask_asic_irq(struct irq_data *d)
49{
50 unsigned long disable_mask;
51 unsigned int irq = d->irq;
52
53 disable_mask = ~(1 << (irq & 0x1f));
54
55 switch (irq >> 5) {
56 case 0:
57 asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
58 break;
59 case 1:
60 asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
61 break;
62 case 2:
63 asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
64 break;
65 case 3:
66 asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
67 break;
68 default:
69 BUG();
70 }
71}
72
73static struct irq_chip asic_irq_chip = {
74 .name = "ASIC Level",
75 .irq_mask = mask_asic_irq,
76 .irq_unmask = unmask_asic_irq,
77};
78
79void __init asic_irq_init(void)
80{
81 int i;
82
83 /* set priority to 0 */
84 write_c0_status(read_c0_status() & ~(0x0000fc00));
85
86 asic_write(0, ien_int_0);
87 asic_write(0, ien_int_1);
88 asic_write(0, ien_int_2);
89 asic_write(0, ien_int_3);
90
91 asic_write(0x0fffffff, int_level_3_3);
92 asic_write(0xffffffff, int_level_3_2);
93 asic_write(0xffffffff, int_level_3_1);
94 asic_write(0xffffffff, int_level_3_0);
95 asic_write(0xffffffff, int_level_2_3);
96 asic_write(0xffffffff, int_level_2_2);
97 asic_write(0xffffffff, int_level_2_1);
98 asic_write(0xffffffff, int_level_2_0);
99 asic_write(0xffffffff, int_level_1_3);
100 asic_write(0xffffffff, int_level_1_2);
101 asic_write(0xffffffff, int_level_1_1);
102 asic_write(0xffffffff, int_level_1_0);
103 asic_write(0xffffffff, int_level_0_3);
104 asic_write(0xffffffff, int_level_0_2);
105 asic_write(0xffffffff, int_level_0_1);
106 asic_write(0xffffffff, int_level_0_0);
107
108 asic_write(0xf, int_int_scan);
109
110 /*
111 * Initialize interrupt handlers.
112 */
113 for (i = 0; i < NR_IRQS; i++)
114 irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
115}
diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c
deleted file mode 100644
index 98dc51650577..000000000000
--- a/arch/mips/powertv/asic/prealloc-calliope.c
+++ /dev/null
@@ -1,385 +0,0 @@
1/*
2 * Memory pre-allocations for Calliope boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * NON_DVR_CAPABLE CALLIOPE RESOURCES
31 */
32struct resource non_dvr_calliope_resources[] __initdata =
33{
34 /*
35 * VIDEO / LX1
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~36.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26700000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * Sysaudio Driver
49 */
50 /* DSP code and data images (1MiB) */
51 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
52 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
53 /* ADSC CPU PCM buffer (40KiB) */
54 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
55 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
56 /* ADSC AUX buffer (128KiB) */
57 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
58 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
59 /* ADSC Main buffer (128KiB) */
60 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
61 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
62
63 /*
64 * STAVEM driver/STAPI
65 */
66 /* 6MiB */
67 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1,
68 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
69
70 /*
71 * DOCSIS Subsystem
72 */
73 /* 7MiB */
74 PREALLOC_DOCSIS("Docsis", 0x27500000, 0x27c00000-1, IORESOURCE_MEM)
75
76 /*
77 * GHW HAL Driver
78 */
79 /* PowerTV Graphics Heap (14MiB) */
80 PREALLOC_NORMAL("GraphicsHeap", 0x26700000, 0x26700000+(14*1048576)-1,
81 IORESOURCE_MEM)
82
83 /*
84 * multi com buffer area
85 */
86 /* 128KiB */
87 PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1,
88 IORESOURCE_MEM)
89
90 /*
91 * DMA Ring buffer (don't need recording buffers)
92 */
93 /* 680KiB */
94 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
95 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
96
97 /*
98 * Display bins buffer for unit0
99 */
100 /* 4KiB */
101 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
102 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
103
104 /*
105 * AVFS: player HAL memory
106 */
107 /* 945K * 3 for playback */
108 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
109 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
110
111 /*
112 * PMEM
113 */
114 /* Persistent memory for diagnostics (64KiB) */
115 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
116 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
117
118 /*
119 * Smartcard
120 */
121 /* Read and write buffers for Internal/External cards (10KiB) */
122 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
123 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
124
125 /*
126 * NAND Flash
127 */
128 /* 10KiB */
129 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
130 IORESOURCE_MEM)
131
132 /*
133 * Synopsys GMAC Memory Region
134 */
135 /* 64KiB */
136 PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1,
137 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
138
139 /*
140 * TFTPBuffer
141 *
142 * This buffer is used in some minimal configurations (e.g. two-way
143 * loader) for storing software images
144 */
145 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
146 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
147
148 /*
149 * Add other resources here
150 */
151
152 /*
153 * End of Resource marker
154 */
155 {
156 .flags = 0,
157 },
158};
159
160
161struct resource non_dvr_vze_calliope_resources[] __initdata =
162{
163 /*
164 * VIDEO / LX1
165 */
166 /* Delta-Mu 1 image (2MiB) */
167 PREALLOC_NORMAL("ST231aImage", 0x22000000, 0x22200000-1,
168 IORESOURCE_MEM)
169 /* Delta-Mu 1 monitor (8KiB) */
170 PREALLOC_NORMAL("ST231aMonitor", 0x22200000, 0x22202000-1,
171 IORESOURCE_MEM)
172 /* Delta-Mu 1 RAM (10.12MiB) */
173 PREALLOC_NORMAL("MediaMemory1", 0x22202000, 0x22C20B85-1,
174 IORESOURCE_MEM)
175
176 /*
177 * Sysaudio Driver
178 */
179 /* DSP code and data images (1MiB) */
180 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
181 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
182 /* ADSC CPU PCM buffer (40KiB) */
183 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
184 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
185 /* ADSC AUX buffer (16KiB) */
186 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1,
187 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
188 /* ADSC Main buffer (16KiB) */
189 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1,
190 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
191
192 /*
193 * STAVEM driver/STAPI
194 */
195 /* 3.125MiB */
196 PREALLOC_NORMAL("AVMEMPartition0", 0x20396000, 0x206B6000-1,
197 IORESOURCE_MEM)
198
199 /*
200 * GHW HAL Driver
201 */
202 /* PowerTV Graphics Heap (2.59MiB) */
203 PREALLOC_NORMAL("GraphicsHeap", 0x20100000, 0x20396000-1,
204 IORESOURCE_MEM)
205
206 /*
207 * multi com buffer area
208 */
209 /* 128KiB */
210 PREALLOC_NORMAL("MulticomSHM", 0x206B6000, 0x206D6000-1,
211 IORESOURCE_MEM)
212
213 /*
214 * DMA Ring buffer (don't need recording buffers)
215 */
216 /* 680KiB */
217 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
218 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
219
220 /*
221 * Display bins buffer for unit0
222 */
223 /* 4KiB */
224 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
225 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
226
227 /*
228 * PMEM
229 */
230 /* Persistent memory for diagnostics (64KiB) */
231 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
232 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
233
234 /*
235 * Smartcard
236 */
237 /* Read and write buffers for Internal/External cards (10KiB) */
238 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
239 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
240
241 /*
242 * NAND Flash
243 */
244 /* 10KiB */
245 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
246 IORESOURCE_MEM)
247
248 /*
249 * Synopsys GMAC Memory Region
250 */
251 /* 64KiB */
252 PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1,
253 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
254
255 /*
256 * Add other resources here
257 */
258
259 /*
260 * End of Resource marker
261 */
262 {
263 .flags = 0,
264 },
265};
266
267struct resource non_dvr_vzf_calliope_resources[] __initdata =
268{
269 /*
270 * VIDEO / LX1
271 */
272 /* Delta-Mu 1 image (2MiB) */
273 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
274 IORESOURCE_MEM)
275 /* Delta-Mu 1 monitor (8KiB) */
276 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
277 IORESOURCE_MEM)
278 /* Delta-Mu 1 RAM (~19.4 (21.5MiB - (2MiB + 8KiB))) */
279 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x25580000-1,
280 IORESOURCE_MEM)
281
282 /*
283 * Sysaudio Driver
284 */
285 /* DSP code and data images (1MiB) */
286 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
287 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
288 /* ADSC CPU PCM buffer (40KiB) */
289 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
290 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
291 /* ADSC AUX buffer (128KiB) */
292 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
293 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
294 /* ADSC Main buffer (128KiB) */
295 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
296 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
297
298 /*
299 * STAVEM driver/STAPI
300 */
301 /* 4.5MiB */
302 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00480000-1,
303 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
304
305 /*
306 * GHW HAL Driver
307 */
308 /* PowerTV Graphics Heap (14MiB) */
309 PREALLOC_NORMAL("GraphicsHeap", 0x25600000, 0x25600000+(14*1048576)-1,
310 IORESOURCE_MEM)
311
312 /*
313 * multi com buffer area
314 */
315 /* 128KiB */
316 PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1,
317 IORESOURCE_MEM)
318
319 /*
320 * DMA Ring buffer (don't need recording buffers)
321 */
322 /* 680KiB */
323 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
324 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
325
326 /*
327 * Display bins buffer for unit0
328 */
329 /* 4KiB */
330 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
331 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
332
333 /*
334 * Display bins buffer for unit1
335 */
336 /* 4KiB */
337 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
338 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
339
340 /*
341 * AVFS: player HAL memory
342 */
343 /* 945K * 3 for playback */
344 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
345 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
346
347 /*
348 * PMEM
349 */
350 /* Persistent memory for diagnostics (64KiB) */
351 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
352 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
353
354 /*
355 * Smartcard
356 */
357 /* Read and write buffers for Internal/External cards (10KiB) */
358 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
359 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
360
361 /*
362 * NAND Flash
363 */
364 /* 10KiB */
365 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
366 IORESOURCE_MEM)
367
368 /*
369 * Synopsys GMAC Memory Region
370 */
371 /* 64KiB */
372 PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1,
373 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
374
375 /*
376 * Add other resources here
377 */
378
379 /*
380 * End of Resource marker
381 */
382 {
383 .flags = 0,
384 },
385};
diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c
deleted file mode 100644
index 7c6ce7596935..000000000000
--- a/arch/mips/powertv/asic/prealloc-cronus.c
+++ /dev/null
@@ -1,340 +0,0 @@
1/*
2 * Memory pre-allocations for Cronus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * DVR_CAPABLE CRONUS RESOURCES
31 */
32struct resource dvr_cronus_resources[] __initdata =
33{
34 /*
35 * VIDEO1 / LX1
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * VIDEO2 / LX2
49 */
50 /* Delta-Mu 2 image (2MiB) */
51 PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1,
52 IORESOURCE_MEM)
53 /* Delta-Mu 2 monitor (8KiB) */
54 PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1,
55 IORESOURCE_MEM)
56 /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
57 PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1,
58 IORESOURCE_MEM)
59
60 /*
61 * Sysaudio Driver
62 */
63 /* DSP code and data images (1MiB) */
64 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
65 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
66 /* ADSC CPU PCM buffer (40KiB) */
67 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
68 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
69 /* ADSC AUX buffer (128KiB) */
70 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
71 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
72 /* ADSC Main buffer (128KiB) */
73 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
74 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
75
76 /*
77 * STAVEM driver/STAPI
78 *
79 * This memory area is used for allocating buffers for Video decoding
80 * purposes. Allocation/De-allocation within this buffer is managed
81 * by the STAVMEM driver of the STAPI. They could be Decimated
82 * Picture Buffers, Intermediate Buffers, as deemed necessary for
83 * video decoding purposes, for any video decoders on Zeus.
84 */
85 /* 12MiB */
86 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1,
87 IORESOURCE_MEM)
88
89 /*
90 * DOCSIS Subsystem
91 */
92 /* 7MiB */
93 PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM)
94
95 /*
96 * GHW HAL Driver
97 */
98 /* PowerTV Graphics Heap (14MiB) */
99 PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1,
100 IORESOURCE_MEM)
101
102 /*
103 * multi com buffer area
104 */
105 /* 128KiB */
106 PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1,
107 IORESOURCE_MEM)
108
109 /*
110 * DMA Ring buffer
111 */
112 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x002EA000-1,
113 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
114
115 /*
116 * Display bins buffer for unit0
117 */
118 /* 4KiB */
119 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
120 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
121
122 /*
123 * Display bins buffer for unit1
124 */
125 /* 4KiB */
126 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
127 IORESOURCE_MEM)
128
129 /*
130 * ITFS
131 */
132 /* 815,104 bytes each for 2 ITFS partitions. */
133 PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, IORESOURCE_MEM)
134
135 /*
136 * AVFS
137 */
138 /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
139 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1,
140 IORESOURCE_MEM)
141
142 /* 4KiB */
143 PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1,
144 IORESOURCE_MEM)
145
146 /*
147 * PMEM
148 */
149 /* Persistent memory for diagnostics (64KiB) */
150 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
151 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
152
153 /*
154 * Smartcard
155 */
156 /* Read and write buffers for Internal/External cards (10KiB) */
157 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
158 IORESOURCE_MEM)
159
160 /*
161 * KAVNET
162 */
163 /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */
164 PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1,
165 IORESOURCE_MEM)
166 /* NP Image - must be video bank 1 (320KiB) */
167 PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM)
168 /* NP IPC - must be video bank 2 (512KiB) */
169 PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM)
170
171 /*
172 * TFTPBuffer
173 *
174 * This buffer is used in some minimal configurations (e.g. two-way
175 * loader) for storing software images
176 */
177 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
178 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
179
180 /*
181 * Add other resources here
182 */
183
184 /*
185 * End of Resource marker
186 */
187 {
188 .flags = 0,
189 },
190};
191
192/*
193 * NON_DVR_CAPABLE CRONUS RESOURCES
194 */
195struct resource non_dvr_cronus_resources[] __initdata =
196{
197 /*
198 * VIDEO1 / LX1
199 */
200 /* Delta-Mu 1 image (2MiB) */
201 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
202 IORESOURCE_MEM)
203 /* Delta-Mu 1 monitor (8KiB) */
204 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
205 IORESOURCE_MEM)
206 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
207 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1,
208 IORESOURCE_MEM)
209
210 /*
211 * VIDEO2 / LX2
212 */
213 /* Delta-Mu 2 image (2MiB) */
214 PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1,
215 IORESOURCE_MEM)
216 /* Delta-Mu 2 monitor (8KiB) */
217 PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1,
218 IORESOURCE_MEM)
219 /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
220 PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1,
221 IORESOURCE_MEM)
222
223 /*
224 * Sysaudio Driver
225 */
226 /* DSP code and data images (1MiB) */
227 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
228 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
229 /* ADSC CPU PCM buffer (40KiB) */
230 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
231 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
232 /* ADSC AUX buffer (128KiB) */
233 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
234 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
235 /* ADSC Main buffer (128KiB) */
236 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
237 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
238
239 /*
240 * STAVEM driver/STAPI
241 *
242 * This memory area is used for allocating buffers for Video decoding
243 * purposes. Allocation/De-allocation within this buffer is managed
244 * by the STAVMEM driver of the STAPI. They could be Decimated
245 * Picture Buffers, Intermediate Buffers, as deemed necessary for
246 * video decoding purposes, for any video decoders on Zeus.
247 */
248 /* 12MiB */
249 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1,
250 IORESOURCE_MEM)
251
252 /*
253 * DOCSIS Subsystem
254 */
255 /* 7MiB */
256 PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM)
257
258 /*
259 * GHW HAL Driver
260 */
261 /* PowerTV Graphics Heap (14MiB) */
262 PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1,
263 IORESOURCE_MEM)
264
265 /*
266 * multi com buffer area
267 */
268 /* 128KiB */
269 PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1,
270 IORESOURCE_MEM)
271
272 /*
273 * DMA Ring buffer (don't need recording buffers)
274 */
275 /* 680KiB */
276 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
277 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
278
279 /*
280 * Display bins buffer for unit0
281 */
282 /* 4KiB */
283 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
284 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
285
286 /*
287 * Display bins buffer for unit1
288 */
289 /* 4KiB */
290 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
291 IORESOURCE_MEM)
292
293 /*
294 * AVFS: player HAL memory
295 */
296 /* 945K * 3 for playback */
297 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, IORESOURCE_MEM)
298
299 /*
300 * PMEM
301 */
302 /* Persistent memory for diagnostics (64KiB) */
303 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
304 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
305
306 /*
307 * Smartcard
308 */
309 /* Read and write buffers for Internal/External cards (10KiB) */
310 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM)
311
312 /*
313 * KAVNET
314 */
315 /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */
316 PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1,
317 IORESOURCE_MEM)
318 /* NP Image - must be video bank 1 (320KiB) */
319 PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM)
320 /* NP IPC - must be video bank 2 (512KiB) */
321 PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM)
322
323 /*
324 * NAND Flash
325 */
326 /* 10KiB */
327 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
328 IORESOURCE_MEM)
329
330 /*
331 * Add other resources here
332 */
333
334 /*
335 * End of Resource marker
336 */
337 {
338 .flags = 0,
339 },
340};
diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c
deleted file mode 100644
index a7937ba7b4c0..000000000000
--- a/arch/mips/powertv/asic/prealloc-cronuslite.c
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 * Memory pre-allocations for Cronus Lite boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * NON_DVR_CAPABLE CRONUSLITE RESOURCES
31 */
32struct resource non_dvr_cronuslite_resources[] __initdata =
33{
34 /*
35 * VIDEO2 / LX2
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x60000000, 0x60200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x60200000, 0x60202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x60202000, 0x62000000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * Sysaudio Driver
49 */
50 /* DSP code and data images (1MiB) */
51 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
52 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
53 /* ADSC CPU PCM buffer (40KiB) */
54 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
55 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
56 /* ADSC AUX buffer (128KiB) */
57 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
58 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
59 /* ADSC Main buffer (128KiB) */
60 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
61 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
62
63 /*
64 * STAVEM driver/STAPI
65 *
66 * This memory area is used for allocating buffers for Video decoding
67 * purposes. Allocation/De-allocation within this buffer is managed
68 * by the STAVMEM driver of the STAPI. They could be Decimated
69 * Picture Buffers, Intermediate Buffers, as deemed necessary for
70 * video decoding purposes, for any video decoders on Zeus.
71 */
72 /* 6MiB */
73 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1,
74 IORESOURCE_MEM)
75
76 /*
77 * DOCSIS Subsystem
78 */
79 /* 7MiB */
80 PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM)
81
82 /*
83 * GHW HAL Driver
84 */
85 /* PowerTV Graphics Heap (14MiB) */
86 PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1,
87 IORESOURCE_MEM)
88
89 /*
90 * multi com buffer area
91 */
92 /* 128KiB */
93 PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1,
94 IORESOURCE_MEM)
95
96 /*
97 * DMA Ring buffer (don't need recording buffers)
98 */
99 /* 680KiB */
100 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
101 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
102
103 /*
104 * Display bins buffer for unit0
105 */
106 /* 4KiB */
107 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
108 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
109
110 /*
111 * Display bins buffer for unit1
112 */
113 /* 4KiB */
114 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
115 IORESOURCE_MEM)
116
117 /*
118 * AVFS: player HAL memory
119 */
120 /* 945K * 3 for playback */
121 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
122 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
123
124 /*
125 * PMEM
126 */
127 /* Persistent memory for diagnostics (64KiB) */
128 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
129 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
130
131 /*
132 * Smartcard
133 */
134 /* Read and write buffers for Internal/External cards (10KiB) */
135 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM)
136
137 /*
138 * KAVNET
139 */
140 /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */
141 PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1,
142 IORESOURCE_MEM)
143 /* NP Image - must be video bank 1 (320KiB) */
144 PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM)
145 /* NP IPC - must be video bank 2 (512KiB) */
146 PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM)
147
148 /*
149 * NAND Flash
150 */
151 /* 10KiB */
152 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
153 IORESOURCE_MEM)
154
155 /*
156 * TFTPBuffer
157 *
158 * This buffer is used in some minimal configurations (e.g. two-way
159 * loader) for storing software images
160 */
161 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
162 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
163
164 /*
165 * Add other resources here
166 */
167
168 /*
169 * End of Resource marker
170 */
171 {
172 .flags = 0,
173 },
174};
diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c
deleted file mode 100644
index 2303bbfe6b82..000000000000
--- a/arch/mips/powertv/asic/prealloc-gaia.c
+++ /dev/null
@@ -1,589 +0,0 @@
1/*
2 * Memory pre-allocations for Gaia boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#include <linux/init.h>
24#include <asm/mach-powertv/asic.h>
25
26/*
27 * DVR_CAPABLE GAIA RESOURCES
28 */
29struct resource dvr_gaia_resources[] __initdata = {
30 /*
31 *
32 * VIDEO1 / LX1
33 *
34 */
35 {
36 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
37 .start = 0x24000000,
38 .end = 0x241FFFFF, /* 2MiB */
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
43 .start = 0x24200000,
44 .end = 0x24201FFF,
45 .flags = IORESOURCE_MEM,
46 },
47 {
48 .name = "MediaMemory1",
49 .start = 0x24202000,
50 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
51 .flags = IORESOURCE_MEM,
52 },
53 /*
54 *
55 * VIDEO2 / LX2
56 *
57 */
58 {
59 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
60 .start = 0x60000000,
61 .end = 0x601FFFFF, /* 2MiB */
62 .flags = IORESOURCE_IO,
63 },
64 {
65 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
66 .start = 0x60200000,
67 .end = 0x60201FFF,
68 .flags = IORESOURCE_IO,
69 },
70 {
71 .name = "MediaMemory2",
72 .start = 0x60202000,
73 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
74 .flags = IORESOURCE_IO,
75 },
76 /*
77 *
78 * Sysaudio Driver
79 *
80 * This driver requires:
81 *
82 * Arbitrary Based Buffers:
83 * DSP_Image_Buff - DSP code and data images (1MB)
84 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
85 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
86 * ADSC_Main_Buff - ADSC Main buffer (16KB)
87 *
88 */
89 {
90 .name = "DSP_Image_Buff",
91 .start = 0x00000000,
92 .end = 0x000FFFFF,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .name = "ADSC_CPU_PCM_Buff",
97 .start = 0x00000000,
98 .end = 0x00009FFF,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .name = "ADSC_AUX_Buff",
103 .start = 0x00000000,
104 .end = 0x00003FFF,
105 .flags = IORESOURCE_MEM,
106 },
107 {
108 .name = "ADSC_Main_Buff",
109 .start = 0x00000000,
110 .end = 0x00003FFF,
111 .flags = IORESOURCE_MEM,
112 },
113 /*
114 *
115 * STAVEM driver/STAPI
116 *
117 * This driver requires:
118 *
119 * Arbitrary Based Buffers:
120 * This memory area is used for allocating buffers for Video decoding
121 * purposes. Allocation/De-allocation within this buffer is managed
122 * by the STAVMEM driver of the STAPI. They could be Decimated
123 * Picture Buffers, Intermediate Buffers, as deemed necessary for
124 * video decoding purposes, for any video decoders on Zeus.
125 *
126 */
127 {
128 .name = "AVMEMPartition0",
129 .start = 0x63580000,
130 .end = 0x64180000 - 1, /* 12 MB total */
131 .flags = IORESOURCE_IO,
132 },
133 /*
134 *
135 * DOCSIS Subsystem
136 *
137 * This driver requires:
138 *
139 * Arbitrary Based Buffers:
140 * Docsis -
141 *
142 */
143 {
144 .name = "Docsis",
145 .start = 0x62000000,
146 .end = 0x62700000 - 1, /* 7 MB total */
147 .flags = IORESOURCE_IO,
148 },
149 /*
150 *
151 * GHW HAL Driver
152 *
153 * This driver requires:
154 *
155 * Arbitrary Based Buffers:
156 * GraphicsHeap - PowerTV Graphics Heap
157 *
158 */
159 {
160 .name = "GraphicsHeap",
161 .start = 0x62700000,
162 .end = 0x63500000 - 1, /* 14 MB total */
163 .flags = IORESOURCE_IO,
164 },
165 /*
166 *
167 * multi com buffer area
168 *
169 * This driver requires:
170 *
171 * Arbitrary Based Buffers:
172 * Docsis -
173 *
174 */
175 {
176 .name = "MulticomSHM",
177 .start = 0x26000000,
178 .end = 0x26020000 - 1,
179 .flags = IORESOURCE_MEM,
180 },
181 /*
182 *
183 * DMA Ring buffer
184 *
185 * This driver requires:
186 *
187 * Arbitrary Based Buffers:
188 * Docsis -
189 *
190 */
191 {
192 .name = "BMM_Buffer",
193 .start = 0x00000000,
194 .end = 0x00280000 - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 /*
198 *
199 * Display bins buffer for unit0
200 *
201 * This driver requires:
202 *
203 * Arbitrary Based Buffers:
204 * Display Bins for unit0
205 *
206 */
207 {
208 .name = "DisplayBins0",
209 .start = 0x00000000,
210 .end = 0x00000FFF, /* 4 KB total */
211 .flags = IORESOURCE_MEM,
212 },
213 /*
214 *
215 * Display bins buffer
216 *
217 * This driver requires:
218 *
219 * Arbitrary Based Buffers:
220 * Display Bins for unit1
221 *
222 */
223 {
224 .name = "DisplayBins1",
225 .start = 0x64AD4000,
226 .end = 0x64AD5000 - 1, /* 4 KB total */
227 .flags = IORESOURCE_IO,
228 },
229 /*
230 *
231 * ITFS
232 *
233 * This driver requires:
234 *
235 * Arbitrary Based Buffers:
236 * Docsis -
237 *
238 */
239 {
240 .name = "ITFS",
241 .start = 0x64180000,
242 /* 815,104 bytes each for 2 ITFS partitions. */
243 .end = 0x6430DFFF,
244 .flags = IORESOURCE_IO,
245 },
246 /*
247 *
248 * AVFS
249 *
250 * This driver requires:
251 *
252 * Arbitrary Based Buffers:
253 * Docsis -
254 *
255 */
256 {
257 .name = "AvfsDmaMem",
258 .start = 0x6430E000,
259 /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
260 .end = 0x64AD0000 - 1,
261 .flags = IORESOURCE_IO,
262 },
263 {
264 .name = "AvfsFileSys",
265 .start = 0x64AD0000,
266 .end = 0x64AD1000 - 1, /* 4K */
267 .flags = IORESOURCE_IO,
268 },
269 /*
270 *
271 * Smartcard
272 *
273 * This driver requires:
274 *
275 * Arbitrary Based Buffers:
276 * Read and write buffers for Internal/External cards
277 *
278 */
279 {
280 .name = "SmartCardInfo",
281 .start = 0x64AD1000,
282 .end = 0x64AD3800 - 1,
283 .flags = IORESOURCE_IO,
284 },
285 /*
286 *
287 * KAVNET
288 * NP Reset Vector - must be of the form xxCxxxxx
289 * NP Image - must be video bank 1
290 * NP IPC - must be video bank 2
291 */
292 {
293 .name = "NP_Reset_Vector",
294 .start = 0x27c00000,
295 .end = 0x27c01000 - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .name = "NP_Image",
300 .start = 0x27020000,
301 .end = 0x27060000 - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .name = "NP_IPC",
306 .start = 0x63500000,
307 .end = 0x63580000 - 1,
308 .flags = IORESOURCE_IO,
309 },
310 /*
311 * Add other resources here
312 */
313 { },
314};
315
316/*
317 * NON_DVR_CAPABLE GAIA RESOURCES
318 */
319struct resource non_dvr_gaia_resources[] __initdata = {
320 /*
321 *
322 * VIDEO1 / LX1
323 *
324 */
325 {
326 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
327 .start = 0x24000000,
328 .end = 0x241FFFFF, /* 2MiB */
329 .flags = IORESOURCE_MEM,
330 },
331 {
332 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
333 .start = 0x24200000,
334 .end = 0x24201FFF,
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 .name = "MediaMemory1",
339 .start = 0x24202000,
340 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
341 .flags = IORESOURCE_MEM,
342 },
343 /*
344 *
345 * VIDEO2 / LX2
346 *
347 */
348 {
349 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
350 .start = 0x60000000,
351 .end = 0x601FFFFF, /* 2MiB */
352 .flags = IORESOURCE_IO,
353 },
354 {
355 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
356 .start = 0x60200000,
357 .end = 0x60201FFF,
358 .flags = IORESOURCE_IO,
359 },
360 {
361 .name = "MediaMemory2",
362 .start = 0x60202000,
363 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
364 .flags = IORESOURCE_IO,
365 },
366 /*
367 *
368 * Sysaudio Driver
369 *
370 * This driver requires:
371 *
372 * Arbitrary Based Buffers:
373 * DSP_Image_Buff - DSP code and data images (1MB)
374 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
375 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
376 * ADSC_Main_Buff - ADSC Main buffer (16KB)
377 *
378 */
379 {
380 .name = "DSP_Image_Buff",
381 .start = 0x00000000,
382 .end = 0x000FFFFF,
383 .flags = IORESOURCE_MEM,
384 },
385 {
386 .name = "ADSC_CPU_PCM_Buff",
387 .start = 0x00000000,
388 .end = 0x00009FFF,
389 .flags = IORESOURCE_MEM,
390 },
391 {
392 .name = "ADSC_AUX_Buff",
393 .start = 0x00000000,
394 .end = 0x00003FFF,
395 .flags = IORESOURCE_MEM,
396 },
397 {
398 .name = "ADSC_Main_Buff",
399 .start = 0x00000000,
400 .end = 0x00003FFF,
401 .flags = IORESOURCE_MEM,
402 },
403 /*
404 *
405 * STAVEM driver/STAPI
406 *
407 * This driver requires:
408 *
409 * Arbitrary Based Buffers:
410 * This memory area is used for allocating buffers for Video decoding
411 * purposes. Allocation/De-allocation within this buffer is managed
412 * by the STAVMEM driver of the STAPI. They could be Decimated
413 * Picture Buffers, Intermediate Buffers, as deemed necessary for
414 * video decoding purposes, for any video decoders on Zeus.
415 *
416 */
417 {
418 .name = "AVMEMPartition0",
419 .start = 0x63580000,
420 .end = 0x64180000 - 1, /* 12 MB total */
421 .flags = IORESOURCE_IO,
422 },
423 /*
424 *
425 * DOCSIS Subsystem
426 *
427 * This driver requires:
428 *
429 * Arbitrary Based Buffers:
430 * Docsis -
431 *
432 */
433 {
434 .name = "Docsis",
435 .start = 0x62000000,
436 .end = 0x62700000 - 1, /* 7 MB total */
437 .flags = IORESOURCE_IO,
438 },
439 /*
440 *
441 * GHW HAL Driver
442 *
443 * This driver requires:
444 *
445 * Arbitrary Based Buffers:
446 * GraphicsHeap - PowerTV Graphics Heap
447 *
448 */
449 {
450 .name = "GraphicsHeap",
451 .start = 0x62700000,
452 .end = 0x63500000 - 1, /* 14 MB total */
453 .flags = IORESOURCE_IO,
454 },
455 /*
456 *
457 * multi com buffer area
458 *
459 * This driver requires:
460 *
461 * Arbitrary Based Buffers:
462 * Docsis -
463 *
464 */
465 {
466 .name = "MulticomSHM",
467 .start = 0x26000000,
468 .end = 0x26020000 - 1,
469 .flags = IORESOURCE_MEM,
470 },
471 /*
472 *
473 * DMA Ring buffer
474 *
475 * This driver requires:
476 *
477 * Arbitrary Based Buffers:
478 * Docsis -
479 *
480 */
481 {
482 .name = "BMM_Buffer",
483 .start = 0x00000000,
484 .end = 0x000AA000 - 1,
485 .flags = IORESOURCE_MEM,
486 },
487 /*
488 *
489 * Display bins buffer for unit0
490 *
491 * This driver requires:
492 *
493 * Arbitrary Based Buffers:
494 * Display Bins for unit0
495 *
496 */
497 {
498 .name = "DisplayBins0",
499 .start = 0x00000000,
500 .end = 0x00000FFF, /* 4 KB total */
501 .flags = IORESOURCE_MEM,
502 },
503 /*
504 *
505 * Display bins buffer
506 *
507 * This driver requires:
508 *
509 * Arbitrary Based Buffers:
510 * Display Bins for unit1
511 *
512 */
513 {
514 .name = "DisplayBins1",
515 .start = 0x64AD4000,
516 .end = 0x64AD5000 - 1, /* 4 KB total */
517 .flags = IORESOURCE_IO,
518 },
519 /*
520 *
521 * AVFS: player HAL memory
522 *
523 *
524 */
525 {
526 .name = "AvfsDmaMem",
527 .start = 0x6430E000,
528 .end = 0x645D2C00 - 1, /* 945K * 3 for playback */
529 .flags = IORESOURCE_IO,
530 },
531 /*
532 *
533 * PMEM
534 *
535 * This driver requires:
536 *
537 * Arbitrary Based Buffers:
538 * Persistent memory for diagnostics.
539 *
540 */
541 {
542 .name = "DiagPersistentMemory",
543 .start = 0x00000000,
544 .end = 0x10000 - 1,
545 .flags = IORESOURCE_MEM,
546 },
547 /*
548 *
549 * Smartcard
550 *
551 * This driver requires:
552 *
553 * Arbitrary Based Buffers:
554 * Read and write buffers for Internal/External cards
555 *
556 */
557 {
558 .name = "SmartCardInfo",
559 .start = 0x64AD1000,
560 .end = 0x64AD3800 - 1,
561 .flags = IORESOURCE_IO,
562 },
563 /*
564 *
565 * KAVNET
566 * NP Reset Vector - must be of the form xxCxxxxx
567 * NP Image - must be video bank 1
568 * NP IPC - must be video bank 2
569 */
570 {
571 .name = "NP_Reset_Vector",
572 .start = 0x27c00000,
573 .end = 0x27c01000 - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .name = "NP_Image",
578 .start = 0x27020000,
579 .end = 0x27060000 - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .name = "NP_IPC",
584 .start = 0x63500000,
585 .end = 0x63580000 - 1,
586 .flags = IORESOURCE_IO,
587 },
588 { },
589};
diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c
deleted file mode 100644
index 6e76f09c68d6..000000000000
--- a/arch/mips/powertv/asic/prealloc-zeus.c
+++ /dev/null
@@ -1,304 +0,0 @@
1/*
2 * Memory pre-allocations for Zeus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * DVR_CAPABLE RESOURCES
31 */
32struct resource dvr_zeus_resources[] __initdata =
33{
34 /*
35 * VIDEO1 / LX1
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * VIDEO2 / LX2
49 */
50 /* Delta-Mu 2 image (2MiB) */
51 PREALLOC_NORMAL("ST231bImage", 0x30000000, 0x30200000-1,
52 IORESOURCE_MEM)
53 /* Delta-Mu 2 monitor (8KiB) */
54 PREALLOC_NORMAL("ST231bMonitor", 0x30200000, 0x30202000-1,
55 IORESOURCE_MEM)
56 /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
57 PREALLOC_NORMAL("MediaMemory2", 0x30202000, 0x32000000-1,
58 IORESOURCE_MEM)
59
60 /*
61 * Sysaudio Driver
62 */
63 /* DSP code and data images (1MiB) */
64 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
65 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
66 /* ADSC CPU PCM buffer (40KiB) */
67 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
68 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
69 /* ADSC AUX buffer (16KiB) */
70 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1,
71 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
72 /* ADSC Main buffer (16KiB) */
73 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1,
74 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
75
76 /*
77 * STAVEM driver/STAPI
78 *
79 * This memory area is used for allocating buffers for Video decoding
80 * purposes. Allocation/De-allocation within this buffer is managed
81 * by the STAVMEM driver of the STAPI. They could be Decimated
82 * Picture Buffers, Intermediate Buffers, as deemed necessary for
83 * video decoding purposes, for any video decoders on Zeus.
84 */
85 /* 12MiB */
86 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1,
87 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
88
89 /*
90 * DOCSIS Subsystem
91 */
92 /* 7MiB */
93 PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM)
94
95 /*
96 * GHW HAL Driver
97 */
98 /* PowerTV Graphics Heap (14MiB) */
99 PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1,
100 IORESOURCE_MEM)
101
102 /*
103 * multi com buffer area
104 */
105 /* 128KiB */
106 PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1,
107 IORESOURCE_MEM)
108
109 /*
110 * DMA Ring buffer
111 */
112 /* 2.5MiB */
113 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1,
114 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
115
116 /*
117 * Display bins buffer for unit0
118 */
119 /* 4KiB */
120 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
121 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
122
123 /*
124 * Display bins buffer for unit1
125 */
126 /* 4KiB */
127 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
128 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
129
130 /*
131 * ITFS
132 */
133 /* 815,104 bytes each for 2 ITFS partitions. */
134 PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1,
135 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
136
137 /*
138 * AVFS
139 */
140 /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
141 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1,
142 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
143 /* 4KiB */
144 PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1,
145 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
146
147 /*
148 * PMEM
149 */
150 /* Persistent memory for diagnostics (64KiB) */
151 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
152 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
153
154 /*
155 * Smartcard
156 */
157 /* Read and write buffers for Internal/External cards (10KiB) */
158 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
159 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
160
161 /*
162 * TFTPBuffer
163 *
164 * This buffer is used in some minimal configurations (e.g. two-way
165 * loader) for storing software images
166 */
167 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
168 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
169
170 /*
171 * Add other resources here
172 */
173
174 /*
175 * End of Resource marker
176 */
177 {
178 .flags = 0,
179 },
180};
181
182/*
183 * NON_DVR_CAPABLE ZEUS RESOURCES
184 */
185struct resource non_dvr_zeus_resources[] __initdata =
186{
187 /*
188 * VIDEO1 / LX1
189 */
190 /* Delta-Mu 1 image (2MiB) */
191 PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1,
192 IORESOURCE_MEM)
193 /* Delta-Mu 1 monitor (8KiB) */
194 PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1,
195 IORESOURCE_MEM)
196 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
197 PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1,
198 IORESOURCE_MEM)
199
200 /*
201 * Sysaudio Driver
202 */
203 /* DSP code and data images (1MiB) */
204 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
205 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
206 /* ADSC CPU PCM buffer (40KiB) */
207 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
208 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
209 /* ADSC AUX buffer (16KiB) */
210 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1,
211 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
212 /* ADSC Main buffer (16KiB) */
213 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1,
214 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
215
216 /*
217 * STAVEM driver/STAPI
218 */
219 /* 6MiB */
220 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1,
221 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
222
223 /*
224 * DOCSIS Subsystem
225 */
226 /* 7MiB */
227 PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM)
228
229 /*
230 * GHW HAL Driver
231 */
232 /* PowerTV Graphics Heap (14MiB) */
233 PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1,
234 IORESOURCE_MEM)
235
236 /*
237 * multi com buffer area
238 */
239 /* 128KiB */
240 PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1,
241 IORESOURCE_MEM)
242
243 /*
244 * DMA Ring buffer
245 */
246 /* 2.5MiB */
247 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1,
248 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
249
250 /*
251 * Display bins buffer for unit0
252 */
253 /* 4KiB */
254 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
255 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
256
257 /*
258 * AVFS: player HAL memory
259 */
260 /* 945K * 3 for playback */
261 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
262 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
263
264 /*
265 * PMEM
266 */
267 /* Persistent memory for diagnostics (64KiB) */
268 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
269 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
270
271 /*
272 * Smartcard
273 */
274 /* Read and write buffers for Internal/External cards (10KiB) */
275 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
276 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
277
278 /*
279 * NAND Flash
280 */
281 /* 10KiB */
282 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
283 IORESOURCE_MEM)
284
285 /*
286 * TFTPBuffer
287 *
288 * This buffer is used in some minimal configurations (e.g. two-way
289 * loader) for storing software images
290 */
291 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
292 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
293
294 /*
295 * Add other resources here
296 */
297
298 /*
299 * End of Resource marker
300 */
301 {
302 .flags = 0,
303 },
304};
diff --git a/arch/mips/powertv/asic/prealloc.h b/arch/mips/powertv/asic/prealloc.h
deleted file mode 100644
index 8e682df17856..000000000000
--- a/arch/mips/powertv/asic/prealloc.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * Definitions for memory preallocations
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#ifndef _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H
22#define _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H
23
24#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */
25#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
26
27/* "struct resource" array element definition */
28#define PREALLOC(NAME, START, END, FLAGS) { \
29 .name = (NAME), \
30 .start = (START), \
31 .end = (END), \
32 .flags = (FLAGS) \
33 },
34
35/* Individual resources in the preallocated resource arrays are defined using
36 * macros. These macros are conditionally defined based on their
37 * corresponding kernel configuration flag:
38 * - CONFIG_PREALLOC_NORMAL: preallocate resources for a normal settop box
39 * - CONFIG_PREALLOC_TFTP: preallocate the TFTP download resource
40 * - CONFIG_PREALLOC_DOCSIS: preallocate the DOCSIS resource
41 * - CONFIG_PREALLOC_PMEM: reserve space for persistent memory
42 */
43#ifdef CONFIG_PREALLOC_NORMAL
44#define PREALLOC_NORMAL(name, start, end, flags) \
45 PREALLOC(name, start, end, flags)
46#else
47#define PREALLOC_NORMAL(name, start, end, flags)
48#endif
49
50#ifdef CONFIG_PREALLOC_TFTP
51#define PREALLOC_TFTP(name, start, end, flags) \
52 PREALLOC(name, start, end, flags)
53#else
54#define PREALLOC_TFTP(name, start, end, flags)
55#endif
56
57#ifdef CONFIG_PREALLOC_DOCSIS
58#define PREALLOC_DOCSIS(name, start, end, flags) \
59 PREALLOC(name, start, end, flags)
60#else
61#define PREALLOC_DOCSIS(name, start, end, flags)
62#endif
63
64#ifdef CONFIG_PREALLOC_PMEM
65#define PREALLOC_PMEM(name, start, end, flags) \
66 PREALLOC(name, start, end, flags)
67#else
68#define PREALLOC_PMEM(name, start, end, flags)
69#endif
70#endif
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
deleted file mode 100644
index 498926377e51..000000000000
--- a/arch/mips/powertv/init.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * PROM library initialisation code.
22 */
23#include <linux/init.h>
24#include <linux/string.h>
25#include <linux/kernel.h>
26
27#include <asm/bootinfo.h>
28#include <linux/io.h>
29#include <asm/cacheflush.h>
30#include <asm/traps.h>
31
32#include <asm/mips-boards/generic.h>
33#include <asm/mach-powertv/asic.h>
34
35#include "init.h"
36
37static int *_prom_envp;
38unsigned long _prom_memsize;
39
40/*
41 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
42 * This macro take care of sign extension, if running in 64-bit mode.
43 */
44#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
45
46char *prom_getenv(char *envname)
47{
48 char *result = NULL;
49
50 if (_prom_envp != NULL) {
51 /*
52 * Return a pointer to the given environment variable.
53 * In 64-bit mode: we're using 64-bit pointers, but all pointers
54 * in the PROM structures are only 32-bit, so we need some
55 * workarounds, if we are running in 64-bit mode.
56 */
57 int i, index = 0;
58
59 i = strlen(envname);
60
61 while (prom_envp(index)) {
62 if (strncmp(envname, prom_envp(index), i) == 0) {
63 result = prom_envp(index + 1);
64 break;
65 }
66 index += 2;
67 }
68 }
69
70 return result;
71}
72
73void __init prom_init(void)
74{
75 int prom_argc;
76 char *prom_argv;
77
78 prom_argc = fw_arg0;
79 prom_argv = (char *) fw_arg1;
80 _prom_envp = (int *) fw_arg2;
81 _prom_memsize = (unsigned long) fw_arg3;
82
83 if (prom_argc == 1) {
84 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
85 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
86 }
87
88 configure_platform();
89 prom_meminit();
90}
diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h
deleted file mode 100644
index c1a8bd0dbe4b..000000000000
--- a/arch/mips/powertv/init.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Definitions from powertv init.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_INIT_H
24#define _POWERTV_INIT_H
25extern unsigned long _prom_memsize;
26extern void prom_meminit(void);
27extern char *prom_getenv(char *name);
28#endif
diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c
deleted file mode 100644
index d060478aab03..000000000000
--- a/arch/mips/powertv/ioremap.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * ioremap.c
3 *
4 * Support for mapping between dma_addr_t values a phys_addr_t values.
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 * Author: David VomLehn <dvomlehn@cisco.com>
23 *
24 * Description: Defines the platform resources for the SA settop.
25 *
26 * NOTE: The bootloader allocates persistent memory at an address which is
27 * 16 MiB below the end of the highest address in KSEG0. All fixed
28 * address memory reservations must avoid this region.
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33
34#include <asm/mach-powertv/ioremap.h>
35
36/*
37 * Define the sizes of and masks for grains in physical and DMA space. The
38 * values are the same but the types are not.
39 */
40#define IOR_PHYS_GRAIN ((phys_addr_t) 1 << IOR_LSBITS)
41#define IOR_PHYS_GRAIN_MASK (IOR_PHYS_GRAIN - 1)
42
43#define IOR_DMA_GRAIN ((dma_addr_t) 1 << IOR_LSBITS)
44#define IOR_DMA_GRAIN_MASK (IOR_DMA_GRAIN - 1)
45
46/*
47 * Values that, when accessed by an index derived from a phys_addr_t and
48 * added to phys_addr_t value, yield a DMA address
49 */
50struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
51EXPORT_SYMBOL(_ior_phys_to_dma);
52
53/*
54 * Values that, when accessed by an index derived from a dma_addr_t and
55 * added to that dma_addr_t value, yield a physical address
56 */
57struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
58EXPORT_SYMBOL(_ior_dma_to_phys);
59
60/**
61 * setup_dma_to_phys - set up conversion from DMA to physical addresses
62 * @dma_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index
63 * into the array _dma_to_phys.
64 * @delta: Value that, when added to the DMA address, will yield the
65 * physical address
66 * @s: Number of bytes in the section of memory with the given delta
67 * between DMA and physical addresses.
68 */
69static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s)
70{
71 int dma_idx, first_idx, last_idx;
72 phys_addr_t first, last;
73
74 /*
75 * Calculate the first and last indices, rounding the first up and
76 * the second down.
77 */
78 first = dma & ~IOR_DMA_GRAIN_MASK;
79 last = (dma + s - 1) & ~IOR_DMA_GRAIN_MASK;
80 first_idx = first >> IOR_LSBITS; /* Convert to indices */
81 last_idx = last >> IOR_LSBITS;
82
83 for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++)
84 _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT;
85}
86
87/**
88 * setup_phys_to_dma - set up conversion from DMA to physical addresses
89 * @phys_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index
90 * into the array _phys_to_dma.
91 * @delta: Value that, when added to the DMA address, will yield the
92 * physical address
93 * @s: Number of bytes in the section of memory with the given delta
94 * between DMA and physical addresses.
95 */
96static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s)
97{
98 int phys_idx, first_idx, last_idx;
99 phys_addr_t first, last;
100
101 /*
102 * Calculate the first and last indices, rounding the first up and
103 * the second down.
104 */
105 first = phys & ~IOR_PHYS_GRAIN_MASK;
106 last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK;
107 first_idx = first >> IOR_LSBITS; /* Convert to indices */
108 last_idx = last >> IOR_LSBITS;
109
110 for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++)
111 _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT;
112}
113
114/**
115 * ioremap_add_map - add to the physical and DMA address conversion arrays
116 * @phys: Process's view of the address of the start of the memory chunk
117 * @dma: DMA address of the start of the memory chunk
118 * @size: Size, in bytes, of the chunk of memory
119 *
120 * NOTE: It might be obvious, but the assumption is that all @size bytes have
121 * the same offset between the physical address and the DMA address.
122 */
123void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size)
124{
125 if (size == 0)
126 return;
127
128 if ((dma & IOR_DMA_GRAIN_MASK) != 0 ||
129 (phys & IOR_PHYS_GRAIN_MASK) != 0 ||
130 (size & IOR_PHYS_GRAIN_MASK) != 0)
131 pr_crit("Memory allocation must be in chunks of 0x%x bytes\n",
132 IOR_PHYS_GRAIN);
133
134 setup_dma_to_phys(dma, phys - dma, size);
135 setup_phys_to_dma(phys, dma - phys, size);
136}
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
deleted file mode 100644
index bc2f3ca22b41..000000000000
--- a/arch/mips/powertv/memory.c
+++ /dev/null
@@ -1,353 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Apparently originally from arch/mips/malta-memory.c. Modified to work
20 * with the PowerTV bootloader.
21 */
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/bootmem.h>
25#include <linux/pfn.h>
26#include <linux/string.h>
27
28#include <asm/bootinfo.h>
29#include <asm/page.h>
30#include <asm/sections.h>
31
32#include <asm/mach-powertv/asic.h>
33#include <asm/mach-powertv/ioremap.h>
34
35#include "init.h"
36
37/* Memory constants */
38#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */
39#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
40#define DEFAULT_MEMSIZE MEBIBYTE(128) /* If no memsize provided */
41
42#define BLDR_SIZE KIBIBYTE(256) /* Memory reserved for bldr */
43#define RV_SIZE MEBIBYTE(4) /* Size of reset vector */
44
45#define LOW_MEM_END 0x20000000 /* Highest low memory address */
46#define BLDR_ALIAS 0x10000000 /* Bootloader address */
47#define RV_PHYS 0x1fc00000 /* Reset vector address */
48#define LOW_RAM_END RV_PHYS /* End of real RAM in low mem */
49
50/*
51 * Very low-level conversion from processor physical address to device
52 * DMA address for the first bank of memory.
53 */
54#define PHYS_TO_DMA(paddr) ((paddr) + (CONFIG_LOW_RAM_DMA - LOW_RAM_ALIAS))
55
56unsigned long ptv_memsize;
57
58/*
59 * struct low_mem_reserved - Items in low memory that are reserved
60 * @start: Physical address of item
61 * @size: Size, in bytes, of this item
62 * @is_aliased: True if this is RAM aliased from another location. If false,
63 * it is something other than aliased RAM and the RAM in the
64 * unaliased address is still visible outside of low memory.
65 */
66struct low_mem_reserved {
67 phys_addr_t start;
68 phys_addr_t size;
69 bool is_aliased;
70};
71
72/*
73 * Must be in ascending address order
74 */
75struct low_mem_reserved low_mem_reserved[] = {
76 {BLDR_ALIAS, BLDR_SIZE, true}, /* Bootloader RAM */
77 {RV_PHYS, RV_SIZE, false}, /* Reset vector */
78};
79
80/*
81 * struct mem_layout - layout of a piece of the system RAM
82 * @phys: Physical address of the start of this piece of RAM. This is the
83 * address at which both the processor and I/O devices see the
84 * RAM.
85 * @alias: Alias of this piece of memory in order to make it appear in
86 * the low memory part of the processor's address space. I/O
87 * devices don't see anything here.
88 * @size: Size, in bytes, of this piece of RAM
89 */
90struct mem_layout {
91 phys_addr_t phys;
92 phys_addr_t alias;
93 phys_addr_t size;
94};
95
96/*
97 * struct mem_layout_list - list descriptor for layouts of system RAM pieces
98 * @family: Specifies the family being described
99 * @n: Number of &struct mem_layout elements
100 * @layout: Pointer to the list of &mem_layout structures
101 */
102struct mem_layout_list {
103 enum family_type family;
104 size_t n;
105 struct mem_layout *layout;
106};
107
108static struct mem_layout f1500_layout[] = {
109 {0x20000000, 0x10000000, MEBIBYTE(256)},
110};
111
112static struct mem_layout f4500_layout[] = {
113 {0x40000000, 0x10000000, MEBIBYTE(256)},
114 {0x20000000, 0x20000000, MEBIBYTE(32)},
115};
116
117static struct mem_layout f8500_layout[] = {
118 {0x40000000, 0x10000000, MEBIBYTE(256)},
119 {0x20000000, 0x20000000, MEBIBYTE(32)},
120 {0x30000000, 0x30000000, MEBIBYTE(32)},
121};
122
123static struct mem_layout fx600_layout[] = {
124 {0x20000000, 0x10000000, MEBIBYTE(256)},
125 {0x60000000, 0x60000000, MEBIBYTE(128)},
126};
127
128static struct mem_layout_list layout_list[] = {
129 {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout},
130 {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout},
131 {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout},
132 {FAMILY_4500, ARRAY_SIZE(f4500_layout), f4500_layout},
133 {FAMILY_8500, ARRAY_SIZE(f8500_layout), f8500_layout},
134 {FAMILY_8500RNG, ARRAY_SIZE(f8500_layout), f8500_layout},
135 {FAMILY_4600, ARRAY_SIZE(fx600_layout), fx600_layout},
136 {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout},
137 {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout},
138 {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout},
139};
140
141/* If we can't determine the layout, use this */
142static struct mem_layout default_layout[] = {
143 {0x20000000, 0x10000000, MEBIBYTE(128)},
144};
145
146/**
147 * register_non_ram - register low memory not available for RAM usage
148 */
149static __init void register_non_ram(void)
150{
151 int i;
152
153 for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++)
154 add_memory_region(low_mem_reserved[i].start,
155 low_mem_reserved[i].size, BOOT_MEM_RESERVED);
156}
157
158/**
159 * get_memsize - get the size of memory as a single bank
160 */
161static phys_addr_t get_memsize(void)
162{
163 static char cmdline[COMMAND_LINE_SIZE] __initdata;
164 phys_addr_t memsize = 0;
165 char *memsize_str;
166 char *ptr;
167
168 /* Check the command line first for a memsize directive */
169 strcpy(cmdline, arcs_cmdline);
170 ptr = strstr(cmdline, "memsize=");
171 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
172 ptr = strstr(ptr, " memsize=");
173
174 if (ptr) {
175 memsize = memparse(ptr + 8, &ptr);
176 } else {
177 /* otherwise look in the environment */
178 memsize_str = prom_getenv("memsize");
179
180 if (memsize_str != NULL) {
181 pr_info("prom memsize = %s\n", memsize_str);
182 memsize = simple_strtol(memsize_str, NULL, 0);
183 }
184
185 if (memsize == 0) {
186 if (_prom_memsize != 0) {
187 memsize = _prom_memsize;
188 pr_info("_prom_memsize = 0x%x\n", memsize);
189 /* add in memory that the bootloader doesn't
190 * report */
191 memsize += BLDR_SIZE;
192 } else {
193 memsize = DEFAULT_MEMSIZE;
194 pr_info("Memsize not passed by bootloader, "
195 "defaulting to 0x%x\n", memsize);
196 }
197 }
198 }
199
200 return memsize;
201}
202
203/**
204 * register_low_ram - register an aliased section of RAM
205 * @p: Alias address of memory
206 * @n: Number of bytes in this section of memory
207 *
208 * Returns the number of bytes registered
209 *
210 */
211static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n)
212{
213 phys_addr_t s;
214 int i;
215 phys_addr_t orig_n;
216
217 orig_n = n;
218
219 BUG_ON(p + n > RV_PHYS);
220
221 for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) {
222 phys_addr_t start;
223 phys_addr_t size;
224
225 start = low_mem_reserved[i].start;
226 size = low_mem_reserved[i].size;
227
228 /* Handle memory before this low memory section */
229 if (p < start) {
230 phys_addr_t s;
231 s = min(n, start - p);
232 add_memory_region(p, s, BOOT_MEM_RAM);
233 p += s;
234 n -= s;
235 }
236
237 /* Handle the low memory section itself. If it's aliased,
238 * we reduce the number of byes left, but if not, the RAM
239 * is available elsewhere and we don't reduce the number of
240 * bytes remaining. */
241 if (p == start) {
242 if (low_mem_reserved[i].is_aliased) {
243 s = min(n, size);
244 n -= s;
245 p += s;
246 } else
247 p += n;
248 }
249 }
250
251 return orig_n - n;
252}
253
254/*
255 * register_ram - register real RAM
256 * @p: Address of memory as seen by devices
257 * @alias: If the memory is seen at an additional address by the processor,
258 * this will be the address, otherwise it is the same as @p.
259 * @n: Number of bytes in this section of memory
260 */
261static __init void register_ram(phys_addr_t p, phys_addr_t alias,
262 phys_addr_t n)
263{
264 /*
265 * If some or all of this memory has an alias, break it into the
266 * aliased and non-aliased portion.
267 */
268 if (p != alias) {
269 phys_addr_t alias_size;
270 phys_addr_t registered;
271
272 alias_size = min(n, LOW_RAM_END - alias);
273 registered = register_low_ram(alias, alias_size);
274 ioremap_add_map(alias, p, n);
275 n -= registered;
276 p += registered;
277 }
278
279#ifdef CONFIG_HIGHMEM
280 if (n != 0) {
281 add_memory_region(p, n, BOOT_MEM_RAM);
282 ioremap_add_map(p, p, n);
283 }
284#endif
285}
286
287/**
288 * register_address_space - register things in the address space
289 * @memsize: Number of bytes of RAM installed
290 *
291 * Takes the given number of bytes of RAM and registers as many of the regions,
292 * or partial regions, as it can. So, the default configuration might have
293 * two regions with 256 MiB each. If the memsize passed in on the command line
294 * is 384 MiB, it will register the first region with 256 MiB and the second
295 * with 128 MiB.
296 */
297static __init void register_address_space(phys_addr_t memsize)
298{
299 int i;
300 phys_addr_t size;
301 size_t n;
302 struct mem_layout *layout;
303 enum family_type family;
304
305 /*
306 * Register all of the things that aren't available to the kernel as
307 * memory.
308 */
309 register_non_ram();
310
311 /* Find the appropriate memory description */
312 family = platform_get_family();
313
314 for (i = 0; i < ARRAY_SIZE(layout_list); i++) {
315 if (layout_list[i].family == family)
316 break;
317 }
318
319 if (i == ARRAY_SIZE(layout_list)) {
320 n = ARRAY_SIZE(default_layout);
321 layout = default_layout;
322 } else {
323 n = layout_list[i].n;
324 layout = layout_list[i].layout;
325 }
326
327 for (i = 0; memsize != 0 && i < n; i++) {
328 size = min(memsize, layout[i].size);
329 register_ram(layout[i].phys, layout[i].alias, size);
330 memsize -= size;
331 }
332}
333
334void __init prom_meminit(void)
335{
336 ptv_memsize = get_memsize();
337 register_address_space(ptv_memsize);
338}
339
340void __init prom_free_prom_memory(void)
341{
342 unsigned long addr;
343 int i;
344
345 for (i = 0; i < boot_mem_map.nr_map; i++) {
346 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
347 continue;
348
349 addr = boot_mem_map.map[i].addr;
350 free_init_pages("prom memory",
351 addr, addr + boot_mem_map.map[i].size);
352 }
353}
diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile
deleted file mode 100644
index 2610a6af5b2c..000000000000
--- a/arch/mips/powertv/pci/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-$(CONFIG_PCI) += fixup-powertv.o
diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c
deleted file mode 100644
index d7ecbae64a6e..000000000000
--- a/arch/mips/powertv/pci/fixup-powertv.c
+++ /dev/null
@@ -1,37 +0,0 @@
1#include <linux/init.h>
2#include <linux/export.h>
3#include <linux/pci.h>
4#include <asm/mach-powertv/interrupts.h>
5#include "powertv-pci.h"
6
7int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
8{
9 return asic_pcie_map_irq(dev, slot, pin);
10}
11
12/* Do platform specific device initialization at pci_enable_device() time */
13int pcibios_plat_dev_init(struct pci_dev *dev)
14{
15 return 0;
16}
17
18/*
19 * asic_pcie_map_irq
20 *
21 * Parameters:
22 * *dev - pointer to a pci_dev structure (not used)
23 * slot - slot number (not used)
24 * pin - pin number (not used)
25 *
26 * Return Value:
27 * Returns: IRQ number (always the PCI Express IRQ number)
28 *
29 * Description:
30 * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt.
31 *
32 */
33int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
34{
35 return irq_pciexp;
36}
37EXPORT_SYMBOL(asic_pcie_map_irq);
diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h
deleted file mode 100644
index 1b5886bbd759..000000000000
--- a/arch/mips/powertv/pci/powertv-pci.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * powertv-pci.c
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20/*
21 * Local definitions for the powertv PCI code
22 */
23
24#ifndef _POWERTV_PCI_POWERTV_PCI_H_
25#define _POWERTV_PCI_POWERTV_PCI_H_
26extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
27extern int asic_pcie_init(void);
28extern int asic_pcie_init(void);
29
30extern int log_level;
31#endif
diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h
deleted file mode 100644
index d94c54311485..000000000000
--- a/arch/mips/powertv/powertv-clock.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 *
18 * Author: David VomLehn
19 */
20
21#ifndef _POWERTV_POWERTV_CLOCK_H
22#define _POWERTV_POWERTV_CLOCK_H
23extern int powertv_clockevent_init(void);
24extern void powertv_clocksource_init(void);
25extern unsigned int mips_get_pll_freq(void);
26#endif
diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c
deleted file mode 100644
index d845eace58e9..000000000000
--- a/arch/mips/powertv/powertv-usb.c
+++ /dev/null
@@ -1,404 +0,0 @@
1/*
2 * powertv-usb.c
3 *
4 * Description: ASIC-specific USB device setup and shutdown
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 *
23 * Author: Ken Eppinett
24 * David Schleef <ds@schleef.org>
25 *
26 * NOTE: The bootloader allocates persistent memory at an address which is
27 * 16 MiB below the end of the highest address in KSEG0. All fixed
28 * address memory reservations must avoid this region.
29 */
30
31#include <linux/kernel.h>
32#include <linux/export.h>
33#include <linux/ioport.h>
34#include <linux/platform_device.h>
35#include <asm/mach-powertv/asic.h>
36#include <asm/mach-powertv/interrupts.h>
37
38/* misc_clk_ctl1 values */
39#define MCC1_30MHZ_POWERUP_SELECT (1 << 14)
40#define MCC1_DIV9 (1 << 13)
41#define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11)
42#define MCC1_USB_POWERUP_SELECT (1 << 1)
43#define MCC1_CLOCK108_POWERUP_SELECT (1 << 0)
44
45/* Possible values for clock select */
46#define MCC1_USB_CLOCK_HIGH_Z (0 << 4)
47#define MCC1_USB_CLOCK_48MHZ (1 << 4)
48#define MCC1_USB_CLOCK_24MHZ (2 << 4)
49#define MCC1_USB_CLOCK_6MHZ (3 << 4)
50
51#define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \
52 MCC1_DIV9 | \
53 MCC1_ETHMIPS_POWERUP_SELECT | \
54 MCC1_USB_POWERUP_SELECT | \
55 MCC1_CLOCK108_POWERUP_SELECT)
56
57/* misc_clk_ctl2 values */
58#define MCC2_GMII_GCLK_TO_PAD (1 << 31)
59#define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29)
60#define MCC2_RMII_0_CLOCK_SELECT (1 << 28)
61#define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27)
62#define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26)
63#define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24)
64#define MCC2_RMII_1_CLOCK_SELECT (1 << 23)
65#define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22)
66#define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21)
67#define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19)
68#define MCC2_RMII_2_CLOCK_SELECT (1 << 18)
69#define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17)
70#define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16)
71
72#define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \
73 MCC2_ETHER125_0_CLOCK_SELECT | \
74 MCC2_RMII_0_CLOCK_SELECT | \
75 MCC2_GMII_TX0_CLOCK_SELECT | \
76 MCC2_GMII_RX0_CLOCK_SELECT | \
77 MCC2_ETHER125_1_CLOCK_SELECT | \
78 MCC2_RMII_1_CLOCK_SELECT | \
79 MCC2_GMII_TX1_CLOCK_SELECT | \
80 MCC2_GMII_RX1_CLOCK_SELECT | \
81 MCC2_ETHER125_2_CLOCK_SELECT | \
82 MCC2_RMII_2_CLOCK_SELECT | \
83 MCC2_GMII_TX2_CLOCK_SELECT | \
84 MCC2_GMII_RX2_CLOCK_SELECT)
85
86/* misc_clk_ctl2 definitions for Gaia */
87#define FSX4A_REF_SELECT (1 << 16)
88#define FSX4B_REF_SELECT (1 << 17)
89#define FSX4C_REF_SELECT (1 << 18)
90#define DDR_PLL_REF_SELECT (1 << 19)
91#define MIPS_PLL_REF_SELECT (1 << 20)
92
93/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
94#define QAM_FS_SDIV_SHIFT 29
95#define QAM_FS_MD_SHIFT 24
96#define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */
97#define QAM_FS_PE_SHIFT 8
98
99#define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5)
100#define QAM_FS_ENABLE_PROGRAM (1 << 4)
101#define QAM_FS_ENABLE_OUTPUT (1 << 3)
102#define QAM_FS_SELECT_TEST_BYPASS (1 << 2)
103#define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1)
104#define QAM_FS_CHOOSE_FS (1 << 0)
105
106/* Definitions for fs432x4a_ctl register */
107#define QAM_FS_NSDIV_54MHZ (1 << 2)
108
109/* Definitions for bcm1_usb2_ctl register */
110#define BCM1_USB2_CTL_BISTOK (1 << 11)
111#define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7)
112#define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6)
113#define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5)
114#define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4)
115#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1)
116#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0)
117
118/* Definitions for crt_spare register */
119#define CRT_SPARE_PORT2_SHIFT_JK (1 << 21)
120#define CRT_SPARE_PORT1_SHIFT_JK (1 << 20)
121#define CRT_SPARE_PORT2_FAST_EDGE (1 << 19)
122#define CRT_SPARE_PORT1_FAST_EDGE (1 << 18)
123#define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17)
124#define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16)
125
126/* Definitions for usb2_stbus_obc register */
127#define USB_STBUS_OBC_STORE32_LOAD32 0x3
128
129/* Definitions for usb2_stbus_mess_size register */
130#define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */
131
132/* Definitions for usb2_stbus_chunk_size register */
133#define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */
134
135/* Definitions for usb2_strap register */
136#define USB2_STRAP_HFREQ_SELECT 0x1
137
138/*
139 * USB Host Resource Definition
140 */
141
142static struct resource ehci_resources[] = {
143 {
144 .parent = &asic_resource,
145 .start = 0,
146 .end = 0xff,
147 .flags = IORESOURCE_MEM,
148 },
149 {
150 .start = irq_usbehci,
151 .end = irq_usbehci,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static u64 ehci_dmamask = 0xffffffffULL;
157
158static struct platform_device ehci_device = {
159 .name = "powertv-ehci",
160 .id = 0,
161 .num_resources = 2,
162 .resource = ehci_resources,
163 .dev = {
164 .dma_mask = &ehci_dmamask,
165 .coherent_dma_mask = 0xffffffff,
166 },
167};
168
169static struct resource ohci_resources[] = {
170 {
171 .parent = &asic_resource,
172 .start = 0,
173 .end = 0xff,
174 .flags = IORESOURCE_MEM,
175 },
176 {
177 .start = irq_usbohci,
178 .end = irq_usbohci,
179 .flags = IORESOURCE_IRQ,
180 },
181};
182
183static u64 ohci_dmamask = 0xffffffffULL;
184
185static struct platform_device ohci_device = {
186 .name = "powertv-ohci",
187 .id = 0,
188 .num_resources = 2,
189 .resource = ohci_resources,
190 .dev = {
191 .dma_mask = &ohci_dmamask,
192 .coherent_dma_mask = 0xffffffff,
193 },
194};
195
196static unsigned usb_users;
197static DEFINE_SPINLOCK(usb_regs_lock);
198
199/*
200 *
201 * fs_update - set frequency synthesizer for USB
202 * @pe_bits Phase tap setting
203 * @md_bits Coarse selector bus for algorithm of phase tap
204 * @sdiv_bits Output divider setting
205 * @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
206 * @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
207 *
208 * QAM frequency selection code, which affects the frequency at which USB
209 * runs. The frequency is calculated as:
210 * 2^15 * ndiv * Fin
211 * Fout = ------------------------------------------------------------
212 * (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
213 * where:
214 * Fin 54 MHz
215 * ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16
216 * sdiv 1 << (sdiv_bits + 1)
217 * ipe Same as pe_bits
218 * md A five-bit, two's-complement integer (range [-16, 15]), which
219 * is the lower 5 bits of md_bits.
220 */
221static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
222 u32 disable_div_by_3, u32 standby)
223{
224 u32 val;
225
226 val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
227 ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
228 (pe_bits << QAM_FS_PE_SHIFT) |
229 QAM_FS_ENABLE_OUTPUT |
230 standby |
231 disable_div_by_3);
232 asic_write(val, fs432x4b4_usb_ctl);
233 asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
234 asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
235 fs432x4b4_usb_ctl);
236}
237
238/*
239 * usb_eye_configure - for optimizing the shape USB eye waveform
240 * @set: Bits to set in the register
241 * @clear: Bits to clear in the register; each bit with a one will
242 * be set in the register, zero bits will not be modified
243 */
244static void usb_eye_configure(u32 set, u32 clear)
245{
246 u32 old;
247
248 old = asic_read(crt_spare);
249 old |= set;
250 old &= ~clear;
251 asic_write(old, crt_spare);
252}
253
254/*
255 * platform_configure_usb - usb configuration based on platform type.
256 */
257static void platform_configure_usb(void)
258{
259 u32 bcm1_usb2_ctl_value;
260 enum asic_type asic_type;
261 unsigned long flags;
262
263 spin_lock_irqsave(&usb_regs_lock, flags);
264 usb_users++;
265
266 if (usb_users != 1) {
267 spin_unlock_irqrestore(&usb_regs_lock, flags);
268 return;
269 }
270
271 asic_type = platform_get_asic();
272
273 switch (asic_type) {
274 case ASIC_ZEUS:
275 fs_update(0x0000, -15, 0x02, 0, 0);
276 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
277 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
278 break;
279
280 case ASIC_CRONUS:
281 case ASIC_CRONUSLITE:
282 usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
283 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
284 QAM_FS_DISABLE_DIGITAL_STANDBY);
285 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
286 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
287 break;
288
289 case ASIC_CALLIOPE:
290 fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
291 QAM_FS_DISABLE_DIGITAL_STANDBY);
292
293 switch (platform_get_family()) {
294 case FAMILY_1500VZE:
295 break;
296
297 case FAMILY_1500VZF:
298 usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
299 CRT_SPARE_PORT1_SHIFT_JK |
300 CRT_SPARE_PORT2_FAST_EDGE |
301 CRT_SPARE_PORT1_FAST_EDGE, 0);
302 break;
303
304 default:
305 usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
306 CRT_SPARE_PORT1_SHIFT_JK, 0);
307 break;
308 }
309
310 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
311 BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
312 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
313 break;
314
315 case ASIC_GAIA:
316 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
317 QAM_FS_DISABLE_DIGITAL_STANDBY);
318 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
319 BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
320 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
321 break;
322
323 default:
324 pr_err("Unknown ASIC type: %d\n", asic_type);
325 bcm1_usb2_ctl_value = 0;
326 break;
327 }
328
329 /* turn on USB power */
330 asic_write(0, usb2_strap);
331 /* Enable all OHCI interrupts */
332 asic_write(bcm1_usb2_ctl_value, usb2_control);
333 /* usb2_stbus_obc store32/load32 */
334 asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
335 /* usb2_stbus_mess_size 2 packets */
336 asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
337 /* usb2_stbus_chunk_size 2 packets */
338 asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
339 spin_unlock_irqrestore(&usb_regs_lock, flags);
340}
341
342static void platform_unconfigure_usb(void)
343{
344 unsigned long flags;
345
346 spin_lock_irqsave(&usb_regs_lock, flags);
347 usb_users--;
348 if (usb_users == 0)
349 asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
350 spin_unlock_irqrestore(&usb_regs_lock, flags);
351}
352
353/*
354 * Set up the USB EHCI interface
355 */
356void platform_configure_usb_ehci()
357{
358 platform_configure_usb();
359}
360EXPORT_SYMBOL(platform_configure_usb_ehci);
361
362/*
363 * Set up the USB OHCI interface
364 */
365void platform_configure_usb_ohci()
366{
367 platform_configure_usb();
368}
369EXPORT_SYMBOL(platform_configure_usb_ohci);
370
371/*
372 * Shut the USB EHCI interface down
373 */
374void platform_unconfigure_usb_ehci()
375{
376 platform_unconfigure_usb();
377}
378EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
379
380/*
381 * Shut the USB OHCI interface down
382 */
383void platform_unconfigure_usb_ohci()
384{
385 platform_unconfigure_usb();
386}
387EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
388
389/**
390 * platform_devices_init - sets up USB device resourse.
391 */
392int __init platform_usb_devices_init(struct platform_device **ehci_dev,
393 struct platform_device **ohci_dev)
394{
395 *ehci_dev = &ehci_device;
396 ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
397 ehci_resources[0].end += ehci_resources[0].start;
398
399 *ohci_dev = &ohci_device;
400 ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
401 ohci_resources[0].end += ohci_resources[0].start;
402
403 return 0;
404}
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
deleted file mode 100644
index 24689bff1039..000000000000
--- a/arch/mips/powertv/powertv_setup.c
+++ /dev/null
@@ -1,319 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/ioport.h>
22#include <linux/pci.h>
23#include <linux/screen_info.h>
24#include <linux/notifier.h>
25#include <linux/etherdevice.h>
26#include <linux/if_ether.h>
27#include <linux/ctype.h>
28#include <linux/cpu.h>
29#include <linux/time.h>
30
31#include <asm/bootinfo.h>
32#include <asm/irq.h>
33#include <asm/mips-boards/generic.h>
34#include <asm/dma.h>
35#include <asm/asm.h>
36#include <asm/traps.h>
37#include <asm/asm-offsets.h>
38#include "reset.h"
39
40#define VAL(n) STR(n)
41
42/*
43 * Macros for loading addresses and storing registers:
44 * LONG_L_ Stringified version of LONG_L for use in asm() statement
45 * LONG_S_ Stringified version of LONG_S for use in asm() statement
46 * PTR_LA_ Stringified version of PTR_LA for use in asm() statement
47 * REG_SIZE Number of 8-bit bytes in a full width register
48 */
49#define LONG_L_ VAL(LONG_L) " "
50#define LONG_S_ VAL(LONG_S) " "
51#define PTR_LA_ VAL(PTR_LA) " "
52
53#ifdef CONFIG_64BIT
54#warning TODO: 64-bit code needs to be verified
55#define REG_SIZE "8" /* In bytes */
56#endif
57
58#ifdef CONFIG_32BIT
59#define REG_SIZE "4" /* In bytes */
60#endif
61
62static void register_panic_notifier(void);
63static int panic_handler(struct notifier_block *notifier_block,
64 unsigned long event, void *cause_string);
65
66const char *get_system_type(void)
67{
68 return "PowerTV";
69}
70
71void __init plat_mem_setup(void)
72{
73 panic_on_oops = 1;
74 register_panic_notifier();
75
76#if 0
77 mips_pcibios_init();
78#endif
79 mips_reboot_setup();
80}
81
82/*
83 * Install a panic notifier for platform-specific diagnostics
84 */
85static void register_panic_notifier()
86{
87 static struct notifier_block panic_notifier = {
88 .notifier_call = panic_handler,
89 .next = NULL,
90 .priority = INT_MAX
91 };
92 atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier);
93}
94
95static int panic_handler(struct notifier_block *notifier_block,
96 unsigned long event, void *cause_string)
97{
98 struct pt_regs my_regs;
99
100 /* Save all of the registers */
101 {
102 unsigned long at, v0, v1; /* Must be on the stack */
103
104 /* Start by saving $at and v0 on the stack. We use $at
105 * ourselves, but it looks like the compiler may use v0 or v1
106 * to load the address of the pt_regs structure. We'll come
107 * back later to store the registers in the pt_regs
108 * structure. */
109 __asm__ __volatile__ (
110 ".set noat\n"
111 LONG_S_ "$at, %[at]\n"
112 LONG_S_ "$2, %[v0]\n"
113 LONG_S_ "$3, %[v1]\n"
114 :
115 [at] "=m" (at),
116 [v0] "=m" (v0),
117 [v1] "=m" (v1)
118 :
119 : "at"
120 );
121
122 __asm__ __volatile__ (
123 ".set noat\n"
124 "move $at, %[pt_regs]\n"
125
126 /* Argument registers */
127 LONG_S_ "$4, " VAL(PT_R4) "($at)\n"
128 LONG_S_ "$5, " VAL(PT_R5) "($at)\n"
129 LONG_S_ "$6, " VAL(PT_R6) "($at)\n"
130 LONG_S_ "$7, " VAL(PT_R7) "($at)\n"
131
132 /* Temporary regs */
133 LONG_S_ "$8, " VAL(PT_R8) "($at)\n"
134 LONG_S_ "$9, " VAL(PT_R9) "($at)\n"
135 LONG_S_ "$10, " VAL(PT_R10) "($at)\n"
136 LONG_S_ "$11, " VAL(PT_R11) "($at)\n"
137 LONG_S_ "$12, " VAL(PT_R12) "($at)\n"
138 LONG_S_ "$13, " VAL(PT_R13) "($at)\n"
139 LONG_S_ "$14, " VAL(PT_R14) "($at)\n"
140 LONG_S_ "$15, " VAL(PT_R15) "($at)\n"
141
142 /* "Saved" registers */
143 LONG_S_ "$16, " VAL(PT_R16) "($at)\n"
144 LONG_S_ "$17, " VAL(PT_R17) "($at)\n"
145 LONG_S_ "$18, " VAL(PT_R18) "($at)\n"
146 LONG_S_ "$19, " VAL(PT_R19) "($at)\n"
147 LONG_S_ "$20, " VAL(PT_R20) "($at)\n"
148 LONG_S_ "$21, " VAL(PT_R21) "($at)\n"
149 LONG_S_ "$22, " VAL(PT_R22) "($at)\n"
150 LONG_S_ "$23, " VAL(PT_R23) "($at)\n"
151
152 /* Add'l temp regs */
153 LONG_S_ "$24, " VAL(PT_R24) "($at)\n"
154 LONG_S_ "$25, " VAL(PT_R25) "($at)\n"
155
156 /* Kernel temp regs */
157 LONG_S_ "$26, " VAL(PT_R26) "($at)\n"
158 LONG_S_ "$27, " VAL(PT_R27) "($at)\n"
159
160 /* Global pointer, stack pointer, frame pointer and
161 * return address */
162 LONG_S_ "$gp, " VAL(PT_R28) "($at)\n"
163 LONG_S_ "$sp, " VAL(PT_R29) "($at)\n"
164 LONG_S_ "$fp, " VAL(PT_R30) "($at)\n"
165 LONG_S_ "$ra, " VAL(PT_R31) "($at)\n"
166
167 /* Now we can get the $at and v0 registers back and
168 * store them */
169 LONG_L_ "$8, %[at]\n"
170 LONG_S_ "$8, " VAL(PT_R1) "($at)\n"
171 LONG_L_ "$8, %[v0]\n"
172 LONG_S_ "$8, " VAL(PT_R2) "($at)\n"
173 LONG_L_ "$8, %[v1]\n"
174 LONG_S_ "$8, " VAL(PT_R3) "($at)\n"
175 :
176 :
177 [at] "m" (at),
178 [v0] "m" (v0),
179 [v1] "m" (v1),
180 [pt_regs] "r" (&my_regs)
181 : "at", "t0"
182 );
183
184 /* Set the current EPC value to be the current location in this
185 * function */
186 __asm__ __volatile__ (
187 ".set noat\n"
188 "1:\n"
189 PTR_LA_ "$at, 1b\n"
190 LONG_S_ "$at, %[cp0_epc]\n"
191 :
192 [cp0_epc] "=m" (my_regs.cp0_epc)
193 :
194 : "at"
195 );
196
197 my_regs.cp0_cause = read_c0_cause();
198 my_regs.cp0_status = read_c0_status();
199 }
200
201 pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
202 "zzzz... \n");
203
204 return NOTIFY_DONE;
205}
206
207/* Information about the RF MAC address, if one was supplied on the
208 * command line. */
209static bool have_rfmac;
210static u8 rfmac[ETH_ALEN];
211
212static int rfmac_param(char *p)
213{
214 u8 *q;
215 bool is_high_nibble;
216 int c;
217
218 /* Skip a leading "0x", if present */
219 if (*p == '0' && *(p+1) == 'x')
220 p += 2;
221
222 q = rfmac;
223 is_high_nibble = true;
224
225 for (c = (unsigned char) *p++;
226 isxdigit(c) && q - rfmac < ETH_ALEN;
227 c = (unsigned char) *p++) {
228 int nibble;
229
230 nibble = (isdigit(c) ? (c - '0') :
231 (isupper(c) ? c - 'A' + 10 : c - 'a' + 10));
232
233 if (is_high_nibble)
234 *q = nibble << 4;
235 else
236 *q++ |= nibble;
237
238 is_high_nibble = !is_high_nibble;
239 }
240
241 /* If we parsed all the way to the end of the parameter value and
242 * parsed all ETH_ALEN bytes, we have a usable RF MAC address */
243 have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN);
244
245 return 0;
246}
247
248early_param("rfmac", rfmac_param);
249
250/*
251 * Generate an Ethernet MAC address that has a good chance of being unique.
252 * @addr: Pointer to six-byte array containing the Ethernet address
253 * Generates an Ethernet MAC address that is highly likely to be unique for
254 * this particular system on a network with other systems of the same type.
255 *
256 * The problem we are solving is that, when eth_random_addr() is used to
257 * generate MAC addresses at startup, there isn't much entropy for the random
258 * number generator to use and the addresses it produces are fairly likely to
259 * be the same as those of other identical systems on the same local network.
260 * This is true even for relatively small numbers of systems (for the reason
261 * why, see the Wikipedia entry for "Birthday problem" at:
262 * http://en.wikipedia.org/wiki/Birthday_problem
263 *
264 * The good news is that we already have a MAC address known to be unique, the
265 * RF MAC address. The bad news is that this address is already in use on the
266 * RF interface. Worse, the obvious trick, taking the RF MAC address and
267 * turning on the locally managed bit, has already been used for other devices.
268 * Still, this does give us something to work with.
269 *
270 * The approach we take is:
271 * 1. If we can't get the RF MAC Address, just call eth_random_addr.
272 * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24
273 * bits of the new address. This is very likely to be unique, except for
274 * the current box.
275 * 3. To avoid using addresses already on the current box, we set the top
276 * six bits of the address with a value different from any currently
277 * registered Scientific Atlanta organizationally unique identifyer
278 * (OUI). This avoids duplication with any addresses on the system that
279 * were generated from valid Scientific Atlanta-registered address by
280 * simply flipping the locally managed bit.
281 * 4. We aren't generating a multicast address, so we leave the multicast
282 * bit off. Since we aren't using a registered address, we have to set
283 * the locally managed bit.
284 * 5. We then randomly generate the remaining 16-bits. This does two
285 * things:
286 * a. It allows us to call this function for more than one device
287 * in this system
288 * b. It ensures that things will probably still work even if
289 * some device on the device network has a locally managed
290 * address that matches the top six bits from step 2.
291 */
292void platform_random_ether_addr(u8 addr[ETH_ALEN])
293{
294 const int num_random_bytes = 2;
295 const unsigned char non_sciatl_oui_bits = 0xc0u;
296 const unsigned char mac_addr_locally_managed = (1 << 1);
297
298 if (!have_rfmac) {
299 pr_warning("rfmac not available on command line; "
300 "generating random MAC address\n");
301 eth_random_addr(addr);
302 }
303
304 else {
305 int i;
306
307 /* Set the first byte to something that won't match a Scientific
308 * Atlanta OUI, is locally managed, and isn't a multicast
309 * address */
310 addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed;
311
312 /* Get some bytes of random address information */
313 get_random_bytes(&addr[1], num_random_bytes);
314
315 /* Copy over the NIC-specific bits of the RF MAC address */
316 for (i = 1 + num_random_bytes; i < ETH_ALEN; i++)
317 addr[i] = rfmac[i];
318 }
319}
diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c
deleted file mode 100644
index 11c32fbf2784..000000000000
--- a/arch/mips/powertv/reset.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/pm.h>
20
21#include <linux/io.h>
22#include <asm/reboot.h> /* Not included by linux/reboot.h */
23
24#include <asm/mach-powertv/asic_regs.h>
25#include "reset.h"
26
27static void mips_machine_restart(char *command)
28{
29 writel(0x1, asic_reg_addr(watchdog));
30}
31
32void mips_reboot_setup(void)
33{
34 _machine_restart = mips_machine_restart;
35}
diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h
deleted file mode 100644
index 888fd09e2620..000000000000
--- a/arch/mips/powertv/reset.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Definitions from powertv reset.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_POWERTV_RESET_H
24#define _POWERTV_POWERTV_RESET_H
25extern void mips_reboot_setup(void);
26#endif
diff --git a/arch/mips/powertv/time.c b/arch/mips/powertv/time.c
deleted file mode 100644
index f38b0d45eca9..000000000000
--- a/arch/mips/powertv/time.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Setting up the clock on the MIPS boards.
20 */
21
22#include <linux/init.h>
23#include <asm/mach-powertv/interrupts.h>
24#include <asm/time.h>
25
26#include "powertv-clock.h"
27
28unsigned int get_c0_compare_int(void)
29{
30 return irq_mips_timer;
31}
32
33void __init plat_time_init(void)
34{
35 powertv_clocksource_init();
36}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 15:15:14 -0500