Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "More hardware support across the field including a bunch of device
  drivers.  The highlight however really are further steps towards
  device tree.

  This has been sitting in -next for ages.  All MIPS _defconfigs have
  been tested to boot or where I don't have hardware available, to at
  least build fine."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (77 commits)
  MIPS: Loongson 1B: Add defconfig
  MIPS: Loongson 1B: Add board support
  MIPS: Netlogic: early console fix
  MIPS: Netlogic: Fix indentation of smpboot.S
  MIPS: Netlogic: remove cpu_has_dc_aliases define for XLP
  MIPS: Netlogic: Remove unused pcibios_fixups
  MIPS: Netlogic: Add XLP SoC devices in FDT
  MIPS: Netlogic: Add IRQ mappings for more devices
  MIPS: Netlogic: USB support for XLP
  MIPS: Netlogic: XLP PCIe controller support.
  MIPS: Netlogic: Platform changes for XLR/XLS I2C
  MIPS: Netlogic: Platform NAND/NOR flash support
  MIPS: Netlogic: Platform changes for XLS USB
  MIPS: Netlogic: Remove NETLOGIC_ prefix
  MIPS: Netlogic: SMP wakeup code update
  MIPS: Netlogic: Update comments in smpboot.S
  MIPS: BCM63XX: Add 96328avng reference board
  MIPS: Expose PCIe drivers for MIPS
  MIPS: BCM63XX: Add PCIe Support for BCM6328
  MIPS: BCM63XX: Move the PCI initialization into its own function
  ...

9 files changed, 462 insertions, 16 deletions

diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c703f43a9914..e13a71cbc3c7 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_WR_PPMC)		+= fixup-wrppmc.o
 obj-$(CONFIG_MIKROTIK_RB532)    += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
 obj-$(CONFIG_CPU_XLR)           += pci-xlr.o
+obj-$(CONFIG_CPU_XLP)           += pci-xlp.o
 
 ifdef CONFIG_PCI_MSI
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002dd..3e7ce65d776c 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -37,7 +37,7 @@
 #define VIA_COBALT_BRD_ID_REG  0x94
 #define VIA_COBALT_BRD_REG_to_ID(reg)   ((unsigned char)(reg) >> 4)
 
-static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_galileo_early_fixup(struct pci_dev *dev)
 {
         if (dev->devfn == PCI_DEVFN(0, 0) &&
                 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
@@ -51,7 +51,7 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
-static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
         unsigned char lt;
@@ -74,7 +74,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
          qube_raq_via_bmIDE_fixup);
 
-static void qube_raq_galileo_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_galileo_fixup(struct pci_dev *dev)
 {
         if (dev->devfn != PCI_DEVFN(0, 0))
                 return;
@@ -129,7 +129,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
 
 int cobalt_board_id;
 
-static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_via_board_id_fixup(struct pci_dev *dev)
 {
         u8 id;
         int retval;
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 70073c98ed32..819622f93e9c 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -101,3 +101,17 @@ static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev)
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
          malta_piix_func1_fixup);
+
+/* Enable PCI 2.1 compatibility in PIIX4 */
+static void __devinit quirk_dlcsetup(struct pci_dev *dev)
+{
+        u8 odlc, ndlc;
+
+        (void) pci_read_config_byte(dev, 0x82, &odlc);
+        /* Enable passive releases and delayed transaction */
+        ndlc = odlc | 7;
+        (void) pci_write_config_byte(dev, 0x82, ndlc);
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
+        quirk_dlcsetup);
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index 3d86823d03a0..76bb1be99d43 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -47,7 +47,7 @@ int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         return irq + GROUP4_IRQ_BASE + 4;
 }
 
-static void rc32434_pci_early_fixup(struct pci_dev *dev)
+static void __devinit rc32434_pci_early_fixup(struct pci_dev *dev)
 {
         if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
                 /* disable prefetched memory range */
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 822ae179bc56..65c7bd100486 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -411,7 +411,7 @@ struct pci_ops bcm63xx_cb_ops = {
  * only one IO window, so it  cannot be shared by PCI and cardbus, use
  * fixup to choose and detect unhandled configuration
  */
-static void bcm63xx_fixup(struct pci_dev *dev)
+static void __devinit bcm63xx_fixup(struct pci_dev *dev)
 {
         static int io_window = -1;
         int i, found, new_io_window;
@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev *dev)
 
 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
 #endif
+
+static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
+{
+        switch (bus->number) {
+        case PCIE_BUS_BRIDGE:
+                return (PCI_SLOT(devfn) == 0);
+        case PCIE_BUS_DEVICE:
+                if (PCI_SLOT(devfn) == 0)
+                        return bcm_pcie_readl(PCIE_DLSTATUS_REG)
+                                        & DLSTATUS_PHYLINKUP;
+        default:
+                return false;
+        }
+}
+
+static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
+                             int where, int size, u32 *val)
+{
+        u32 data;
+        u32 reg = where & ~3;
+
+        if (!bcm63xx_pcie_can_access(bus, devfn))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (bus->number == PCIE_BUS_DEVICE)
+                reg += PCIE_DEVICE_OFFSET;
+
+        data = bcm_pcie_readl(reg);
+
+        *val = postprocess_read(data, where, size);
+
+        return PCIBIOS_SUCCESSFUL;
+
+}
+
+static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
+                              int where, int size, u32 val)
+{
+        u32 data;
+        u32 reg = where & ~3;
+
+        if (!bcm63xx_pcie_can_access(bus, devfn))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (bus->number == PCIE_BUS_DEVICE)
+                reg += PCIE_DEVICE_OFFSET;
+
+
+        data = bcm_pcie_readl(reg);
+
+        data = preprocess_write(data, val, where, size);
+        bcm_pcie_writel(data, reg);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+struct pci_ops bcm63xx_pcie_ops = {
+        .read   = bcm63xx_pcie_read,
+        .write  = bcm63xx_pcie_write
+};
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 39eb7c417e2f..8a48139d219c 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -10,6 +10,7 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/delay.h>
 #include <asm/bootinfo.h>
 
 #include "pci-bcm63xx.h"
@@ -71,6 +72,26 @@ struct pci_controller bcm63xx_cb_controller = {
 };
 #endif
 
+static struct resource bcm_pcie_mem_resource = {
+        .name   = "bcm63xx PCIe memory space",
+        .start  = BCM_PCIE_MEM_BASE_PA,
+        .end    = BCM_PCIE_MEM_END_PA,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource bcm_pcie_io_resource = {
+        .name   = "bcm63xx PCIe IO space",
+        .start  = 0,
+        .end    = 0,
+        .flags  = 0,
+};
+
+struct pci_controller bcm63xx_pcie_controller = {
+        .pci_ops        = &bcm63xx_pcie_ops,
+        .io_resource    = &bcm_pcie_io_resource,
+        .mem_resource   = &bcm_pcie_mem_resource,
+};
+
 static u32 bcm63xx_int_cfg_readl(u32 reg)
 {
         u32 tmp;
@@ -94,17 +115,99 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
 
 void __iomem *pci_iospace_start;
 
-static int __init bcm63xx_pci_init(void)
+static void __init bcm63xx_reset_pcie(void)
 {
-        unsigned int mem_size;
         u32 val;
 
-        if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
-                return -ENODEV;
+        /* enable clock */
+        val = bcm_perf_readl(PERF_CKCTL_REG);
+        val |= CKCTL_6328_PCIE_EN;
+        bcm_perf_writel(val, PERF_CKCTL_REG);
+
+        /* enable SERDES */
+        val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
+        val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
+        bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
+
+        /* reset the PCIe core */
+        val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
+
+        val &= ~SOFTRESET_6328_PCIE_MASK;
+        val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
+        val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
+        val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
+        bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+        mdelay(10);
+
+        val |= SOFTRESET_6328_PCIE_MASK;
+        val |= SOFTRESET_6328_PCIE_CORE_MASK;
+        val |= SOFTRESET_6328_PCIE_HARD_MASK;
+        bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+        mdelay(10);
+
+        val |= SOFTRESET_6328_PCIE_EXT_MASK;
+        bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+        mdelay(200);
+}
 
-        if (!bcm63xx_pci_enabled)
-                return -ENODEV;
+static int __init bcm63xx_register_pcie(void)
+{
+        u32 val;
 
+        bcm63xx_reset_pcie();
+
+        /* configure the PCIe bridge */
+        val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
+        val |= OPT1_RD_BE_OPT_EN;
+        val |= OPT1_RD_REPLY_BE_FIX_EN;
+        val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
+        val |= OPT1_L1_INT_STATUS_MASK_POL;
+        bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
+
+        /* setup the interrupts */
+        val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
+        val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
+        bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
+
+        val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
+        /* enable credit checking and error checking */
+        val |= OPT2_TX_CREDIT_CHK_EN;
+        val |= OPT2_UBUS_UR_DECODE_DIS;
+
+        /* set device bus/func for the pcie device */
+        val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
+        val |= OPT2_CFG_TYPE1_BD_SEL;
+        bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
+
+        /* setup class code as bridge */
+        val = bcm_pcie_readl(PCIE_IDVAL3_REG);
+        val &= ~IDVAL3_CLASS_CODE_MASK;
+        val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+        bcm_pcie_writel(val, PCIE_IDVAL3_REG);
+
+        /* disable bar1 size */
+        val = bcm_pcie_readl(PCIE_CONFIG2_REG);
+        val &= ~CONFIG2_BAR1_SIZE_MASK;
+        bcm_pcie_writel(val, PCIE_CONFIG2_REG);
+
+        /* set bar0 to little endian */
+        val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
+        val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
+        val |= BASEMASK_REMAP_EN;
+        bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
+
+        val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
+        bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+
+        register_pci_controller(&bcm63xx_pcie_controller);
+
+        return 0;
+}
+
+static int __init bcm63xx_register_pci(void)
+{
+        unsigned int mem_size;
+        u32 val;
         /*
          * configuration  access are  done through  IO space,  remap 4
          * first bytes to access it from CPU.
@@ -221,4 +324,22 @@ static int __init bcm63xx_pci_init(void)
         return 0;
 }
 
+
+static int __init bcm63xx_pci_init(void)
+{
+        if (!bcm63xx_pci_enabled)
+                return -ENODEV;
+
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                return bcm63xx_register_pcie();
+        case BCM6348_CPU_ID:
+        case BCM6358_CPU_ID:
+        case BCM6368_CPU_ID:
+                return bcm63xx_register_pci();
+        default:
+                return -ENODEV;
+        }
+}
+
 arch_initcall(bcm63xx_pci_init);
diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
index a6e594ef3d6a..e6736d558ac7 100644
--- a/arch/mips/pci/pci-bcm63xx.h
+++ b/arch/mips/pci/pci-bcm63xx.h
@@ -13,11 +13,16 @@
  */
 #define CARDBUS_PCI_IDSEL       0x8
 
+
+#define PCIE_BUS_BRIDGE         0
+#define PCIE_BUS_DEVICE         1
+
 /*
  * defined in ops-bcm63xx.c
  */
 extern struct pci_ops bcm63xx_pci_ops;
 extern struct pci_ops bcm63xx_cb_ops;
+extern struct pci_ops bcm63xx_pcie_ops;
 
 /*
  * defined in pci-bcm63xx.c
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
new file mode 100644
index 000000000000..140557a20488
--- /dev/null
+++ b/arch/mips/pci/pci-xlp.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/msi.h>
+#include <linux/mm.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
+#include <linux/console.h>
+
+#include <asm/io.h>
+
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/haldefs.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pcibus.h>
+#include <asm/netlogic/xlp-hal/bridge.h>
+
+static void *pci_config_base;
+
+#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
+
+/* PCI ops */
+static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
+        int where)
+{
+        u32 data;
+        u32 *cfgaddr;
+
+        cfgaddr = (u32 *)(pci_config_base +
+                        pci_cfg_addr(bus->number, devfn, where & ~3));
+        data = *cfgaddr;
+        return data;
+}
+
+static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
+        int where, u32 data)
+{
+        u32 *cfgaddr;
+
+        cfgaddr = (u32 *)(pci_config_base +
+                        pci_cfg_addr(bus->number, devfn, where & ~3));
+        *cfgaddr = data;
+}
+
+static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
+        int where, int size, u32 *val)
+{
+        u32 data;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        data = pci_cfg_read_32bit(bus, devfn, where);
+
+        if (size == 1)
+                *val = (data >> ((where & 3) << 3)) & 0xff;
+        else if (size == 2)
+                *val = (data >> ((where & 3) << 3)) & 0xffff;
+        else
+                *val = data;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
+                int where, int size, u32 val)
+{
+        u32 data;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        data = pci_cfg_read_32bit(bus, devfn, where);
+
+        if (size == 1)
+                data = (data & ~(0xff << ((where & 3) << 3))) |
+                        (val << ((where & 3) << 3));
+        else if (size == 2)
+                data = (data & ~(0xffff << ((where & 3) << 3))) |
+                        (val << ((where & 3) << 3));
+        else
+                data = val;
+
+        pci_cfg_write_32bit(bus, devfn, where, data);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops nlm_pci_ops = {
+        .read  = nlm_pcibios_read,
+        .write = nlm_pcibios_write
+};
+
+static struct resource nlm_pci_mem_resource = {
+        .name           = "XLP PCI MEM",
+        .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
+        .end            = 0xdfffffffUL,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct resource nlm_pci_io_resource = {
+        .name           = "XLP IO MEM",
+        .start          = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
+        .end            = 0x17ffffffUL,
+        .flags          = IORESOURCE_IO,
+};
+
+struct pci_controller nlm_pci_controller = {
+        .index          = 0,
+        .pci_ops        = &nlm_pci_ops,
+        .mem_resource   = &nlm_pci_mem_resource,
+        .mem_offset     = 0x00000000UL,
+        .io_resource    = &nlm_pci_io_resource,
+        .io_offset      = 0x00000000UL,
+};
+
+static int get_irq_vector(const struct pci_dev *dev)
+{
+        /*
+         * For XLP PCIe, there is an IRQ per Link, find out which
+         * link the device is on to assign interrupts
+        */
+        if (dev->bus->self == NULL)
+                return 0;
+
+        switch  (dev->bus->self->devfn) {
+        case 0x8:
+                return PIC_PCIE_LINK_0_IRQ;
+        case 0x9:
+                return PIC_PCIE_LINK_1_IRQ;
+        case 0xa:
+                return PIC_PCIE_LINK_2_IRQ;
+        case 0xb:
+                return PIC_PCIE_LINK_3_IRQ;
+        }
+        WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
+        return 0;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return get_irq_vector(dev);
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+static int xlp_enable_pci_bswap(void)
+{
+        uint64_t pciebase, sysbase;
+        int node, i;
+        u32 reg;
+
+        /* Chip-0 so node set to 0 */
+        node = 0;
+        sysbase = nlm_get_bridge_regbase(node);
+        /*
+         *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
+         * from the link's address ranges.
+         */
+        for (i = 0; i < 4; i++) {
+                pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i));
+                if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
+                        continue;
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg);
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM,
+                        reg | 0xfff);
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg);
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
+        }
+        return 0;
+}
+
+static int __init pcibios_init(void)
+{
+        /* Firmware assigns PCI resources */
+        pci_set_flags(PCI_PROBE_ONLY);
+        pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
+
+        /* Extend IO port for memory mapped io */
+        ioport_resource.start =  0;
+        ioport_resource.end   = ~0;
+
+        xlp_enable_pci_bswap();
+        set_io_port_base(CKSEG1);
+        nlm_pci_controller.io_map_base = CKSEG1;
+
+        register_pci_controller(&nlm_pci_controller);
+        pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
+                &nlm_pci_mem_resource);
+
+        return 0;
+}
+arch_initcall(pcibios_init);
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 172af1cd5867..18af021d289a 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -375,7 +375,3 @@ static int __init pcibios_init(void)
 }
 
 arch_initcall(pcibios_init);
-
-struct pci_fixup pcibios_fixups[] = {
-        {0}
-};