MIPS: KVM: Use host CCA for TLB mappings

KVM TLB mappings for the guest were being created with a cache coherency
attribute (CCA) of 3, which is cached incoherent. Create them instead
with the default host CCA, which should be the correct one for coherency
on SMP systems.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2 files changed, 12 insertions, 9 deletions

diff --git a/arch/mips/kvm/mmu.c b/arch/mips/kvm/mmu.c
index 2f494ec5c939..ecead748de04 100644
--- a/arch/mips/kvm/mmu.c
+++ b/arch/mips/kvm/mmu.c
@@ -116,9 +116,11 @@ int kvm_mips_handle_kseg0_tlb_fault(unsigned long badvaddr,
         pfn1 = kvm->arch.guest_pmap[gfn | 0x1];
 
         entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) |
-                   (0x3 << ENTRYLO_C_SHIFT) | ENTRYLO_D | ENTRYLO_V;
+                ((_page_cachable_default >> _CACHE_SHIFT) << ENTRYLO_C_SHIFT) |
+                ENTRYLO_D | ENTRYLO_V;
         entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) |
-                   (0x3 << ENTRYLO_C_SHIFT) | ENTRYLO_D | ENTRYLO_V;
+                ((_page_cachable_default >> _CACHE_SHIFT) << ENTRYLO_C_SHIFT) |
+                ENTRYLO_D | ENTRYLO_V;
 
         preempt_disable();
         entryhi = (vaddr | kvm_mips_get_kernel_asid(vcpu));
@@ -157,13 +159,13 @@ int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 
         /* Get attributes from the Guest TLB */
         entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) |
-                   (0x3 << ENTRYLO_C_SHIFT) |
-                   (tlb->tlb_lo[0] & ENTRYLO_D) |
-                   (tlb->tlb_lo[0] & ENTRYLO_V);
+                ((_page_cachable_default >> _CACHE_SHIFT) << ENTRYLO_C_SHIFT) |
+                (tlb->tlb_lo[0] & ENTRYLO_D) |
+                (tlb->tlb_lo[0] & ENTRYLO_V);
         entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) |
-                   (0x3 << ENTRYLO_C_SHIFT) |
-                   (tlb->tlb_lo[1] & ENTRYLO_D) |
-                   (tlb->tlb_lo[1] & ENTRYLO_V);
+                ((_page_cachable_default >> _CACHE_SHIFT) << ENTRYLO_C_SHIFT) |
+                (tlb->tlb_lo[1] & ENTRYLO_D) |
+                (tlb->tlb_lo[1] & ENTRYLO_V);
 
         kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc,
                   tlb->tlb_lo[0], tlb->tlb_lo[1]);
diff --git a/arch/mips/kvm/tlb.c b/arch/mips/kvm/tlb.c
index 385fbd34e77d..9699352293e4 100644
--- a/arch/mips/kvm/tlb.c
+++ b/arch/mips/kvm/tlb.c
@@ -179,7 +179,8 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
         pfn = CPHYSADDR(vcpu->arch.kseg0_commpage) >> PAGE_SHIFT;
         pair_idx = (badvaddr >> PAGE_SHIFT) & 1;
         entrylo[pair_idx] = mips3_paddr_to_tlbpfn(pfn << PAGE_SHIFT) |
-                (0x3 << ENTRYLO_C_SHIFT) | ENTRYLO_D | ENTRYLO_V;
+                ((_page_cachable_default >> _CACHE_SHIFT) << ENTRYLO_C_SHIFT) |
+                ENTRYLO_D | ENTRYLO_V;
 
         local_irq_save(flags);