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authorJayachandran C <jchandra@broadcom.com>2013-08-11 07:40:16 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-10-29 16:23:51 -0400
commitc2377a42cd7696022448bcebaa12b07427dc1038 (patch)
tree93ee8cab72fba818cf298ecac79c2221e6d86078 /arch/mips/include/asm/stackframe.h
parent1a9db0a9ea11ebf2d83d928f4933f21bf6a808e9 (diff)
MIPS: Move definition of SMP processor id register to header file
The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/stackframe.h')
-rw-r--r--arch/mips/include/asm/stackframe.h24
1 files changed, 6 insertions, 18 deletions
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 23fc95e65673..4857e2c8df5a 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -17,6 +17,7 @@
17#include <asm/asmmacro.h> 17#include <asm/asmmacro.h>
18#include <asm/mipsregs.h> 18#include <asm/mipsregs.h>
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/thread_info.h>
20 21
21/* 22/*
22 * For SMTC kernel, global IE should be left set, and interrupts 23 * For SMTC kernel, global IE should be left set, and interrupts
@@ -93,21 +94,8 @@
93 .endm 94 .endm
94 95
95#ifdef CONFIG_SMP 96#ifdef CONFIG_SMP
96#ifdef CONFIG_MIPS_MT_SMTC
97#define PTEBASE_SHIFT 19 /* TCBIND */
98#define CPU_ID_REG CP0_TCBIND
99#define CPU_ID_MFC0 mfc0
100#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
101#define PTEBASE_SHIFT 48 /* XCONTEXT */
102#define CPU_ID_REG CP0_XCONTEXT
103#define CPU_ID_MFC0 MFC0
104#else
105#define PTEBASE_SHIFT 23 /* CONTEXT */
106#define CPU_ID_REG CP0_CONTEXT
107#define CPU_ID_MFC0 MFC0
108#endif
109 .macro get_saved_sp /* SMP variation */ 97 .macro get_saved_sp /* SMP variation */
110 CPU_ID_MFC0 k0, CPU_ID_REG 98 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
111#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 99#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
112 lui k1, %hi(kernelsp) 100 lui k1, %hi(kernelsp)
113#else 101#else
@@ -117,17 +105,17 @@
117 daddiu k1, %hi(kernelsp) 105 daddiu k1, %hi(kernelsp)
118 dsll k1, 16 106 dsll k1, 16
119#endif 107#endif
120 LONG_SRL k0, PTEBASE_SHIFT 108 LONG_SRL k0, SMP_CPUID_PTRSHIFT
121 LONG_ADDU k1, k0 109 LONG_ADDU k1, k0
122 LONG_L k1, %lo(kernelsp)(k1) 110 LONG_L k1, %lo(kernelsp)(k1)
123 .endm 111 .endm
124 112
125 .macro set_saved_sp stackp temp temp2 113 .macro set_saved_sp stackp temp temp2
126 CPU_ID_MFC0 \temp, CPU_ID_REG 114 ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG
127 LONG_SRL \temp, PTEBASE_SHIFT 115 LONG_SRL \temp, SMP_CPUID_PTRSHIFT
128 LONG_S \stackp, kernelsp(\temp) 116 LONG_S \stackp, kernelsp(\temp)
129 .endm 117 .endm
130#else 118#else /* !CONFIG_SMP */
131 .macro get_saved_sp /* Uniprocessor variation */ 119 .macro get_saved_sp /* Uniprocessor variation */
132#ifdef CONFIG_CPU_JUMP_WORKAROUNDS 120#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
133 /* 121 /*