MIPS: Netlogic: Add support for USB on XLP2xx

Add USB intialization code to handle the new XLP2XX USB 3.0 block.
This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic
for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h
and xlp/nlm_hal.c is also updated for the new USB block.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5744/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 12 insertions, 0 deletions

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 61c84de0ed4f..55eee77adaca 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -72,6 +72,12 @@
 #define XLP_IO_USB_OHCI2_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 4)
 #define XLP_IO_USB_OHCI3_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 5)
 
+/* XLP2xx has an updated USB block */
+#define XLP2XX_IO_USB_OFFSET(node, i)   XLP_HDR_OFFSET(node, 0, 4, i)
+#define XLP2XX_IO_USB_XHCI0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 1)
+#define XLP2XX_IO_USB_XHCI1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 2)
+#define XLP2XX_IO_USB_XHCI2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 3)
+
 #define XLP_IO_NAE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 0)
 #define XLP_IO_POE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 1)
 
@@ -148,6 +154,7 @@
 #define PCI_DEVICE_ID_NLM_NOR           0x1015
 #define PCI_DEVICE_ID_NLM_NAND          0x1016
 #define PCI_DEVICE_ID_NLM_MMC           0x1018
+#define PCI_DEVICE_ID_NLM_XHCI          0x101d
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 4950ea502398..17daffb280a3 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -41,12 +41,17 @@
 #define PIC_PCIE_LINK_1_IRQ             20
 #define PIC_PCIE_LINK_2_IRQ             21
 #define PIC_PCIE_LINK_3_IRQ             22
+
 #define PIC_EHCI_0_IRQ                  23
 #define PIC_EHCI_1_IRQ                  24
 #define PIC_OHCI_0_IRQ                  25
 #define PIC_OHCI_1_IRQ                  26
 #define PIC_OHCI_2_IRQ                  27
 #define PIC_OHCI_3_IRQ                  28
+#define PIC_2XX_XHCI_0_IRQ              23
+#define PIC_2XX_XHCI_1_IRQ              24
+#define PIC_2XX_XHCI_2_IRQ              25
+
 #define PIC_MMC_IRQ                     29
 #define PIC_I2C_0_IRQ                   30
 #define PIC_I2C_1_IRQ                   31