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authorJames Hogan <james.hogan@imgtec.com>2016-05-20 18:28:41 -0400
committerRalf Baechle <ralf@linux-mips.org>2016-05-28 06:35:10 -0400
commit5aadab0c1a3451565dec3b02ebbe162854d39181 (patch)
treecc5eae4abc73be41839b7a202d48932bb20cf79a /arch/mips/include/asm/mipsregs.h
parentc84700cc575f4625e719817595b3df33c00307c7 (diff)
MIPS: Simplify DSP instruction encoding macros
Simplify the DSP instruction wrapper macros which use explicit encodings for microMIPS and normal MIPS by using the new encoding macros and removing duplication. To me this makes it easier to read since it is much shorter, but it also ensures .insn is used, preventing objdump disassembling the microMIPS code as normal MIPS. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13314/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
-rw-r--r--arch/mips/include/asm/mipsregs.h107
1 files changed, 17 insertions, 90 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 918c576bf9ec..3a062ae933a4 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2282,7 +2282,6 @@ do { \
2282 2282
2283#else 2283#else
2284 2284
2285#ifdef CONFIG_CPU_MICROMIPS
2286#define rddsp(mask) \ 2285#define rddsp(mask) \
2287({ \ 2286({ \
2288 unsigned int __res; \ 2287 unsigned int __res; \
@@ -2291,8 +2290,8 @@ do { \
2291 " .set push \n" \ 2290 " .set push \n" \
2292 " .set noat \n" \ 2291 " .set noat \n" \
2293 " # rddsp $1, %x1 \n" \ 2292 " # rddsp $1, %x1 \n" \
2294 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 2293 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2295 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 2294 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2296 " move %0, $1 \n" \ 2295 " move %0, $1 \n" \
2297 " .set pop \n" \ 2296 " .set pop \n" \
2298 : "=r" (__res) \ 2297 : "=r" (__res) \
@@ -2307,22 +2306,22 @@ do { \
2307 " .set noat \n" \ 2306 " .set noat \n" \
2308 " move $1, %0 \n" \ 2307 " move $1, %0 \n" \
2309 " # wrdsp $1, %x1 \n" \ 2308 " # wrdsp $1, %x1 \n" \
2310 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 2309 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2311 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 2310 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2312 " .set pop \n" \ 2311 " .set pop \n" \
2313 : \ 2312 : \
2314 : "r" (val), "i" (mask)); \ 2313 : "r" (val), "i" (mask)); \
2315} while (0) 2314} while (0)
2316 2315
2317#define _umips_dsp_mfxxx(ins) \ 2316#define _dsp_mfxxx(ins) \
2318({ \ 2317({ \
2319 unsigned long __treg; \ 2318 unsigned long __treg; \
2320 \ 2319 \
2321 __asm__ __volatile__( \ 2320 __asm__ __volatile__( \
2322 " .set push \n" \ 2321 " .set push \n" \
2323 " .set noat \n" \ 2322 " .set noat \n" \
2324 " .hword 0x0001 \n" \ 2323 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2325 " .hword %x1 \n" \ 2324 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2326 " move %0, $1 \n" \ 2325 " move %0, $1 \n" \
2327 " .set pop \n" \ 2326 " .set pop \n" \
2328 : "=r" (__treg) \ 2327 : "=r" (__treg) \
@@ -2330,101 +2329,28 @@ do { \
2330 __treg; \ 2329 __treg; \
2331}) 2330})
2332 2331
2333#define _umips_dsp_mtxxx(val, ins) \ 2332#define _dsp_mtxxx(val, ins) \
2334do { \ 2333do { \
2335 __asm__ __volatile__( \ 2334 __asm__ __volatile__( \
2336 " .set push \n" \ 2335 " .set push \n" \
2337 " .set noat \n" \ 2336 " .set noat \n" \
2338 " move $1, %0 \n" \ 2337 " move $1, %0 \n" \
2339 " .hword 0x0001 \n" \ 2338 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2340 " .hword %x1 \n" \ 2339 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2341 " .set pop \n" \ 2340 " .set pop \n" \
2342 : \ 2341 : \
2343 : "r" (val), "i" (ins)); \ 2342 : "r" (val), "i" (ins)); \
2344} while (0) 2343} while (0)
2345 2344
2346#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 2345#ifdef CONFIG_CPU_MICROMIPS
2347#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
2348
2349#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
2350#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
2351
2352#define mflo0() _umips_dsp_mflo(0)
2353#define mflo1() _umips_dsp_mflo(1)
2354#define mflo2() _umips_dsp_mflo(2)
2355#define mflo3() _umips_dsp_mflo(3)
2356
2357#define mfhi0() _umips_dsp_mfhi(0)
2358#define mfhi1() _umips_dsp_mfhi(1)
2359#define mfhi2() _umips_dsp_mfhi(2)
2360#define mfhi3() _umips_dsp_mfhi(3)
2361 2346
2362#define mtlo0(x) _umips_dsp_mtlo(x, 0) 2347#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2363#define mtlo1(x) _umips_dsp_mtlo(x, 1) 2348#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2364#define mtlo2(x) _umips_dsp_mtlo(x, 2)
2365#define mtlo3(x) _umips_dsp_mtlo(x, 3)
2366 2349
2367#define mthi0(x) _umips_dsp_mthi(x, 0) 2350#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2368#define mthi1(x) _umips_dsp_mthi(x, 1) 2351#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2369#define mthi2(x) _umips_dsp_mthi(x, 2)
2370#define mthi3(x) _umips_dsp_mthi(x, 3)
2371 2352
2372#else /* !CONFIG_CPU_MICROMIPS */ 2353#else /* !CONFIG_CPU_MICROMIPS */
2373#define rddsp(mask) \
2374({ \
2375 unsigned int __res; \
2376 \
2377 __asm__ __volatile__( \
2378 " .set push \n" \
2379 " .set noat \n" \
2380 " # rddsp $1, %x1 \n" \
2381 " .word 0x7c000cb8 | (%x1 << 16) \n" \
2382 " move %0, $1 \n" \
2383 " .set pop \n" \
2384 : "=r" (__res) \
2385 : "i" (mask)); \
2386 __res; \
2387})
2388
2389#define wrdsp(val, mask) \
2390do { \
2391 __asm__ __volatile__( \
2392 " .set push \n" \
2393 " .set noat \n" \
2394 " move $1, %0 \n" \
2395 " # wrdsp $1, %x1 \n" \
2396 " .word 0x7c2004f8 | (%x1 << 11) \n" \
2397 " .set pop \n" \
2398 : \
2399 : "r" (val), "i" (mask)); \
2400} while (0)
2401
2402#define _dsp_mfxxx(ins) \
2403({ \
2404 unsigned long __treg; \
2405 \
2406 __asm__ __volatile__( \
2407 " .set push \n" \
2408 " .set noat \n" \
2409 " .word (0x00000810 | %1) \n" \
2410 " move %0, $1 \n" \
2411 " .set pop \n" \
2412 : "=r" (__treg) \
2413 : "i" (ins)); \
2414 __treg; \
2415})
2416
2417#define _dsp_mtxxx(val, ins) \
2418do { \
2419 __asm__ __volatile__( \
2420 " .set push \n" \
2421 " .set noat \n" \
2422 " move $1, %0 \n" \
2423 " .word (0x00200011 | %1) \n" \
2424 " .set pop \n" \
2425 : \
2426 : "r" (val), "i" (ins)); \
2427} while (0)
2428 2354
2429#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 2355#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2430#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 2356#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
@@ -2432,6 +2358,8 @@ do { \
2432#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 2358#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2433#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 2359#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2434 2360
2361#endif /* CONFIG_CPU_MICROMIPS */
2362
2435#define mflo0() _dsp_mflo(0) 2363#define mflo0() _dsp_mflo(0)
2436#define mflo1() _dsp_mflo(1) 2364#define mflo1() _dsp_mflo(1)
2437#define mflo2() _dsp_mflo(2) 2365#define mflo2() _dsp_mflo(2)
@@ -2452,7 +2380,6 @@ do { \
2452#define mthi2(x) _dsp_mthi(x, 2) 2380#define mthi2(x) _dsp_mthi(x, 2)
2453#define mthi3(x) _dsp_mthi(x, 3) 2381#define mthi3(x) _dsp_mthi(x, 3)
2454 2382
2455#endif /* CONFIG_CPU_MICROMIPS */
2456#endif 2383#endif
2457 2384
2458/* 2385/*
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