diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2012-10-25 15:21:29 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2012-12-12 10:52:06 -0500 |
commit | 5456bd26ae0606a98bc937ec71c748f2de5a6a90 (patch) | |
tree | 8d7662bcf30131c138ac5e9b345726c68f3388d5 /arch/mips/cavium-octeon | |
parent | 4fe64af7da539bc58c9e571da5ef0eb4589c9a35 (diff) |
MIPS: Octeon: Simplify code by assuming CONFIG_64BIT is always set.
No 32-bit kernels supported on Octeon.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon')
-rw-r--r-- | arch/mips/cavium-octeon/octeon-memcpy.S | 27 | ||||
-rw-r--r-- | arch/mips/cavium-octeon/setup.c | 6 |
2 files changed, 0 insertions, 33 deletions
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S index db478dbb9c7b..0ba0eb96d9ac 100644 --- a/arch/mips/cavium-octeon/octeon-memcpy.S +++ b/arch/mips/cavium-octeon/octeon-memcpy.S | |||
@@ -79,11 +79,6 @@ | |||
79 | /* | 79 | /* |
80 | * Only on the 64-bit kernel we can made use of 64-bit registers. | 80 | * Only on the 64-bit kernel we can made use of 64-bit registers. |
81 | */ | 81 | */ |
82 | #ifdef CONFIG_64BIT | ||
83 | #define USE_DOUBLE | ||
84 | #endif | ||
85 | |||
86 | #ifdef USE_DOUBLE | ||
87 | 82 | ||
88 | #define LOAD ld | 83 | #define LOAD ld |
89 | #define LOADL ldl | 84 | #define LOADL ldl |
@@ -119,26 +114,6 @@ | |||
119 | #define t6 $14 | 114 | #define t6 $14 |
120 | #define t7 $15 | 115 | #define t7 $15 |
121 | 116 | ||
122 | #else | ||
123 | |||
124 | #define LOAD lw | ||
125 | #define LOADL lwl | ||
126 | #define LOADR lwr | ||
127 | #define STOREL swl | ||
128 | #define STORER swr | ||
129 | #define STORE sw | ||
130 | #define ADD addu | ||
131 | #define SUB subu | ||
132 | #define SRL srl | ||
133 | #define SLL sll | ||
134 | #define SRA sra | ||
135 | #define SLLV sllv | ||
136 | #define SRLV srlv | ||
137 | #define NBYTES 4 | ||
138 | #define LOG_NBYTES 2 | ||
139 | |||
140 | #endif /* USE_DOUBLE */ | ||
141 | |||
142 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | 117 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
143 | #define LDFIRST LOADR | 118 | #define LDFIRST LOADR |
144 | #define LDREST LOADL | 119 | #define LDREST LOADL |
@@ -395,12 +370,10 @@ EXC( sb t0, N(dst), s_exc_p1) | |||
395 | 370 | ||
396 | COPY_BYTE(0) | 371 | COPY_BYTE(0) |
397 | COPY_BYTE(1) | 372 | COPY_BYTE(1) |
398 | #ifdef USE_DOUBLE | ||
399 | COPY_BYTE(2) | 373 | COPY_BYTE(2) |
400 | COPY_BYTE(3) | 374 | COPY_BYTE(3) |
401 | COPY_BYTE(4) | 375 | COPY_BYTE(4) |
402 | COPY_BYTE(5) | 376 | COPY_BYTE(5) |
403 | #endif | ||
404 | EXC( lb t0, NBYTES-2(src), l_exc) | 377 | EXC( lb t0, NBYTES-2(src), l_exc) |
405 | SUB len, len, 1 | 378 | SUB len, len, 1 |
406 | jr ra | 379 | jr ra |
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index c0c2d14be423..67aa3b942f06 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c | |||
@@ -666,16 +666,10 @@ void __init plat_mem_setup(void) | |||
666 | cvmx_bootmem_lock(); | 666 | cvmx_bootmem_lock(); |
667 | while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) | 667 | while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) |
668 | && (total < MAX_MEMORY)) { | 668 | && (total < MAX_MEMORY)) { |
669 | #ifdef CONFIG_64BIT | ||
670 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, | 669 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, |
671 | __pa_symbol(&__init_end), -1, | 670 | __pa_symbol(&__init_end), -1, |
672 | 0x100000, | 671 | 0x100000, |
673 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | 672 | CVMX_BOOTMEM_FLAG_NO_LOCKING); |
674 | #else | ||
675 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, | ||
676 | 0x100000, | ||
677 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | ||
678 | #endif | ||
679 | if (memory >= 0) { | 673 | if (memory >= 0) { |
680 | u64 size = mem_alloc_size; | 674 | u64 size = mem_alloc_size; |
681 | 675 | ||