aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/boot
diff options
context:
space:
mode:
authorAaro Koskinen <aaro.koskinen@iki.fi>2016-03-08 16:32:26 -0500
committerRalf Baechle <ralf@linux-mips.org>2016-05-13 08:01:44 -0400
commitfa0a497b9e13cd3c494dbbb93b156752fd15fdd2 (patch)
treeb2e5c84be268cf079a4116fb184abf74b006fc76 /arch/mips/boot
parent99a7a234c890177c4d4f2b0fb02317ef19c364a2 (diff)
MIPS: Octeon: Add DTS for D-Link DSR-1000N
Add DTS for D-Link DSR-1000N that is usable as is without any "pruning" with APPENDED_DTB. Split out the common parts from octeon_3xxx.dts into octeon_3xxx.dtsi. Compared to builtin generic DTB, we can specificy fixed links properly and avoid probing non-existent I2C devices. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12840/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/boot')
-rw-r--r--arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts78
-rw-r--r--arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts205
-rw-r--r--arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi231
3 files changed, 312 insertions, 202 deletions
diff --git a/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts
new file mode 100644
index 000000000000..d6bc994f736f
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts
@@ -0,0 +1,78 @@
1/*
2 * Device tree source for D-Link DSR-1000N.
3 *
4 * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/include/ "octeon_3xxx.dtsi"
12
13/ {
14 model = "dlink,dsr-1000n";
15
16 soc@0 {
17 smi0: mdio@1180000001800 {
18 phy8: ethernet-phy@8 {
19 reg = <8>;
20 compatible = "ethernet-phy-ieee802.3-c22";
21 };
22 };
23
24 pip: pip@11800a0000000 {
25 interface@0 {
26 ethernet@0 {
27 fixed-link {
28 speed = <1000>;
29 full-duplex;
30 };
31 };
32 ethernet@1 {
33 fixed-link {
34 speed = <1000>;
35 full-duplex;
36 };
37 };
38 ethernet@2 {
39 phy-handle = <&phy8>;
40 };
41 };
42 };
43
44 twsi0: i2c@1180000001000 {
45 rtc@68 {
46 compatible = "dallas,ds1337";
47 reg = <0x68>;
48 };
49 };
50
51 uart0: serial@1180000000800 {
52 clock-frequency = <500000000>;
53 };
54
55 usbn: usbn@1180068000000 {
56 refclk-frequency = <12000000>;
57 refclk-type = "crystal";
58 };
59 };
60
61 leds {
62 compatible = "gpio-leds";
63
64 usb1 {
65 label = "usb1";
66 gpios = <&gpio 9 1>; /* Active low */
67 };
68
69 usb2 {
70 label = "usb2";
71 gpios = <&gpio 10 1>; /* Active low */
72 };
73 };
74
75 aliases {
76 pip = &pip;
77 };
78};
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
index 9c48e0586ba7..de61f02d3ef6 100644
--- a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
@@ -1,4 +1,3 @@
1/dts-v1/;
2/* 1/*
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. 2 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
4 * 3 *
@@ -6,56 +5,12 @@
6 * use. Because of this, it contains a super-set of the available 5 * use. Because of this, it contains a super-set of the available
7 * devices and properties. 6 * devices and properties.
8 */ 7 */
9/ {
10 compatible = "cavium,octeon-3860";
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&ciu>;
14
15 soc@0 {
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges; /* Direct mapping */
20
21 ciu: interrupt-controller@1070000000000 {
22 compatible = "cavium,octeon-3860-ciu";
23 interrupt-controller;
24 /* Interrupts are specified by two parts:
25 * 1) Controller register (0 or 1)
26 * 2) Bit within the register (0..63)
27 */
28 #interrupt-cells = <2>;
29 reg = <0x10700 0x00000000 0x0 0x7000>;
30 };
31 8
32 gpio: gpio-controller@1070000000800 { 9/include/ "octeon_3xxx.dtsi"
33 #gpio-cells = <2>;
34 compatible = "cavium,octeon-3860-gpio";
35 reg = <0x10700 0x00000800 0x0 0x100>;
36 gpio-controller;
37 /* Interrupts are specified by two parts:
38 * 1) GPIO pin number (0..15)
39 * 2) Triggering (1 - edge rising
40 * 2 - edge falling
41 * 4 - level active high
42 * 8 - level active low)
43 */
44 interrupt-controller;
45 #interrupt-cells = <2>;
46 /* The GPIO pin connect to 16 consecutive CUI bits */
47 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
48 <0 20>, <0 21>, <0 22>, <0 23>,
49 <0 24>, <0 25>, <0 26>, <0 27>,
50 <0 28>, <0 29>, <0 30>, <0 31>;
51 };
52 10
11/ {
12 soc@0 {
53 smi0: mdio@1180000001800 { 13 smi0: mdio@1180000001800 {
54 compatible = "cavium,octeon-3860-mdio";
55 #address-cells = <1>;
56 #size-cells = <0>;
57 reg = <0x11800 0x00001800 0x0 0x40>;
58
59 phy0: ethernet-phy@0 { 14 phy0: ethernet-phy@0 {
60 compatible = "marvell,88e1118"; 15 compatible = "marvell,88e1118";
61 marvell,reg-init = 16 marvell,reg-init =
@@ -220,35 +175,16 @@
220 }; 175 };
221 176
222 pip: pip@11800a0000000 { 177 pip: pip@11800a0000000 {
223 compatible = "cavium,octeon-3860-pip";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x11800 0xa0000000 0x0 0x2000>;
227
228 interface@0 { 178 interface@0 {
229 compatible = "cavium,octeon-3860-pip-interface";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <0>; /* interface */
233
234 ethernet@0 { 179 ethernet@0 {
235 compatible = "cavium,octeon-3860-pip-port";
236 reg = <0x0>; /* Port */
237 local-mac-address = [ 00 00 00 00 00 00 ];
238 phy-handle = <&phy2>; 180 phy-handle = <&phy2>;
239 cavium,alt-phy-handle = <&phy100>; 181 cavium,alt-phy-handle = <&phy100>;
240 }; 182 };
241 ethernet@1 { 183 ethernet@1 {
242 compatible = "cavium,octeon-3860-pip-port";
243 reg = <0x1>; /* Port */
244 local-mac-address = [ 00 00 00 00 00 00 ];
245 phy-handle = <&phy3>; 184 phy-handle = <&phy3>;
246 cavium,alt-phy-handle = <&phy101>; 185 cavium,alt-phy-handle = <&phy101>;
247 }; 186 };
248 ethernet@2 { 187 ethernet@2 {
249 compatible = "cavium,octeon-3860-pip-port";
250 reg = <0x2>; /* Port */
251 local-mac-address = [ 00 00 00 00 00 00 ];
252 phy-handle = <&phy4>; 188 phy-handle = <&phy4>;
253 cavium,alt-phy-handle = <&phy102>; 189 cavium,alt-phy-handle = <&phy102>;
254 }; 190 };
@@ -322,11 +258,6 @@
322 }; 258 };
323 259
324 interface@1 { 260 interface@1 {
325 compatible = "cavium,octeon-3860-pip-interface";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <1>; /* interface */
329
330 ethernet@0 { 261 ethernet@0 {
331 compatible = "cavium,octeon-3860-pip-port"; 262 compatible = "cavium,octeon-3860-pip-port";
332 reg = <0x0>; /* Port */ 263 reg = <0x0>; /* Port */
@@ -355,13 +286,6 @@
355 }; 286 };
356 287
357 twsi0: i2c@1180000001000 { 288 twsi0: i2c@1180000001000 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 compatible = "cavium,octeon-3860-twsi";
361 reg = <0x11800 0x00001000 0x0 0x200>;
362 interrupts = <0 45>;
363 clock-frequency = <100000>;
364
365 rtc@68 { 289 rtc@68 {
366 compatible = "dallas,ds1337"; 290 compatible = "dallas,ds1337";
367 reg = <0x68>; 291 reg = <0x68>;
@@ -381,15 +305,6 @@
381 clock-frequency = <100000>; 305 clock-frequency = <100000>;
382 }; 306 };
383 307
384 uart0: serial@1180000000800 {
385 compatible = "cavium,octeon-3860-uart","ns16550";
386 reg = <0x11800 0x00000800 0x0 0x400>;
387 clock-frequency = <0>;
388 current-speed = <115200>;
389 reg-shift = <3>;
390 interrupts = <0 34>;
391 };
392
393 uart1: serial@1180000000c00 { 308 uart1: serial@1180000000c00 {
394 compatible = "cavium,octeon-3860-uart","ns16550"; 309 compatible = "cavium,octeon-3860-uart","ns16550";
395 reg = <0x11800 0x00000c00 0x0 0x400>; 310 reg = <0x11800 0x00000c00 0x0 0x400>;
@@ -409,98 +324,6 @@
409 }; 324 };
410 325
411 bootbus: bootbus@1180000000000 { 326 bootbus: bootbus@1180000000000 {
412 compatible = "cavium,octeon-3860-bootbus";
413 reg = <0x11800 0x00000000 0x0 0x200>;
414 /* The chip select number and offset */
415 #address-cells = <2>;
416 /* The size of the chip select region */
417 #size-cells = <1>;
418 ranges = <0 0 0x0 0x1f400000 0xc00000>,
419 <1 0 0x10000 0x30000000 0>,
420 <2 0 0x10000 0x40000000 0>,
421 <3 0 0x10000 0x50000000 0>,
422 <4 0 0x0 0x1d020000 0x10000>,
423 <5 0 0x0 0x1d040000 0x10000>,
424 <6 0 0x0 0x1d050000 0x10000>,
425 <7 0 0x10000 0x90000000 0>;
426
427 cavium,cs-config@0 {
428 compatible = "cavium,octeon-3860-bootbus-config";
429 cavium,cs-index = <0>;
430 cavium,t-adr = <20>;
431 cavium,t-ce = <60>;
432 cavium,t-oe = <60>;
433 cavium,t-we = <45>;
434 cavium,t-rd-hld = <35>;
435 cavium,t-wr-hld = <45>;
436 cavium,t-pause = <0>;
437 cavium,t-wait = <0>;
438 cavium,t-page = <35>;
439 cavium,t-rd-dly = <0>;
440
441 cavium,pages = <0>;
442 cavium,bus-width = <8>;
443 };
444 cavium,cs-config@4 {
445 compatible = "cavium,octeon-3860-bootbus-config";
446 cavium,cs-index = <4>;
447 cavium,t-adr = <320>;
448 cavium,t-ce = <320>;
449 cavium,t-oe = <320>;
450 cavium,t-we = <320>;
451 cavium,t-rd-hld = <320>;
452 cavium,t-wr-hld = <320>;
453 cavium,t-pause = <320>;
454 cavium,t-wait = <320>;
455 cavium,t-page = <320>;
456 cavium,t-rd-dly = <0>;
457
458 cavium,pages = <0>;
459 cavium,bus-width = <8>;
460 };
461 cavium,cs-config@5 {
462 compatible = "cavium,octeon-3860-bootbus-config";
463 cavium,cs-index = <5>;
464 cavium,t-adr = <5>;
465 cavium,t-ce = <300>;
466 cavium,t-oe = <125>;
467 cavium,t-we = <150>;
468 cavium,t-rd-hld = <100>;
469 cavium,t-wr-hld = <30>;
470 cavium,t-pause = <0>;
471 cavium,t-wait = <30>;
472 cavium,t-page = <320>;
473 cavium,t-rd-dly = <0>;
474
475 cavium,pages = <0>;
476 cavium,bus-width = <16>;
477 };
478 cavium,cs-config@6 {
479 compatible = "cavium,octeon-3860-bootbus-config";
480 cavium,cs-index = <6>;
481 cavium,t-adr = <5>;
482 cavium,t-ce = <300>;
483 cavium,t-oe = <270>;
484 cavium,t-we = <150>;
485 cavium,t-rd-hld = <100>;
486 cavium,t-wr-hld = <70>;
487 cavium,t-pause = <0>;
488 cavium,t-wait = <0>;
489 cavium,t-page = <320>;
490 cavium,t-rd-dly = <0>;
491
492 cavium,pages = <0>;
493 cavium,wait-mode;
494 cavium,bus-width = <16>;
495 };
496
497 flash0: nor@0,0 {
498 compatible = "cfi-flash";
499 reg = <0 0 0x800000>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 };
503
504 led0: led-display@4,0 { 327 led0: led-display@4,0 {
505 compatible = "avago,hdsp-253x"; 328 compatible = "avago,hdsp-253x";
506 reg = <4 0x20 0x20>, <4 0 0x20>; 329 reg = <4 0x20 0x20>, <4 0 0x20>;
@@ -515,17 +338,6 @@
515 }; 338 };
516 }; 339 };
517 340
518 dma0: dma-engine@1180000000100 {
519 compatible = "cavium,octeon-5750-bootbus-dma";
520 reg = <0x11800 0x00000100 0x0 0x8>;
521 interrupts = <0 63>;
522 };
523 dma1: dma-engine@1180000000108 {
524 compatible = "cavium,octeon-5750-bootbus-dma";
525 reg = <0x11800 0x00000108 0x0 0x8>;
526 interrupts = <0 63>;
527 };
528
529 uctl: uctl@118006f000000 { 341 uctl: uctl@118006f000000 {
530 compatible = "cavium,octeon-6335-uctl"; 342 compatible = "cavium,octeon-6335-uctl";
531 reg = <0x11800 0x6f000000 0x0 0x100>; 343 reg = <0x11800 0x6f000000 0x0 0x100>;
@@ -552,21 +364,10 @@
552 }; 364 };
553 365
554 usbn: usbn@1180068000000 { 366 usbn: usbn@1180068000000 {
555 compatible = "cavium,octeon-5750-usbn";
556 reg = <0x11800 0x68000000 0x0 0x1000>;
557 ranges; /* Direct mapping */
558 #address-cells = <2>;
559 #size-cells = <2>;
560 /* 12MHz, 24MHz and 48MHz allowed */ 367 /* 12MHz, 24MHz and 48MHz allowed */
561 refclk-frequency = <12000000>; 368 refclk-frequency = <12000000>;
562 /* Either "crystal" or "external" */ 369 /* Either "crystal" or "external" */
563 refclk-type = "crystal"; 370 refclk-type = "crystal";
564
565 usbc@16f0010000000 {
566 compatible = "cavium,octeon-5750-usbc";
567 reg = <0x16f00 0x10000000 0x0 0x80000>;
568 interrupts = <0 56>;
569 };
570 }; 371 };
571 }; 372 };
572 373
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi
new file mode 100644
index 000000000000..5302148e05a3
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi
@@ -0,0 +1,231 @@
1/* OCTEON 3XXX DTS common parts. */
2
3/dts-v1/;
4
5/ {
6 compatible = "cavium,octeon-3860";
7 #address-cells = <2>;
8 #size-cells = <2>;
9 interrupt-parent = <&ciu>;
10
11 soc@0 {
12 compatible = "simple-bus";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 ranges; /* Direct mapping */
16
17 ciu: interrupt-controller@1070000000000 {
18 compatible = "cavium,octeon-3860-ciu";
19 interrupt-controller;
20 /* Interrupts are specified by two parts:
21 * 1) Controller register (0 or 1)
22 * 2) Bit within the register (0..63)
23 */
24 #interrupt-cells = <2>;
25 reg = <0x10700 0x00000000 0x0 0x7000>;
26 };
27
28 gpio: gpio-controller@1070000000800 {
29 #gpio-cells = <2>;
30 compatible = "cavium,octeon-3860-gpio";
31 reg = <0x10700 0x00000800 0x0 0x100>;
32 gpio-controller;
33 /* Interrupts are specified by two parts:
34 * 1) GPIO pin number (0..15)
35 * 2) Triggering (1 - edge rising
36 * 2 - edge falling
37 * 4 - level active high
38 * 8 - level active low)
39 */
40 interrupt-controller;
41 #interrupt-cells = <2>;
42 /* The GPIO pin connect to 16 consecutive CUI bits */
43 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
44 <0 20>, <0 21>, <0 22>, <0 23>,
45 <0 24>, <0 25>, <0 26>, <0 27>,
46 <0 28>, <0 29>, <0 30>, <0 31>;
47 };
48
49 smi0: mdio@1180000001800 {
50 compatible = "cavium,octeon-3860-mdio";
51 #address-cells = <1>;
52 #size-cells = <0>;
53 reg = <0x11800 0x00001800 0x0 0x40>;
54 };
55
56 pip: pip@11800a0000000 {
57 compatible = "cavium,octeon-3860-pip";
58 #address-cells = <1>;
59 #size-cells = <0>;
60 reg = <0x11800 0xa0000000 0x0 0x2000>;
61
62 interface@0 {
63 compatible = "cavium,octeon-3860-pip-interface";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 reg = <0>; /* interface */
67
68 ethernet@0 {
69 compatible = "cavium,octeon-3860-pip-port";
70 reg = <0x0>; /* Port */
71 local-mac-address = [ 00 00 00 00 00 00 ];
72 };
73 ethernet@1 {
74 compatible = "cavium,octeon-3860-pip-port";
75 reg = <0x1>; /* Port */
76 local-mac-address = [ 00 00 00 00 00 00 ];
77 };
78 ethernet@2 {
79 compatible = "cavium,octeon-3860-pip-port";
80 reg = <0x2>; /* Port */
81 local-mac-address = [ 00 00 00 00 00 00 ];
82 };
83 };
84
85 interface@1 {
86 compatible = "cavium,octeon-3860-pip-interface";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <1>; /* interface */
90 };
91 };
92
93 twsi0: i2c@1180000001000 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 compatible = "cavium,octeon-3860-twsi";
97 reg = <0x11800 0x00001000 0x0 0x200>;
98 interrupts = <0 45>;
99 clock-frequency = <100000>;
100 };
101
102 uart0: serial@1180000000800 {
103 compatible = "cavium,octeon-3860-uart","ns16550";
104 reg = <0x11800 0x00000800 0x0 0x400>;
105 clock-frequency = <0>;
106 current-speed = <115200>;
107 reg-shift = <3>;
108 interrupts = <0 34>;
109 };
110
111 bootbus: bootbus@1180000000000 {
112 compatible = "cavium,octeon-3860-bootbus";
113 reg = <0x11800 0x00000000 0x0 0x200>;
114 /* The chip select number and offset */
115 #address-cells = <2>;
116 /* The size of the chip select region */
117 #size-cells = <1>;
118 ranges = <0 0 0x0 0x1f400000 0xc00000>,
119 <1 0 0x10000 0x30000000 0>,
120 <2 0 0x10000 0x40000000 0>,
121 <3 0 0x10000 0x50000000 0>,
122 <4 0 0x0 0x1d020000 0x10000>,
123 <5 0 0x0 0x1d040000 0x10000>,
124 <6 0 0x0 0x1d050000 0x10000>,
125 <7 0 0x10000 0x90000000 0>;
126
127 cavium,cs-config@0 {
128 compatible = "cavium,octeon-3860-bootbus-config";
129 cavium,cs-index = <0>;
130 cavium,t-adr = <20>;
131 cavium,t-ce = <60>;
132 cavium,t-oe = <60>;
133 cavium,t-we = <45>;
134 cavium,t-rd-hld = <35>;
135 cavium,t-wr-hld = <45>;
136 cavium,t-pause = <0>;
137 cavium,t-wait = <0>;
138 cavium,t-page = <35>;
139 cavium,t-rd-dly = <0>;
140
141 cavium,pages = <0>;
142 cavium,bus-width = <8>;
143 };
144 cavium,cs-config@4 {
145 compatible = "cavium,octeon-3860-bootbus-config";
146 cavium,cs-index = <4>;
147 cavium,t-adr = <320>;
148 cavium,t-ce = <320>;
149 cavium,t-oe = <320>;
150 cavium,t-we = <320>;
151 cavium,t-rd-hld = <320>;
152 cavium,t-wr-hld = <320>;
153 cavium,t-pause = <320>;
154 cavium,t-wait = <320>;
155 cavium,t-page = <320>;
156 cavium,t-rd-dly = <0>;
157
158 cavium,pages = <0>;
159 cavium,bus-width = <8>;
160 };
161 cavium,cs-config@5 {
162 compatible = "cavium,octeon-3860-bootbus-config";
163 cavium,cs-index = <5>;
164 cavium,t-adr = <5>;
165 cavium,t-ce = <300>;
166 cavium,t-oe = <125>;
167 cavium,t-we = <150>;
168 cavium,t-rd-hld = <100>;
169 cavium,t-wr-hld = <30>;
170 cavium,t-pause = <0>;
171 cavium,t-wait = <30>;
172 cavium,t-page = <320>;
173 cavium,t-rd-dly = <0>;
174
175 cavium,pages = <0>;
176 cavium,bus-width = <16>;
177 };
178 cavium,cs-config@6 {
179 compatible = "cavium,octeon-3860-bootbus-config";
180 cavium,cs-index = <6>;
181 cavium,t-adr = <5>;
182 cavium,t-ce = <300>;
183 cavium,t-oe = <270>;
184 cavium,t-we = <150>;
185 cavium,t-rd-hld = <100>;
186 cavium,t-wr-hld = <70>;
187 cavium,t-pause = <0>;
188 cavium,t-wait = <0>;
189 cavium,t-page = <320>;
190 cavium,t-rd-dly = <0>;
191
192 cavium,pages = <0>;
193 cavium,wait-mode;
194 cavium,bus-width = <16>;
195 };
196
197 flash0: nor@0,0 {
198 compatible = "cfi-flash";
199 reg = <0 0 0x800000>;
200 #address-cells = <1>;
201 #size-cells = <1>;
202 };
203 };
204
205 dma0: dma-engine@1180000000100 {
206 compatible = "cavium,octeon-5750-bootbus-dma";
207 reg = <0x11800 0x00000100 0x0 0x8>;
208 interrupts = <0 63>;
209 };
210
211 dma1: dma-engine@1180000000108 {
212 compatible = "cavium,octeon-5750-bootbus-dma";
213 reg = <0x11800 0x00000108 0x0 0x8>;
214 interrupts = <0 63>;
215 };
216
217 usbn: usbn@1180068000000 {
218 compatible = "cavium,octeon-5750-usbn";
219 reg = <0x11800 0x68000000 0x0 0x1000>;
220 ranges; /* Direct mapping */
221 #address-cells = <2>;
222 #size-cells = <2>;
223
224 usbc@16f0010000000 {
225 compatible = "cavium,octeon-5750-usbc";
226 reg = <0x16f00 0x10000000 0x0 0x80000>;
227 interrupts = <0 56>;
228 };
229 };
230 };
231};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 14:02:35 -0400