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authorLinus Torvalds <torvalds@linux-foundation.org>2016-01-24 15:50:56 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2016-01-24 15:50:56 -0500
commite2464688b59c6ae9928f385dabf5355e30cff298 (patch)
tree1039fa8c818e6ac16d6f1504c28e80bfe902b0f3 /arch/mips/boot
parente1c10879ed59436cde537b723545430b04d4dec0 (diff)
parent07d17f09691e549fac0101333eebe0161a472b50 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for 4.5 plus some 4.4 fixes. The executive summary: - ATH79 platform improvments, use DT bindings for the ATH79 USB PHY. - Avoid useless rebuilds for zboot. - jz4780: Add NEMC, BCH and NAND device tree nodes - Initial support for the MicroChip's DT platform. As all the device drivers are missing this is still of limited use. - Some Loongson3 cleanups. - The unavoidable whitespace polishing. - Reduce clock skew when synchronizing the CPU cycle counters on CPU startup. - Add MIPS R6 fixes. - Lots of cleanups across arch/mips as fallout from KVM. - Lots of minor fixes and changes for IEEE 754-2008 support to the FPU emulator / fp-assist software. - Minor Ralink, BCM47xx and bcm963xx platform support improvments. - Support SMP on BCM63168" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits) MIPS: zboot: Add support for serial debug using the PROM MIPS: zboot: Avoid useless rebuilds MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function MIPS: bcm963xx: Update bcm_tag field image_sequence MIPS: bcm963xx: Move extended flash address to bcm_tag header file MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure MIPS: bcm63xx: nvram: Use nvram structure definition from header file MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure MAINTAINERS: Add KVM for MIPS entry MIPS: KVM: Add missing newline to kvm_err() MIPS: Move KVM specific opcodes into asm/inst.h MIPS: KVM: Use cacheops.h definitions MIPS: Break down cacheops.h definitions MIPS: Use EXCCODE_ constants with set_except_vector() MIPS: Update trap codes MIPS: Move Cause.ExcCode trap codes to mipsregs.h MIPS: KVM: Make kvm_mips_{init,exit}() static MIPS: KVM: Refactor added offsetof()s MIPS: KVM: Convert EXPORT_SYMBOL to _GPL ...
Diffstat (limited to 'arch/mips/boot')
-rw-r--r--arch/mips/boot/compressed/Makefile15
-rw-r--r--arch/mips/boot/compressed/uart-prom.c7
-rw-r--r--arch/mips/boot/dts/Makefile1
-rw-r--r--arch/mips/boot/dts/brcm/bcm6328.dtsi9
-rw-r--r--arch/mips/boot/dts/brcm/bcm6368.dtsi22
-rw-r--r--arch/mips/boot/dts/ingenic/ci20.dts64
-rw-r--r--arch/mips/boot/dts/ingenic/jz4780.dtsi26
-rw-r--r--arch/mips/boot/dts/pic32/Makefile12
-rw-r--r--arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi236
-rw-r--r--arch/mips/boot/dts/pic32/pic32mzda.dtsi281
-rw-r--r--arch/mips/boot/dts/pic32/pic32mzda_sk.dts151
-rw-r--r--arch/mips/boot/dts/qca/ar9132.dtsi26
-rw-r--r--arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts8
13 files changed, 852 insertions, 6 deletions
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index d5bdee115f22..4eff1ef02eff 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -29,20 +29,23 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
29 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \ 29 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
30 -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS) 30 -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
31 31
32targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o
33
34# decompressor objects (linked with vmlinuz) 32# decompressor objects (linked with vmlinuz)
35vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o 33vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o
36 34
37ifdef CONFIG_DEBUG_ZBOOT 35ifdef CONFIG_DEBUG_ZBOOT
38vmlinuzobjs-$(CONFIG_DEBUG_ZBOOT) += $(obj)/dbg.o 36vmlinuzobjs-$(CONFIG_DEBUG_ZBOOT) += $(obj)/dbg.o
39vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o 37vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
38vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM) += $(obj)/uart-prom.o
40vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o 39vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
41endif 40endif
42 41
43ifdef CONFIG_KERNEL_XZ 42vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o
44vmlinuzobjs-y += $(obj)/../../lib/ashldi3.o 43
45endif 44$(obj)/ashldi3.o: KBUILD_CFLAGS += -I$(srctree)/arch/mips/lib
45$(obj)/ashldi3.c: $(srctree)/arch/mips/lib/ashldi3.c
46 $(call cmd,shipped)
47
48targets := $(notdir $(vmlinuzobjs-y))
46 49
47targets += vmlinux.bin 50targets += vmlinux.bin
48OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S 51OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
@@ -60,7 +63,7 @@ targets += vmlinux.bin.z
60$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE 63$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
61 $(call if_changed,$(tool_y)) 64 $(call if_changed,$(tool_y))
62 65
63targets += piggy.o 66targets += piggy.o dummy.o
64OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \ 67OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
65 --set-section-flags=.image=contents,alloc,load,readonly,data 68 --set-section-flags=.image=contents,alloc,load,readonly,data
66$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE 69$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
diff --git a/arch/mips/boot/compressed/uart-prom.c b/arch/mips/boot/compressed/uart-prom.c
new file mode 100644
index 000000000000..1c3d51bc90bb
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-prom.c
@@ -0,0 +1,7 @@
1
2extern void prom_putchar(unsigned char ch);
3
4void putc(char c)
5{
6 prom_putchar(c);
7}
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index a0bf516ec394..fc7a0a98e9bf 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += ingenic
4dts-dirs += lantiq 4dts-dirs += lantiq
5dts-dirs += mti 5dts-dirs += mti
6dts-dirs += netlogic 6dts-dirs += netlogic
7dts-dirs += pic32
7dts-dirs += qca 8dts-dirs += qca
8dts-dirs += ralink 9dts-dirs += ralink
9dts-dirs += xilfpga 10dts-dirs += xilfpga
diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi
index d52ce3d07f16..459b9b252c3b 100644
--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
@@ -31,6 +31,7 @@
31 }; 31 };
32 32
33 aliases { 33 aliases {
34 leds0 = &leds0;
34 uart0 = &uart0; 35 uart0 = &uart0;
35 }; 36 };
36 37
@@ -81,5 +82,13 @@
81 offset = <0x28>; 82 offset = <0x28>;
82 mask = <0x1>; 83 mask = <0x1>;
83 }; 84 };
85
86 leds0: led-controller@10000800 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "brcm,bcm6328-leds";
90 reg = <0x10000800 0x24>;
91 status = "disabled";
92 };
84 }; 93 };
85}; 94};
diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi
index 45152bc22117..9c8d3fe28b31 100644
--- a/arch/mips/boot/dts/brcm/bcm6368.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi
@@ -32,6 +32,7 @@
32 }; 32 };
33 33
34 aliases { 34 aliases {
35 leds0 = &leds0;
35 uart0 = &uart0; 36 uart0 = &uart0;
36 }; 37 };
37 38
@@ -50,6 +51,19 @@
50 compatible = "simple-bus"; 51 compatible = "simple-bus";
51 ranges; 52 ranges;
52 53
54 periph_cntl: syscon@10000000 {
55 compatible = "syscon";
56 reg = <0x10000000 0x14>;
57 little-endian;
58 };
59
60 reboot: syscon-reboot@10000008 {
61 compatible = "syscon-reboot";
62 regmap = <&periph_cntl>;
63 offset = <0x8>;
64 mask = <0x1>;
65 };
66
53 periph_intc: periph_intc@10000020 { 67 periph_intc: periph_intc@10000020 {
54 compatible = "brcm,bcm3380-l2-intc"; 68 compatible = "brcm,bcm3380-l2-intc";
55 reg = <0x10000024 0x4 0x1000002c 0x4>, 69 reg = <0x10000024 0x4 0x1000002c 0x4>,
@@ -62,6 +76,14 @@
62 interrupts = <2>; 76 interrupts = <2>;
63 }; 77 };
64 78
79 leds0: led-controller@100000d0 {
80 #address-cells = <1>;
81 #size-cells = <0>;
82 compatible = "brcm,bcm6358-leds";
83 reg = <0x100000d0 0x8>;
84 status = "disabled";
85 };
86
65 uart0: serial@10000100 { 87 uart0: serial@10000100 {
66 compatible = "brcm,bcm6345-uart"; 88 compatible = "brcm,bcm6345-uart";
67 reg = <0x10000100 0x18>; 89 reg = <0x10000100 0x18>;
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 9fcb9e7d1f57..1652d8d60b1e 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -42,3 +42,67 @@
42&uart4 { 42&uart4 {
43 status = "okay"; 43 status = "okay";
44}; 44};
45
46&nemc {
47 status = "okay";
48
49 nandc: nand-controller@1 {
50 compatible = "ingenic,jz4780-nand";
51 reg = <1 0 0x1000000>;
52
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 ingenic,bch-controller = <&bch>;
57
58 ingenic,nemc-tAS = <10>;
59 ingenic,nemc-tAH = <5>;
60 ingenic,nemc-tBP = <10>;
61 ingenic,nemc-tAW = <15>;
62 ingenic,nemc-tSTRV = <100>;
63
64 nand@1 {
65 reg = <1>;
66
67 nand-ecc-step-size = <1024>;
68 nand-ecc-strength = <24>;
69 nand-ecc-mode = "hw";
70 nand-on-flash-bbt;
71
72 partitions {
73 compatible = "fixed-partitions";
74 #address-cells = <2>;
75 #size-cells = <2>;
76
77 partition@0 {
78 label = "u-boot-spl";
79 reg = <0x0 0x0 0x0 0x800000>;
80 };
81
82 partition@0x800000 {
83 label = "u-boot";
84 reg = <0x0 0x800000 0x0 0x200000>;
85 };
86
87 partition@0xa00000 {
88 label = "u-boot-env";
89 reg = <0x0 0xa00000 0x0 0x200000>;
90 };
91
92 partition@0xc00000 {
93 label = "boot";
94 reg = <0x0 0xc00000 0x0 0x4000000>;
95 };
96
97 partition@0x8c00000 {
98 label = "system";
99 reg = <0x0 0x4c00000 0x1 0xfb400000>;
100 };
101 };
102 };
103 };
104};
105
106&bch {
107 status = "okay";
108};
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 65389f602733..b868b429add2 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -108,4 +108,30 @@
108 108
109 status = "disabled"; 109 status = "disabled";
110 }; 110 };
111
112 nemc: nemc@13410000 {
113 compatible = "ingenic,jz4780-nemc";
114 reg = <0x13410000 0x10000>;
115 #address-cells = <2>;
116 #size-cells = <1>;
117 ranges = <1 0 0x1b000000 0x1000000
118 2 0 0x1a000000 0x1000000
119 3 0 0x19000000 0x1000000
120 4 0 0x18000000 0x1000000
121 5 0 0x17000000 0x1000000
122 6 0 0x16000000 0x1000000>;
123
124 clocks = <&cgu JZ4780_CLK_NEMC>;
125
126 status = "disabled";
127 };
128
129 bch: bch@134d0000 {
130 compatible = "ingenic,jz4780-bch";
131 reg = <0x134d0000 0x10000>;
132
133 clocks = <&cgu JZ4780_CLK_BCH>;
134
135 status = "disabled";
136 };
111}; 137};
diff --git a/arch/mips/boot/dts/pic32/Makefile b/arch/mips/boot/dts/pic32/Makefile
new file mode 100644
index 000000000000..7ac790551ec9
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/Makefile
@@ -0,0 +1,12 @@
1dtb-$(CONFIG_DTB_PIC32_MZDA_SK) += pic32mzda_sk.dtb
2
3dtb-$(CONFIG_DTB_PIC32_NONE) += \
4 pic32mzda_sk.dtb
5
6obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
7
8# Force kbuild to make empty built-in.o if necessary
9obj- += dummy.o
10
11always := $(dtb-y)
12clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
new file mode 100644
index 000000000000..ef1335012f43
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
@@ -0,0 +1,236 @@
1/*
2 * Device Tree Source for PIC32MZDA clock data
3 *
4 * Purna Chandra Mandal <purna.mandal@microchip.com>
5 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/* all fixed rate clocks */
11
12/ {
13 POSC:posc_clk { /* On-chip primary oscillator */
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 };
18
19 FRC:frc_clk { /* internal FRC oscillator */
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
22 clock-frequency = <8000000>;
23 };
24
25 BFRC:bfrc_clk { /* internal backup FRC oscillator */
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <8000000>;
29 };
30
31 LPRC:lprc_clk { /* internal low-power FRC oscillator */
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <32000>;
35 };
36
37 /* UPLL provides clock to USBCORE */
38 UPLL:usb_phy_clk {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <24000000>;
42 clock-output-names = "usbphy_clk";
43 };
44
45 TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <4000000>;
49 status = "disabled";
50 };
51
52 /* external clock input on REFCLKIx pin */
53 REFIx:refix_clk {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <24000000>;
57 status = "disabled";
58 };
59
60 /* PIC32 specific clks */
61 pic32_clktree {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 reg = <0x1f801200 0x200>;
65 compatible = "microchip,pic32mzda-clk";
66 ranges = <0 0x1f801200 0x200>;
67
68 /* secondary oscillator; external input on SOSCI pin */
69 SOSC:sosc_clk@0 {
70 #clock-cells = <0>;
71 compatible = "microchip,pic32mzda-sosc";
72 clock-frequency = <32768>;
73 reg = <0x000 0x10>, /* enable reg */
74 <0x1d0 0x10>; /* status reg */
75 microchip,bit-mask = <0x02>; /* enable mask */
76 microchip,status-bit-mask = <0x10>; /* status-mask*/
77 };
78
79 FRCDIV:frcdiv_clk {
80 #clock-cells = <0>;
81 compatible = "microchip,pic32mzda-frcdivclk";
82 clocks = <&FRC>;
83 clock-output-names = "frcdiv_clk";
84 };
85
86 /* System PLL clock */
87 SYSPLL:spll_clk@020 {
88 #clock-cells = <0>;
89 compatible = "microchip,pic32mzda-syspll";
90 reg = <0x020 0x10>, /* SPLL register */
91 <0x1d0 0x10>; /* CLKSTAT register */
92 clocks = <&POSC>, <&FRC>;
93 clock-output-names = "sys_pll";
94 microchip,status-bit-mask = <0x80>; /* SPLLRDY */
95 };
96
97 /* system clock; mux with postdiv & slew */
98 SYSCLK:sys_clk@1c0 {
99 #clock-cells = <0>;
100 compatible = "microchip,pic32mzda-sysclk-v2";
101 reg = <0x1c0 0x04>; /* SLEWCON */
102 clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>,
103 <&LPRC>, <&FRCDIV>;
104 microchip,clock-indices = <0>, <1>, <2>, <4>,
105 <5>, <7>;
106 clock-output-names = "sys_clk";
107 };
108
109 /* Peripheral bus1 clock */
110 PBCLK1:pb1_clk@140 {
111 reg = <0x140 0x10>;
112 #clock-cells = <0>;
113 compatible = "microchip,pic32mzda-pbclk";
114 clocks = <&SYSCLK>;
115 clock-output-names = "pb1_clk";
116 /* used by system modules, not gateable */
117 microchip,ignore-unused;
118 };
119
120 /* Peripheral bus2 clock */
121 PBCLK2:pb2_clk@150 {
122 reg = <0x150 0x10>;
123 #clock-cells = <0>;
124 compatible = "microchip,pic32mzda-pbclk";
125 clocks = <&SYSCLK>;
126 clock-output-names = "pb2_clk";
127 /* avoid gating even if unused */
128 microchip,ignore-unused;
129 };
130
131 /* Peripheral bus3 clock */
132 PBCLK3:pb3_clk@160 {
133 reg = <0x160 0x10>;
134 #clock-cells = <0>;
135 compatible = "microchip,pic32mzda-pbclk";
136 clocks = <&SYSCLK>;
137 clock-output-names = "pb3_clk";
138 };
139
140 /* Peripheral bus4 clock(I/O ports, GPIO) */
141 PBCLK4:pb4_clk@170 {
142 reg = <0x170 0x10>;
143 #clock-cells = <0>;
144 compatible = "microchip,pic32mzda-pbclk";
145 clocks = <&SYSCLK>;
146 clock-output-names = "pb4_clk";
147 };
148
149 /* Peripheral bus clock */
150 PBCLK5:pb5_clk@180 {
151 reg = <0x180 0x10>;
152 #clock-cells = <0>;
153 compatible = "microchip,pic32mzda-pbclk";
154 clocks = <&SYSCLK>;
155 clock-output-names = "pb5_clk";
156 };
157
158 /* Peripheral Bus6 clock; */
159 PBCLK6:pb6_clk@190 {
160 reg = <0x190 0x10>;
161 compatible = "microchip,pic32mzda-pbclk";
162 clocks = <&SYSCLK>;
163 #clock-cells = <0>;
164 };
165
166 /* Peripheral bus7 clock */
167 PBCLK7:pb7_clk@1a0 {
168 reg = <0x1a0 0x10>;
169 #clock-cells = <0>;
170 compatible = "microchip,pic32mzda-pbclk";
171 /* CPU is driven by this clock; so named */
172 clock-output-names = "cpu_clk";
173 clocks = <&SYSCLK>;
174 };
175
176 /* Reference Oscillator clock for SPI/I2S */
177 REFCLKO1:refo1_clk@80 {
178 reg = <0x080 0x20>;
179 #clock-cells = <0>;
180 compatible = "microchip,pic32mzda-refoclk";
181 clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
182 <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
183 microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
184 <5>, <7>, <8>, <9>;
185 clock-output-names = "refo1_clk";
186 };
187
188 /* Reference Oscillator clock for SQI */
189 REFCLKO2:refo2_clk@a0 {
190 reg = <0x0a0 0x20>;
191 #clock-cells = <0>;
192 compatible = "microchip,pic32mzda-refoclk";
193 clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
194 <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
195 microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
196 <5>, <7>, <8>, <9>;
197 clock-output-names = "refo2_clk";
198 };
199
200 /* Reference Oscillator clock, ADC */
201 REFCLKO3:refo3_clk@c0 {
202 reg = <0x0c0 0x20>;
203 compatible = "microchip,pic32mzda-refoclk";
204 clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
205 <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
206 microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
207 <5>, <7>, <8>, <9>;
208 #clock-cells = <0>;
209 clock-output-names = "refo3_clk";
210 };
211
212 /* Reference Oscillator clock */
213 REFCLKO4:refo4_clk@e0 {
214 reg = <0x0e0 0x20>;
215 compatible = "microchip,pic32mzda-refoclk";
216 clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
217 <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
218 microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
219 <5>, <7>, <8>, <9>;
220 #clock-cells = <0>;
221 clock-output-names = "refo4_clk";
222 };
223
224 /* Reference Oscillator clock, LCD */
225 REFCLKO5:refo5_clk@100 {
226 reg = <0x100 0x20>;
227 compatible = "microchip,pic32mzda-refoclk";
228 clocks = <&SYSCLK>,<&PBCLK1>,<&POSC>,<&FRC>,<&LPRC>,
229 <&SOSC>,<&SYSPLL>,<&REFIx>,<&BFRC>;
230 microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
231 <5>, <7>, <8>, <9>;
232 #clock-cells = <0>;
233 clock-output-names = "refo5_clk";
234 };
235 };
236};
diff --git a/arch/mips/boot/dts/pic32/pic32mzda.dtsi b/arch/mips/boot/dts/pic32/pic32mzda.dtsi
new file mode 100644
index 000000000000..ad9e3318c2ce
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda.dtsi
@@ -0,0 +1,281 @@
1/*
2 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <dt-bindings/interrupt-controller/irq.h>
11
12#include "pic32mzda-clk.dtsi"
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&evic>;
18
19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 gpio2 = &gpio2;
23 gpio3 = &gpio3;
24 gpio4 = &gpio4;
25 gpio5 = &gpio5;
26 gpio6 = &gpio6;
27 gpio7 = &gpio7;
28 gpio8 = &gpio8;
29 gpio9 = &gpio9;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu@0 {
43 compatible = "mti,mips14KEc";
44 device_type = "cpu";
45 };
46 };
47
48 soc {
49 compatible = "microchip,pic32mzda-infra";
50 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
51 };
52
53 evic: interrupt-controller@1f810000 {
54 compatible = "microchip,pic32mzda-evic";
55 interrupt-controller;
56 #interrupt-cells = <2>;
57 reg = <0x1f810000 0x1000>;
58 microchip,external-irqs = <3 8 13 18 23>;
59 };
60
61 pic32_pinctrl: pinctrl@1f801400{
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "microchip,pic32mzda-pinctrl";
65 reg = <0x1f801400 0x400>;
66 clocks = <&PBCLK1>;
67 };
68
69 /* PORTA */
70 gpio0: gpio0@1f860000 {
71 compatible = "microchip,pic32mzda-gpio";
72 reg = <0x1f860000 0x100>;
73 interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
74 #gpio-cells = <2>;
75 gpio-controller;
76 interrupt-controller;
77 #interrupt-cells = <2>;
78 clocks = <&PBCLK4>;
79 microchip,gpio-bank = <0>;
80 gpio-ranges = <&pic32_pinctrl 0 0 16>;
81 };
82
83 /* PORTB */
84 gpio1: gpio1@1f860100 {
85 compatible = "microchip,pic32mzda-gpio";
86 reg = <0x1f860100 0x100>;
87 interrupts = <119 IRQ_TYPE_LEVEL_HIGH>;
88 #gpio-cells = <2>;
89 gpio-controller;
90 interrupt-controller;
91 #interrupt-cells = <2>;
92 clocks = <&PBCLK4>;
93 microchip,gpio-bank = <1>;
94 gpio-ranges = <&pic32_pinctrl 0 16 16>;
95 };
96
97 /* PORTC */
98 gpio2: gpio2@1f860200 {
99 compatible = "microchip,pic32mzda-gpio";
100 reg = <0x1f860200 0x100>;
101 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
102 #gpio-cells = <2>;
103 gpio-controller;
104 interrupt-controller;
105 #interrupt-cells = <2>;
106 clocks = <&PBCLK4>;
107 microchip,gpio-bank = <2>;
108 gpio-ranges = <&pic32_pinctrl 0 32 16>;
109 };
110
111 /* PORTD */
112 gpio3: gpio3@1f860300 {
113 compatible = "microchip,pic32mzda-gpio";
114 reg = <0x1f860300 0x100>;
115 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
116 #gpio-cells = <2>;
117 gpio-controller;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 clocks = <&PBCLK4>;
121 microchip,gpio-bank = <3>;
122 gpio-ranges = <&pic32_pinctrl 0 48 16>;
123 };
124
125 /* PORTE */
126 gpio4: gpio4@1f860400 {
127 compatible = "microchip,pic32mzda-gpio";
128 reg = <0x1f860400 0x100>;
129 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>;
131 gpio-controller;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 clocks = <&PBCLK4>;
135 microchip,gpio-bank = <4>;
136 gpio-ranges = <&pic32_pinctrl 0 64 16>;
137 };
138
139 /* PORTF */
140 gpio5: gpio5@1f860500 {
141 compatible = "microchip,pic32mzda-gpio";
142 reg = <0x1f860500 0x100>;
143 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>;
145 gpio-controller;
146 interrupt-controller;
147 #interrupt-cells = <2>;
148 clocks = <&PBCLK4>;
149 microchip,gpio-bank = <5>;
150 gpio-ranges = <&pic32_pinctrl 0 80 16>;
151 };
152
153 /* PORTG */
154 gpio6: gpio6@1f860600 {
155 compatible = "microchip,pic32mzda-gpio";
156 reg = <0x1f860600 0x100>;
157 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
158 #gpio-cells = <2>;
159 gpio-controller;
160 interrupt-controller;
161 #interrupt-cells = <2>;
162 clocks = <&PBCLK4>;
163 microchip,gpio-bank = <6>;
164 gpio-ranges = <&pic32_pinctrl 0 96 16>;
165 };
166
167 /* PORTH */
168 gpio7: gpio7@1f860700 {
169 compatible = "microchip,pic32mzda-gpio";
170 reg = <0x1f860700 0x100>;
171 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>;
173 gpio-controller;
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 clocks = <&PBCLK4>;
177 microchip,gpio-bank = <7>;
178 gpio-ranges = <&pic32_pinctrl 0 112 16>;
179 };
180
181 /* PORTI does not exist */
182
183 /* PORTJ */
184 gpio8: gpio8@1f860800 {
185 compatible = "microchip,pic32mzda-gpio";
186 reg = <0x1f860800 0x100>;
187 interrupts = <126 IRQ_TYPE_LEVEL_HIGH>;
188 #gpio-cells = <2>;
189 gpio-controller;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 clocks = <&PBCLK4>;
193 microchip,gpio-bank = <8>;
194 gpio-ranges = <&pic32_pinctrl 0 128 16>;
195 };
196
197 /* PORTK */
198 gpio9: gpio9@1f860900 {
199 compatible = "microchip,pic32mzda-gpio";
200 reg = <0x1f860900 0x100>;
201 interrupts = <127 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>;
203 gpio-controller;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 clocks = <&PBCLK4>;
207 microchip,gpio-bank = <9>;
208 gpio-ranges = <&pic32_pinctrl 0 144 16>;
209 };
210
211 sdhci: sdhci@1f8ec000 {
212 compatible = "microchip,pic32mzda-sdhci";
213 reg = <0x1f8ec000 0x100>;
214 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&REFCLKO4>, <&PBCLK5>;
216 clock-names = "base_clk", "sys_clk";
217 bus-width = <4>;
218 cap-sd-highspeed;
219 status = "disabled";
220 };
221
222 uart1: serial@1f822000 {
223 compatible = "microchip,pic32mzda-uart";
224 reg = <0x1f822000 0x50>;
225 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
226 <113 IRQ_TYPE_LEVEL_HIGH>,
227 <114 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&PBCLK2>;
229 status = "disabled";
230 };
231
232 uart2: serial@1f822200 {
233 compatible = "microchip,pic32mzda-uart";
234 reg = <0x1f822200 0x50>;
235 interrupts = <145 IRQ_TYPE_LEVEL_HIGH>,
236 <146 IRQ_TYPE_LEVEL_HIGH>,
237 <147 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&PBCLK2>;
239 status = "disabled";
240 };
241
242 uart3: serial@1f822400 {
243 compatible = "microchip,pic32mzda-uart";
244 reg = <0x1f822400 0x50>;
245 interrupts = <157 IRQ_TYPE_LEVEL_HIGH>,
246 <158 IRQ_TYPE_LEVEL_HIGH>,
247 <159 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&PBCLK2>;
249 status = "disabled";
250 };
251
252 uart4: serial@1f822600 {
253 compatible = "microchip,pic32mzda-uart";
254 reg = <0x1f822600 0x50>;
255 interrupts = <170 IRQ_TYPE_LEVEL_HIGH>,
256 <171 IRQ_TYPE_LEVEL_HIGH>,
257 <172 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&PBCLK2>;
259 status = "disabled";
260 };
261
262 uart5: serial@1f822800 {
263 compatible = "microchip,pic32mzda-uart";
264 reg = <0x1f822800 0x50>;
265 interrupts = <179 IRQ_TYPE_LEVEL_HIGH>,
266 <180 IRQ_TYPE_LEVEL_HIGH>,
267 <181 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&PBCLK2>;
269 status = "disabled";
270 };
271
272 uart6: serial@1f822A00 {
273 compatible = "microchip,pic32mzda-uart";
274 reg = <0x1f822A00 0x50>;
275 interrupts = <188 IRQ_TYPE_LEVEL_HIGH>,
276 <189 IRQ_TYPE_LEVEL_HIGH>,
277 <190 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&PBCLK2>;
279 status = "disabled";
280 };
281};
diff --git a/arch/mips/boot/dts/pic32/pic32mzda_sk.dts b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts
new file mode 100644
index 000000000000..5d434a50e85b
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts
@@ -0,0 +1,151 @@
1/*
2 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15#include "pic32mzda.dtsi"
16
17/ {
18 compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda";
19 model = "Microchip PIC32MZDA Starter Kit";
20
21 memory {
22 device_type = "memory";
23 reg = <0x08000000 0x08000000>;
24 };
25
26 chosen {
27 bootargs = "earlyprintk=ttyPIC1,115200n8r console=ttyPIC1,115200n8";
28 };
29
30 leds0 {
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&user_leds_s0>;
34
35 led@1 {
36 label = "pic32mzda_sk:red:led1";
37 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
38 linux,default-trigger = "heartbeat";
39 };
40
41 led@2 {
42 label = "pic32mzda_sk:yellow:led2";
43 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
44 linux,default-trigger = "mmc0";
45 };
46
47 led@3 {
48 label = "pic32mzda_sk:green:led3";
49 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
50 default-state = "on";
51 };
52 };
53
54 keys0 {
55 compatible = "gpio-keys";
56 pinctrl-0 = <&user_buttons_s0>;
57 pinctrl-names = "default";
58
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 button@sw1 {
63 label = "ESC";
64 linux,code = <1>;
65 gpios = <&gpio1 12 0>;
66 };
67
68 button@sw2 {
69 label = "Home";
70 linux,code = <102>;
71 gpios = <&gpio1 13 0>;
72 };
73
74 button@sw3 {
75 label = "Menu";
76 linux,code = <139>;
77 gpios = <&gpio1 14 0>;
78 };
79 };
80};
81
82&uart2 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart2>;
85 status = "okay";
86};
87
88&uart4 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_uart4>;
91 status = "okay";
92};
93
94&sdhci {
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_sdhc1>;
97 status = "okay";
98 assigned-clocks = <&REFCLKO2>,<&REFCLKO4>,<&REFCLKO5>;
99 assigned-clock-rates = <50000000>,<25000000>,<40000000>;
100};
101
102&pic32_pinctrl {
103
104 pinctrl_sdhc1: sdhc1_pins0 {
105 pins = "A6", "D4", "G13", "G12", "G14", "A7", "A0";
106 microchip,digital;
107 };
108
109 user_leds_s0: user_leds_s0 {
110 pins = "H0", "H1", "H2";
111 output-low;
112 microchip,digital;
113 };
114
115 user_buttons_s0: user_buttons_s0 {
116 pins = "B12", "B13", "B14";
117 microchip,digital;
118 input-enable;
119 bias-pull-up;
120 };
121
122 pinctrl_uart2: pinctrl_uart2 {
123 uart2-tx {
124 pins = "G9";
125 function = "U2TX";
126 microchip,digital;
127 output-high;
128 };
129 uart2-rx {
130 pins = "B0";
131 function = "U2RX";
132 microchip,digital;
133 input-enable;
134 };
135 };
136
137 pinctrl_uart4: uart4-0 {
138 uart4-tx {
139 pins = "C3";
140 function = "U4TX";
141 microchip,digital;
142 output-high;
143 };
144 uart4-rx {
145 pins = "E8";
146 function = "U4RX";
147 microchip,digital;
148 input-enable;
149 };
150 };
151};
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi
index 13d0439496a9..3ad4ba9b12fd 100644
--- a/arch/mips/boot/dts/qca/ar9132.dtsi
+++ b/arch/mips/boot/dts/qca/ar9132.dtsi
@@ -125,6 +125,21 @@
125 }; 125 };
126 }; 126 };
127 127
128 usb@1b000100 {
129 compatible = "qca,ar7100-ehci", "generic-ehci";
130 reg = <0x1b000100 0x100>;
131
132 interrupts = <3>;
133 resets = <&rst 5>;
134
135 has-transaction-translator;
136
137 phy-names = "usb";
138 phys = <&usb_phy>;
139
140 status = "disabled";
141 };
142
128 spi@1f000000 { 143 spi@1f000000 {
129 compatible = "qca,ar9132-spi", "qca,ar7100-spi"; 144 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
130 reg = <0x1f000000 0x10>; 145 reg = <0x1f000000 0x10>;
@@ -138,4 +153,15 @@
138 #size-cells = <0>; 153 #size-cells = <0>;
139 }; 154 };
140 }; 155 };
156
157 usb_phy: usb-phy {
158 compatible = "qca,ar7100-usb-phy";
159
160 reset-names = "usb-phy", "usb-suspend-override";
161 resets = <&rst 4>, <&rst 3>;
162
163 #phy-cells = <0>;
164
165 status = "disabled";
166 };
141}; 167};
diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
index 003015ab34e7..e535ee3c26a4 100644
--- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
+++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
@@ -35,6 +35,10 @@
35 }; 35 };
36 }; 36 };
37 37
38 usb@1b000100 {
39 status = "okay";
40 };
41
38 spi@1f000000 { 42 spi@1f000000 {
39 status = "okay"; 43 status = "okay";
40 num-cs = <1>; 44 num-cs = <1>;
@@ -65,6 +69,10 @@
65 }; 69 };
66 }; 70 };
67 71
72 usb-phy {
73 status = "okay";
74 };
75
68 gpio-keys { 76 gpio-keys {
69 compatible = "gpio-keys-polled"; 77 compatible = "gpio-keys-polled";
70 #address-cells = <1>; 78 #address-cells = <1>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 14:04:41 -0400