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authorLinus Torvalds <torvalds@linux-foundation.org>2015-01-18 01:00:40 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-01-18 01:00:40 -0500
commitd0ac5d8e673aa7317c0d132ba3092935dac53298 (patch)
tree458afa365611acc689c63be1d7c6a7ac64c10d92 /arch/arm
parent12ba8571ab6b232f5facef6b1dd28c5ebc2b530a (diff)
parent966903a98fd80ae5f5c4a7ca121d36ea0ba23143 (diff)
Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "We've been sitting on our fixes branch for a while, so this batch is unfortunately on the large side. A lot of these are tweaks and fixes to device trees, fixing various bugs around clocks, reg ranges, etc. There's also a few defconfig updates (which are on the late side, no more of those). All in all the diffstat is bigger than ideal at this time, but nothing in here seems particularly risky" * tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits) reset: sunxi: fix spinlock initialization ARM: dts: disable CCI on exynos5420 based arndale-octa drivers: bus: check cci device tree node status ARM: rockchip: disable jtag/sdmmc autoswitching on rk3288 ARM: nomadik: fix up leftover device tree pins ARM: at91: board-dt-sama5: add phy_fixup to override NAND_Tree ARM: at91/dt: sam9263: Add missing clocks to lcdc node ARM: at91: sama5d3: dt: correct the sound route ARM: at91/dt: sama5d4: fix the timer reg length ARM: exynos_defconfig: Enable LM90 driver ARM: exynos_defconfig: Enable options for display panel support arm: dts: Use pmu_system_controller phandle for dp phy ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instances ARM: dts: berlin: correct BG2Q's SM GPIO location. ARM: dts: berlin: add broken-cd and set bus width for eMMC in Marvell DMP DT ARM: dts: berlin: fix io clk and add missing core clk for BG2Q sdhci2 host ARM: dts: Revert disabling of smc91x for n900 ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling ARM: dts: dra7-evm: fix qspi device tree partition size ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi2
-rw-r--r--arch/arm/boot/dts/berlin2q-marvell-dmp.dts2
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi63
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts10
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts4
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi6
-rw-r--r--arch/arm/boot/dts/imx25.dtsi2
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts22
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi4
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts4
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi30
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi2
-rw-r--r--arch/arm/boot/dts/ste-nomadik-nhk15.dts8
-rw-r--r--arch/arm/configs/exynos_defconfig18
-rw-r--r--arch/arm/configs/omap2plus_defconfig2
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c18
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c2
-rw-r--r--arch/arm/mach-imx/clk-imx6sx.c3
-rw-r--r--arch/arm/mach-omap2/board-generic.c18
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/control.h4
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S21
-rw-r--r--arch/arm/mach-omap2/omap-smp.c13
-rw-r--r--arch/arm/mach-omap2/timer.c44
-rw-r--r--arch/arm/mach-rockchip/rockchip.c27
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c7
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c3
30 files changed, 265 insertions, 80 deletions
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 1467750e3377..e8c6c600a5b6 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -953,6 +953,8 @@
953 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; 953 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
954 pinctrl-names = "default"; 954 pinctrl-names = "default";
955 pinctrl-0 = <&pinctrl_fb>; 955 pinctrl-0 = <&pinctrl_fb>;
956 clocks = <&lcd_clk>, <&lcd_clk>;
957 clock-names = "lcdc_clk", "hclk";
956 status = "disabled"; 958 status = "disabled";
957 }; 959 };
958 960
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index 28e7e2060c33..a98ac1bd8f65 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -65,6 +65,8 @@
65}; 65};
66 66
67&sdhci2 { 67&sdhci2 {
68 broken-cd;
69 bus-width = <8>;
68 non-removable; 70 non-removable;
69 status = "okay"; 71 status = "okay";
70}; 72};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 35253c947a7c..e2f61f27944e 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -83,7 +83,8 @@
83 compatible = "mrvl,pxav3-mmc"; 83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab1000 0x200>; 84 reg = <0xab1000 0x200>;
85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&chip CLKID_SDIO1XIN>; 86 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
87 clock-names = "io", "core";
87 status = "disabled"; 88 status = "disabled";
88 }; 89 };
89 90
@@ -348,36 +349,6 @@
348 interrupt-parent = <&gic>; 349 interrupt-parent = <&gic>;
349 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 350 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
350 }; 351 };
351
352 gpio4: gpio@5000 {
353 compatible = "snps,dw-apb-gpio";
354 reg = <0x5000 0x400>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357
358 porte: gpio-port@4 {
359 compatible = "snps,dw-apb-gpio-port";
360 gpio-controller;
361 #gpio-cells = <2>;
362 snps,nr-gpios = <32>;
363 reg = <0>;
364 };
365 };
366
367 gpio5: gpio@c000 {
368 compatible = "snps,dw-apb-gpio";
369 reg = <0xc000 0x400>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372
373 portf: gpio-port@5 {
374 compatible = "snps,dw-apb-gpio-port";
375 gpio-controller;
376 #gpio-cells = <2>;
377 snps,nr-gpios = <32>;
378 reg = <0>;
379 };
380 };
381 }; 352 };
382 353
383 chip: chip-control@ea0000 { 354 chip: chip-control@ea0000 {
@@ -466,6 +437,21 @@
466 ranges = <0 0xfc0000 0x10000>; 437 ranges = <0 0xfc0000 0x10000>;
467 interrupt-parent = <&sic>; 438 interrupt-parent = <&sic>;
468 439
440 sm_gpio1: gpio@5000 {
441 compatible = "snps,dw-apb-gpio";
442 reg = <0x5000 0x400>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445
446 portf: gpio-port@5 {
447 compatible = "snps,dw-apb-gpio-port";
448 gpio-controller;
449 #gpio-cells = <2>;
450 snps,nr-gpios = <32>;
451 reg = <0>;
452 };
453 };
454
469 i2c2: i2c@7000 { 455 i2c2: i2c@7000 {
470 compatible = "snps,designware-i2c"; 456 compatible = "snps,designware-i2c";
471 #address-cells = <1>; 457 #address-cells = <1>;
@@ -516,6 +502,21 @@
516 status = "disabled"; 502 status = "disabled";
517 }; 503 };
518 504
505 sm_gpio0: gpio@c000 {
506 compatible = "snps,dw-apb-gpio";
507 reg = <0xc000 0x400>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510
511 porte: gpio-port@4 {
512 compatible = "snps,dw-apb-gpio-port";
513 gpio-controller;
514 #gpio-cells = <2>;
515 snps,nr-gpios = <32>;
516 reg = <0>;
517 };
518 };
519
519 sysctrl: pin-controller@d000 { 520 sysctrl: pin-controller@d000 {
520 compatible = "marvell,berlin2q-system-ctrl"; 521 compatible = "marvell,berlin2q-system-ctrl";
521 reg = <0xd000 0x100>; 522 reg = <0xd000 0x100>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c7bfc0..ad4118f7e1a6 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -499,23 +499,23 @@
499 }; 499 };
500 partition@5 { 500 partition@5 {
501 label = "QSPI.u-boot-spl-os"; 501 label = "QSPI.u-boot-spl-os";
502 reg = <0x00140000 0x00010000>; 502 reg = <0x00140000 0x00080000>;
503 }; 503 };
504 partition@6 { 504 partition@6 {
505 label = "QSPI.u-boot-env"; 505 label = "QSPI.u-boot-env";
506 reg = <0x00150000 0x00010000>; 506 reg = <0x001c0000 0x00010000>;
507 }; 507 };
508 partition@7 { 508 partition@7 {
509 label = "QSPI.u-boot-env.backup1"; 509 label = "QSPI.u-boot-env.backup1";
510 reg = <0x00160000 0x0010000>; 510 reg = <0x001d0000 0x0010000>;
511 }; 511 };
512 partition@8 { 512 partition@8 {
513 label = "QSPI.kernel"; 513 label = "QSPI.kernel";
514 reg = <0x00170000 0x0800000>; 514 reg = <0x001e0000 0x0800000>;
515 }; 515 };
516 partition@9 { 516 partition@9 {
517 label = "QSPI.file-system"; 517 label = "QSPI.file-system";
518 reg = <0x00970000 0x01690000>; 518 reg = <0x009e0000 0x01620000>;
519 }; 519 };
520 }; 520 };
521}; 521};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fcd7acf..d75c89d7666a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -736,7 +736,7 @@
736 736
737 dp_phy: video-phy@10040720 { 737 dp_phy: video-phy@10040720 {
738 compatible = "samsung,exynos5250-dp-video-phy"; 738 compatible = "samsung,exynos5250-dp-video-phy";
739 reg = <0x10040720 4>; 739 samsung,pmu-syscon = <&pmu_system_controller>;
740 #phy-cells = <0>; 740 #phy-cells = <0>;
741 }; 741 };
742 742
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index aa7a7d727a7e..db2c1c4cd900 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -372,3 +372,7 @@
372&usbdrd_dwc3_1 { 372&usbdrd_dwc3_1 {
373 dr_mode = "host"; 373 dr_mode = "host";
374}; 374};
375
376&cci {
377 status = "disabled";
378};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f6760b..6d38f8bfd0e6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -120,7 +120,7 @@
120 }; 120 };
121 }; 121 };
122 122
123 cci@10d20000 { 123 cci: cci@10d20000 {
124 compatible = "arm,cci-400"; 124 compatible = "arm,cci-400";
125 #address-cells = <1>; 125 #address-cells = <1>;
126 #size-cells = <1>; 126 #size-cells = <1>;
@@ -503,8 +503,8 @@
503 }; 503 };
504 504
505 dp_phy: video-phy@10040728 { 505 dp_phy: video-phy@10040728 {
506 compatible = "samsung,exynos5250-dp-video-phy"; 506 compatible = "samsung,exynos5420-dp-video-phy";
507 reg = <0x10040728 4>; 507 samsung,pmu-syscon = <&pmu_system_controller>;
508 #phy-cells = <0>; 508 #phy-cells = <0>;
509 }; 509 };
510 510
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 58d3c3cf2923..d238676a9107 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -162,7 +162,7 @@
162 #size-cells = <0>; 162 #size-cells = <0>;
163 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; 163 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
164 reg = <0x43fa4000 0x4000>; 164 reg = <0x43fa4000 0x4000>;
165 clocks = <&clks 62>, <&clks 62>; 165 clocks = <&clks 78>, <&clks 78>;
166 clock-names = "ipg", "per"; 166 clock-names = "ipg", "per";
167 interrupts = <14>; 167 interrupts = <14>;
168 status = "disabled"; 168 status = "disabled";
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 56569cecaa78..649befeb2cf9 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -127,24 +127,12 @@
127 #address-cells = <1>; 127 #address-cells = <1>;
128 #size-cells = <0>; 128 #size-cells = <0>;
129 129
130 reg_usbh1_vbus: regulator@0 { 130 reg_hub_reset: regulator@0 {
131 compatible = "regulator-fixed";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbh1reg>;
134 reg = <0>;
135 regulator-name = "usbh1_vbus";
136 regulator-min-microvolt = <5000000>;
137 regulator-max-microvolt = <5000000>;
138 gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 };
141
142 reg_usbotg_vbus: regulator@1 {
143 compatible = "regulator-fixed"; 131 compatible = "regulator-fixed";
144 pinctrl-names = "default"; 132 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_usbotgreg>; 133 pinctrl-0 = <&pinctrl_usbotgreg>;
146 reg = <1>; 134 reg = <0>;
147 regulator-name = "usbotg_vbus"; 135 regulator-name = "hub_reset";
148 regulator-min-microvolt = <5000000>; 136 regulator-min-microvolt = <5000000>;
149 regulator-max-microvolt = <5000000>; 137 regulator-max-microvolt = <5000000>;
150 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 138 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
@@ -176,6 +164,7 @@
176 reg = <0>; 164 reg = <0>;
177 clocks = <&clks IMX5_CLK_DUMMY>; 165 clocks = <&clks IMX5_CLK_DUMMY>;
178 clock-names = "main_clk"; 166 clock-names = "main_clk";
167 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
179 }; 168 };
180 }; 169 };
181}; 170};
@@ -419,7 +408,7 @@
419&usbh1 { 408&usbh1 {
420 pinctrl-names = "default"; 409 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_usbh1>; 410 pinctrl-0 = <&pinctrl_usbh1>;
422 vbus-supply = <&reg_usbh1_vbus>; 411 vbus-supply = <&reg_hub_reset>;
423 fsl,usbphy = <&usbh1phy>; 412 fsl,usbphy = <&usbh1phy>;
424 phy_type = "ulpi"; 413 phy_type = "ulpi";
425 status = "okay"; 414 status = "okay";
@@ -429,7 +418,6 @@
429 dr_mode = "otg"; 418 dr_mode = "otg";
430 disable-over-current; 419 disable-over-current;
431 phy_type = "utmi_wide"; 420 phy_type = "utmi_wide";
432 vbus-supply = <&reg_usbotg_vbus>;
433 status = "okay"; 421 status = "okay";
434}; 422};
435 423
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7f1cee..2109d0763c1b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -335,8 +335,8 @@
335 vpu: vpu@02040000 { 335 vpu: vpu@02040000 {
336 compatible = "cnm,coda960"; 336 compatible = "cnm,coda960";
337 reg = <0x02040000 0x3c000>; 337 reg = <0x02040000 0x3c000>;
338 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, 338 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
339 <0 12 IRQ_TYPE_LEVEL_HIGH>; 339 <0 3 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg"; 340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, 342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 657da14cb4b5..c70bb27ac65a 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -142,6 +142,7 @@
142 scfg: scfg@1570000 { 142 scfg: scfg@1570000 {
143 compatible = "fsl,ls1021a-scfg", "syscon"; 143 compatible = "fsl,ls1021a-scfg", "syscon";
144 reg = <0x0 0x1570000 0x0 0x10000>; 144 reg = <0x0 0x1570000 0x0 0x10000>;
145 big-endian;
145 }; 146 };
146 147
147 clockgen: clocking@1ee1000 { 148 clockgen: clocking@1ee1000 {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 53f3ca064140..b550c41b46f1 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -700,11 +700,9 @@
700 }; 700 };
701 }; 701 };
702 702
703 /* Ethernet is on some early development boards and qemu */
703 ethernet@gpmc { 704 ethernet@gpmc {
704 compatible = "smsc,lan91c94"; 705 compatible = "smsc,lan91c94";
705
706 status = "disabled";
707
708 interrupt-parent = <&gpio2>; 706 interrupt-parent = <&gpio2>;
709 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ 707 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
710 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ 708 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 3e067dd65d0c..6194d673e80b 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -155,6 +155,15 @@
155}; 155};
156 156
157&pinctrl { 157&pinctrl {
158 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
159 drive-strength = <8>;
160 };
161
162 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
163 bias-pull-up;
164 drive-strength = <8>;
165 };
166
158 backlight { 167 backlight {
159 bl_en: bl-en { 168 bl_en: bl-en {
160 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; 169 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -173,6 +182,27 @@
173 }; 182 };
174 }; 183 };
175 184
185 sdmmc {
186 /*
187 * Default drive strength isn't enough to achieve even
188 * high-speed mode on EVB board so bump up to 8ma.
189 */
190 sdmmc_bus4: sdmmc-bus4 {
191 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
192 <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
193 <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
194 <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
195 };
196
197 sdmmc_clk: sdmmc-clk {
198 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
199 };
200
201 sdmmc_cmd: sdmmc-cmd {
202 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
203 };
204 };
205
176 usb { 206 usb {
177 host_vbus_drv: host-vbus-drv { 207 host_vbus_drv: host-vbus-drv {
178 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; 208 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 49c10d33df30..77e03655aca3 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -176,7 +176,7 @@
176 "Headphone Jack", "HPOUTR", 176 "Headphone Jack", "HPOUTR",
177 "IN2L", "Line In Jack", 177 "IN2L", "Line In Jack",
178 "IN2R", "Line In Jack", 178 "IN2R", "Line In Jack",
179 "MICBIAS", "IN1L", 179 "Mic", "MICBIAS",
180 "IN1L", "Mic"; 180 "IN1L", "Mic";
181 181
182 atmel,ssc-controller = <&ssc0>; 182 atmel,ssc-controller = <&ssc0>;
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 1b0f30c2c4a5..b94995d1889f 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1008,7 +1008,7 @@
1008 1008
1009 pit: timer@fc068630 { 1009 pit: timer@fc068630 {
1010 compatible = "atmel,at91sam9260-pit"; 1010 compatible = "atmel,at91sam9260-pit";
1011 reg = <0xfc068630 0xf>; 1011 reg = <0xfc068630 0x10>;
1012 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1012 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1013 clocks = <&h32ck>; 1013 clocks = <&h32ck>;
1014 }; 1014 };
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
index a8c00ee7522a..3d0b8755caee 100644
--- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -25,11 +25,11 @@
25 stmpe2401_1 { 25 stmpe2401_1 {
26 stmpe2401_1_nhk_mode: stmpe2401_1_nhk { 26 stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
27 nhk_cfg1 { 27 nhk_cfg1 {
28 ste,pins = "GPIO76_B20"; // IRQ line 28 pins = "GPIO76_B20"; // IRQ line
29 ste,input = <0>; 29 ste,input = <0>;
30 }; 30 };
31 nhk_cfg2 { 31 nhk_cfg2 {
32 ste,pins = "GPIO77_B8"; // reset line 32 pins = "GPIO77_B8"; // reset line
33 ste,output = <1>; 33 ste,output = <1>;
34 }; 34 };
35 }; 35 };
@@ -37,11 +37,11 @@
37 stmpe2401_2 { 37 stmpe2401_2 {
38 stmpe2401_2_nhk_mode: stmpe2401_2_nhk { 38 stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
39 nhk_cfg1 { 39 nhk_cfg1 {
40 ste,pins = "GPIO78_A8"; // IRQ line 40 pins = "GPIO78_A8"; // IRQ line
41 ste,input = <0>; 41 ste,input = <0>;
42 }; 42 };
43 nhk_cfg2 { 43 nhk_cfg2 {
44 ste,pins = "GPIO79_C9"; // reset line 44 pins = "GPIO79_C9"; // reset line
45 ste,output = <1>; 45 ste,output = <1>;
46 }; 46 };
47 }; 47 };
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 5ef14de00a29..3d0c5d65c741 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -84,7 +84,8 @@ CONFIG_DEBUG_GPIO=y
84CONFIG_POWER_SUPPLY=y 84CONFIG_POWER_SUPPLY=y
85CONFIG_BATTERY_SBS=y 85CONFIG_BATTERY_SBS=y
86CONFIG_CHARGER_TPS65090=y 86CONFIG_CHARGER_TPS65090=y
87# CONFIG_HWMON is not set 87CONFIG_HWMON=y
88CONFIG_SENSORS_LM90=y
88CONFIG_THERMAL=y 89CONFIG_THERMAL=y
89CONFIG_EXYNOS_THERMAL=y 90CONFIG_EXYNOS_THERMAL=y
90CONFIG_EXYNOS_THERMAL_CORE=y 91CONFIG_EXYNOS_THERMAL_CORE=y
@@ -109,11 +110,26 @@ CONFIG_REGULATOR_S2MPA01=y
109CONFIG_REGULATOR_S2MPS11=y 110CONFIG_REGULATOR_S2MPS11=y
110CONFIG_REGULATOR_S5M8767=y 111CONFIG_REGULATOR_S5M8767=y
111CONFIG_REGULATOR_TPS65090=y 112CONFIG_REGULATOR_TPS65090=y
113CONFIG_DRM=y
114CONFIG_DRM_BRIDGE=y
115CONFIG_DRM_PTN3460=y
116CONFIG_DRM_PS8622=y
117CONFIG_DRM_EXYNOS=y
118CONFIG_DRM_EXYNOS_FIMD=y
119CONFIG_DRM_EXYNOS_DP=y
120CONFIG_DRM_PANEL=y
121CONFIG_DRM_PANEL_SIMPLE=y
112CONFIG_FB=y 122CONFIG_FB=y
113CONFIG_FB_MODE_HELPERS=y 123CONFIG_FB_MODE_HELPERS=y
114CONFIG_FB_SIMPLE=y 124CONFIG_FB_SIMPLE=y
115CONFIG_EXYNOS_VIDEO=y 125CONFIG_EXYNOS_VIDEO=y
116CONFIG_EXYNOS_MIPI_DSI=y 126CONFIG_EXYNOS_MIPI_DSI=y
127CONFIG_BACKLIGHT_LCD_SUPPORT=y
128CONFIG_LCD_CLASS_DEVICE=y
129CONFIG_LCD_PLATFORM=y
130CONFIG_BACKLIGHT_CLASS_DEVICE=y
131CONFIG_BACKLIGHT_GENERIC=y
132CONFIG_BACKLIGHT_PWM=y
117CONFIG_FRAMEBUFFER_CONSOLE=y 133CONFIG_FRAMEBUFFER_CONSOLE=y
118CONFIG_FONTS=y 134CONFIG_FONTS=y
119CONFIG_FONT_7x14=y 135CONFIG_FONT_7x14=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index c2c3a852af9f..667d9d52aa01 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -68,7 +68,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
68CONFIG_CPU_FREQ_GOV_POWERSAVE=y 68CONFIG_CPU_FREQ_GOV_POWERSAVE=y
69CONFIG_CPU_FREQ_GOV_USERSPACE=y 69CONFIG_CPU_FREQ_GOV_USERSPACE=y
70CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y 70CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
71CONFIG_GENERIC_CPUFREQ_CPU0=y 71CONFIG_CPUFREQ_DT=y
72# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set 72# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
73CONFIG_CPU_IDLE=y 73CONFIG_CPU_IDLE=y
74CONFIG_BINFMT_MISC=y 74CONFIG_BINFMT_MISC=y
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 8fb9ef5333f1..97f7367d32b8 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -17,6 +17,7 @@
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/phy.h> 18#include <linux/phy.h>
19#include <linux/clk-provider.h> 19#include <linux/clk-provider.h>
20#include <linux/phy.h>
20 21
21#include <asm/setup.h> 22#include <asm/setup.h>
22#include <asm/irq.h> 23#include <asm/irq.h>
@@ -26,8 +27,25 @@
26 27
27#include "generic.h" 28#include "generic.h"
28 29
30static int ksz8081_phy_fixup(struct phy_device *phy)
31{
32 int value;
33
34 value = phy_read(phy, 0x16);
35 value &= ~0x20;
36 phy_write(phy, 0x16, value);
37
38 return 0;
39}
40
29static void __init sama5_dt_device_init(void) 41static void __init sama5_dt_device_init(void)
30{ 42{
43 if (of_machine_is_compatible("atmel,sama5d4ek") &&
44 IS_ENABLED(CONFIG_PHYLIB)) {
45 phy_register_fixup_for_id("fc028000.etherne:00",
46 ksz8081_phy_fixup);
47 }
48
31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 49 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
32} 50}
33 51
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 5951660d1bd2..2daef619d053 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
144 post_div_table[1].div = 1; 144 post_div_table[1].div = 1;
145 post_div_table[2].div = 1; 145 post_div_table[2].div = 1;
146 video_div_table[1].div = 1; 146 video_div_table[1].div = 1;
147 video_div_table[2].div = 1; 147 video_div_table[3].div = 1;
148 } 148 }
149 149
150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 17354a11356f..5a3e5a159e70 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
558 clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); 558 clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
559 clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); 559 clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
560 560
561 clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
562 clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
563
561 /* Set initial power mode */ 564 /* Set initial power mode */
562 imx6q_set_lpm(WAIT_CLOCKED); 565 imx6q_set_lpm(WAIT_CLOCKED);
563} 566}
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 608079a1aba6..b61c049f92d6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -77,6 +77,24 @@ MACHINE_END
77#endif 77#endif
78 78
79#ifdef CONFIG_ARCH_OMAP3 79#ifdef CONFIG_ARCH_OMAP3
80/* Some boards need board name for legacy userspace in /proc/cpuinfo */
81static const char *const n900_boards_compat[] __initconst = {
82 "nokia,omap3-n900",
83 NULL,
84};
85
86DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
87 .reserve = omap_reserve,
88 .map_io = omap3_map_io,
89 .init_early = omap3430_init_early,
90 .init_machine = omap_generic_init,
91 .init_late = omap3_init_late,
92 .init_time = omap3_sync32k_timer_init,
93 .dt_compat = n900_boards_compat,
94 .restart = omap3xxx_restart,
95MACHINE_END
96
97/* Generic omap3 boards, most boards can use these */
80static const char *const omap3_boards_compat[] __initconst = { 98static const char *const omap3_boards_compat[] __initconst = {
81 "ti,omap3430", 99 "ti,omap3430",
82 "ti,omap3", 100 "ti,omap3",
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea849e7b..db57741c9c8a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -249,6 +249,7 @@ extern void omap4_cpu_die(unsigned int cpu);
249extern struct smp_operations omap4_smp_ops; 249extern struct smp_operations omap4_smp_ops;
250 250
251extern void omap5_secondary_startup(void); 251extern void omap5_secondary_startup(void);
252extern void omap5_secondary_hyp_startup(void);
252#endif 253#endif
253 254
254#if defined(CONFIG_SMP) && defined(CONFIG_PM) 255#if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a3c013345c45..a80ac2d70bb1 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -286,6 +286,10 @@
286#define OMAP5XXX_CONTROL_STATUS 0x134 286#define OMAP5XXX_CONTROL_STATUS 0x134
287#define OMAP5_DEVICETYPE_MASK (0x7 << 6) 287#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
288 288
289/* DRA7XX CONTROL CORE BOOTSTRAP */
290#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
291#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
292
289/* 293/*
290 * REVISIT: This list of registers is not comprehensive - there are more 294 * REVISIT: This list of registers is not comprehensive - there are more
291 * that should be added. 295 * that should be added.
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4993d4bfe9b2..6d1dffca6c7b 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -22,6 +22,7 @@
22 22
23/* Physical address needed since MMU not enabled yet on secondary core */ 23/* Physical address needed since MMU not enabled yet on secondary core */
24#define AUX_CORE_BOOT0_PA 0x48281800 24#define AUX_CORE_BOOT0_PA 0x48281800
25#define API_HYP_ENTRY 0x102
25 26
26/* 27/*
27 * OMAP5 specific entry point for secondary CPU to jump from ROM 28 * OMAP5 specific entry point for secondary CPU to jump from ROM
@@ -41,6 +42,26 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
41 b secondary_startup 42 b secondary_startup
42ENDPROC(omap5_secondary_startup) 43ENDPROC(omap5_secondary_startup)
43/* 44/*
45 * Same as omap5_secondary_startup except we call into the ROM to
46 * enable HYP mode first. This is called instead of
47 * omap5_secondary_startup if the primary CPU was put into HYP mode by
48 * the boot loader.
49 */
50ENTRY(omap5_secondary_hyp_startup)
51wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
52 ldr r0, [r2]
53 mov r0, r0, lsr #5
54 mrc p15, 0, r4, c0, c0, 5
55 and r4, r4, #0x0f
56 cmp r0, r4
57 bne wait_2
58 ldr r12, =API_HYP_ENTRY
59 adr r0, hyp_boot
60 smc #0
61hyp_boot:
62 b secondary_startup
63ENDPROC(omap5_secondary_hyp_startup)
64/*
44 * OMAP4 specific entry point for secondary CPU to jump from ROM 65 * OMAP4 specific entry point for secondary CPU to jump from ROM
45 * code. This routine also provides a holding flag into which 66 * code. This routine also provides a holding flag into which
46 * secondary core is held until we're ready for it to initialise. 67 * secondary core is held until we're ready for it to initialise.
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 256e84ef0f67..5305ec7341ec 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -22,6 +22,7 @@
22#include <linux/irqchip/arm-gic.h> 22#include <linux/irqchip/arm-gic.h>
23 23
24#include <asm/smp_scu.h> 24#include <asm/smp_scu.h>
25#include <asm/virt.h>
25 26
26#include "omap-secure.h" 27#include "omap-secure.h"
27#include "omap-wakeupgen.h" 28#include "omap-wakeupgen.h"
@@ -227,8 +228,16 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
227 if (omap_secure_apis_support()) 228 if (omap_secure_apis_support())
228 omap_auxcoreboot_addr(virt_to_phys(startup_addr)); 229 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
229 else 230 else
230 writel_relaxed(virt_to_phys(omap5_secondary_startup), 231 /*
231 base + OMAP_AUX_CORE_BOOT_1); 232 * If the boot CPU is in HYP mode then start secondary
233 * CPU in HYP mode as well.
234 */
235 if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
236 writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
237 base + OMAP_AUX_CORE_BOOT_1);
238 else
239 writel_relaxed(virt_to_phys(omap5_secondary_startup),
240 base + OMAP_AUX_CORE_BOOT_1);
232 241
233} 242}
234 243
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 4f61148ec168..7d45c84c69ba 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -54,6 +54,7 @@
54 54
55#include "soc.h" 55#include "soc.h"
56#include "common.h" 56#include "common.h"
57#include "control.h"
57#include "powerdomain.h" 58#include "powerdomain.h"
58#include "omap-secure.h" 59#include "omap-secure.h"
59 60
@@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
496 void __iomem *base; 497 void __iomem *base;
497 static struct clk *sys_clk; 498 static struct clk *sys_clk;
498 unsigned long rate; 499 unsigned long rate;
499 unsigned int reg, num, den; 500 unsigned int reg;
501 unsigned long long num, den;
500 502
501 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 503 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
502 if (!base) { 504 if (!base) {
@@ -511,13 +513,42 @@ static void __init realtime_counter_init(void)
511 } 513 }
512 514
513 rate = clk_get_rate(sys_clk); 515 rate = clk_get_rate(sys_clk);
516
517 if (soc_is_dra7xx()) {
518 /*
519 * Errata i856 says the 32.768KHz crystal does not start at
520 * power on, so the CPU falls back to an emulated 32KHz clock
521 * based on sysclk / 610 instead. This causes the master counter
522 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
523 * (OR sysclk * 75 / 244)
524 *
525 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
526 * Of course any board built without a populated 32.768KHz
527 * crystal would also need this fix even if the CPU is fixed
528 * later.
529 *
530 * Either case can be detected by using the two speedselect bits
531 * If they are not 0, then the 32.768KHz clock driving the
532 * coarse counter that corrects the fine counter every time it
533 * ticks is actually rate/610 rather than 32.768KHz and we
534 * should compensate to avoid the 570ppm (at 20MHz, much worse
535 * at other rates) too fast system time.
536 */
537 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
538 if (reg & DRA7_SPEEDSELECT_MASK) {
539 num = 75;
540 den = 244;
541 goto sysclk1_based;
542 }
543 }
544
514 /* Numerator/denumerator values refer TRM Realtime Counter section */ 545 /* Numerator/denumerator values refer TRM Realtime Counter section */
515 switch (rate) { 546 switch (rate) {
516 case 1200000: 547 case 12000000:
517 num = 64; 548 num = 64;
518 den = 125; 549 den = 125;
519 break; 550 break;
520 case 1300000: 551 case 13000000:
521 num = 768; 552 num = 768;
522 den = 1625; 553 den = 1625;
523 break; 554 break;
@@ -529,11 +560,11 @@ static void __init realtime_counter_init(void)
529 num = 192; 560 num = 192;
530 den = 625; 561 den = 625;
531 break; 562 break;
532 case 2600000: 563 case 26000000:
533 num = 384; 564 num = 384;
534 den = 1625; 565 den = 1625;
535 break; 566 break;
536 case 2700000: 567 case 27000000:
537 num = 256; 568 num = 256;
538 den = 1125; 569 den = 1125;
539 break; 570 break;
@@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
545 break; 576 break;
546 } 577 }
547 578
579sysclk1_based:
548 /* Program numerator and denumerator registers */ 580 /* Program numerator and denumerator registers */
549 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & 581 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
550 NUMERATOR_DENUMERATOR_MASK; 582 NUMERATOR_DENUMERATOR_MASK;
@@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
556 reg |= den; 588 reg |= den;
557 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 589 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
558 590
559 arch_timer_freq = (rate / den) * num; 591 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
560 set_cntfreq(); 592 set_cntfreq();
561 593
562 iounmap(base); 594 iounmap(base);
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index d226b71d21d5..a611f4852582 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -19,11 +19,37 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <linux/irqchip.h> 21#include <linux/irqchip.h>
22#include <linux/clk-provider.h>
23#include <linux/clocksource.h>
24#include <linux/mfd/syscon.h>
25#include <linux/regmap.h>
22#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
23#include <asm/mach/map.h> 27#include <asm/mach/map.h>
24#include <asm/hardware/cache-l2x0.h> 28#include <asm/hardware/cache-l2x0.h>
25#include "core.h" 29#include "core.h"
26 30
31#define RK3288_GRF_SOC_CON0 0x244
32
33static void __init rockchip_timer_init(void)
34{
35 if (of_machine_is_compatible("rockchip,rk3288")) {
36 struct regmap *grf;
37
38 /*
39 * Disable auto jtag/sdmmc switching that causes issues
40 * with the mmc controllers making them unreliable
41 */
42 grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
43 if (!IS_ERR(grf))
44 regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
45 else
46 pr_err("rockchip: could not get grf syscon\n");
47 }
48
49 of_clk_init(NULL);
50 clocksource_of_init();
51}
52
27static void __init rockchip_dt_init(void) 53static void __init rockchip_dt_init(void)
28{ 54{
29 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 55 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -42,6 +68,7 @@ static const char * const rockchip_board_dt_compat[] = {
42DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") 68DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
43 .l2c_aux_val = 0, 69 .l2c_aux_val = 0,
44 .l2c_aux_mask = ~0, 70 .l2c_aux_mask = ~0,
71 .init_time = rockchip_timer_init,
45 .dt_compat = rockchip_board_dt_compat, 72 .dt_compat = rockchip_board_dt_compat,
46 .init_machine = rockchip_dt_init, 73 .init_machine = rockchip_dt_init,
47MACHINE_END 74MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 79ad93dfdae4..d191cf419731 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -800,7 +800,14 @@ void __init r8a7740_init_irq_of(void)
800 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); 800 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
801 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); 801 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
802 802
803#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
804 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
805 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
806
807 gic_init(0, 29, gic_dist_base, gic_cpu_base);
808#else
803 irqchip_init(); 809 irqchip_init();
810#endif
804 811
805 /* route signals to GIC */ 812 /* route signals to GIC */
806 iowrite32(0x0, pfc_inta_ctrl); 813 iowrite32(0x0, pfc_inta_ctrl);
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 93ebe3430bfe..fb5e1bb34be8 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -595,6 +595,7 @@ static struct platform_device ipmmu_device = {
595 595
596static struct renesas_intc_irqpin_config irqpin0_platform_data = { 596static struct renesas_intc_irqpin_config irqpin0_platform_data = {
597 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ 597 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
598 .control_parent = true,
598}; 599};
599 600
600static struct resource irqpin0_resources[] = { 601static struct resource irqpin0_resources[] = {
@@ -656,6 +657,7 @@ static struct platform_device irqpin1_device = {
656 657
657static struct renesas_intc_irqpin_config irqpin2_platform_data = { 658static struct renesas_intc_irqpin_config irqpin2_platform_data = {
658 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ 659 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
660 .control_parent = true,
659}; 661};
660 662
661static struct resource irqpin2_resources[] = { 663static struct resource irqpin2_resources[] = {
@@ -686,6 +688,7 @@ static struct platform_device irqpin2_device = {
686 688
687static struct renesas_intc_irqpin_config irqpin3_platform_data = { 689static struct renesas_intc_irqpin_config irqpin3_platform_data = {
688 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ 690 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
691 .control_parent = true,
689}; 692};
690 693
691static struct resource irqpin3_resources[] = { 694static struct resource irqpin3_resources[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 21:06:49 -0500