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authorJames Morse <james.morse@arm.com>2016-10-18 06:27:46 -0400
committerWill Deacon <will.deacon@arm.com>2016-10-20 04:50:53 -0400
commit2a6dcb2b5f3e21592ca8dfa198dcce7bec09b020 (patch)
tree48b4ba1964223e9c90a967752babd3ce24f2739b /arch/arm64/kernel
parent87261d19046aeaeed8eb3d2793fde850ae1b5c9e (diff)
arm64: cpufeature: Schedule enable() calls instead of calling them via IPI
The enable() call for a cpufeature/errata is called using on_each_cpu(). This issues a cross-call IPI to get the work done. Implicitly, this stashes the running PSTATE in SPSR when the CPU receives the IPI, and restores it when we return. This means an enable() call can never modify PSTATE. To allow PAN to do this, change the on_each_cpu() call to use stop_machine(). This schedules the work on each CPU which allows us to modify PSTATE. This involves changing the protype of all the enable() functions. enable_cpu_capabilities() is called during boot and enables the feature on all online CPUs. This path now uses stop_machine(). CPU features for hotplug'd CPUs are enabled by verify_local_cpu_features() which only acts on the local CPU, and can already modify the running PSTATE as it is called from secondary_start_kernel(). Reported-by: Tony Thompson <anthony.thompson@arm.com> Reported-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
-rw-r--r--arch/arm64/kernel/cpu_errata.c3
-rw-r--r--arch/arm64/kernel/cpufeature.c10
-rw-r--r--arch/arm64/kernel/traps.c3
3 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 0150394f4cab..b75e917aac46 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -39,10 +39,11 @@ has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
39 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask); 39 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
40} 40}
41 41
42static void cpu_enable_trap_ctr_access(void *__unused) 42static int cpu_enable_trap_ctr_access(void *__unused)
43{ 43{
44 /* Clear SCTLR_EL1.UCT */ 44 /* Clear SCTLR_EL1.UCT */
45 config_sctlr_el1(SCTLR_EL1_UCT, 0); 45 config_sctlr_el1(SCTLR_EL1_UCT, 0);
46 return 0;
46} 47}
47 48
48#define MIDR_RANGE(model, min, max) \ 49#define MIDR_RANGE(model, min, max) \
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d577f263cc4a..c02504ea304b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -19,7 +19,9 @@
19#define pr_fmt(fmt) "CPU features: " fmt 19#define pr_fmt(fmt) "CPU features: " fmt
20 20
21#include <linux/bsearch.h> 21#include <linux/bsearch.h>
22#include <linux/cpumask.h>
22#include <linux/sort.h> 23#include <linux/sort.h>
24#include <linux/stop_machine.h>
23#include <linux/types.h> 25#include <linux/types.h>
24#include <asm/cpu.h> 26#include <asm/cpu.h>
25#include <asm/cpufeature.h> 27#include <asm/cpufeature.h>
@@ -941,7 +943,13 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
941{ 943{
942 for (; caps->matches; caps++) 944 for (; caps->matches; caps++)
943 if (caps->enable && cpus_have_cap(caps->capability)) 945 if (caps->enable && cpus_have_cap(caps->capability))
944 on_each_cpu(caps->enable, NULL, true); 946 /*
947 * Use stop_machine() as it schedules the work allowing
948 * us to modify PSTATE, instead of on_each_cpu() which
949 * uses an IPI, giving us a PSTATE that disappears when
950 * we return.
951 */
952 stop_machine(caps->enable, NULL, cpu_online_mask);
945} 953}
946 954
947/* 955/*
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 7255c9d6cfb7..c9986b3e0a96 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -428,9 +428,10 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
428 force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0); 428 force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
429} 429}
430 430
431void cpu_enable_cache_maint_trap(void *__unused) 431int cpu_enable_cache_maint_trap(void *__unused)
432{ 432{
433 config_sctlr_el1(SCTLR_EL1_UCI, 0); 433 config_sctlr_el1(SCTLR_EL1_UCI, 0);
434 return 0;
434} 435}
435 436
436#define __user_cache_maint(insn, address, res) \ 437#define __user_cache_maint(insn, address, res) \