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authorOlof Johansson <olof@lixom.net>2012-09-16 23:12:26 -0400
committerOlof Johansson <olof@lixom.net>2012-09-16 23:13:04 -0400
commitf4936639bc4a75218b5598ff69c52b9a8dd7f23d (patch)
tree9c08fc81cb3d3e658ca7f8dc20a949496d9e6130 /arch/arm/plat-omap
parentd1226e8f98f130918265fb5b4dddcb60b783eb34 (diff)
parent11964f53eb4d9ce59a058be9999d9cfcb1ced878 (diff)
Merge tag 'omap-devel-am33xx-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren: From Paul Walmsley <paul@pwsan.com>: AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx should now boot on mainline after this is applied, according to Vaibhav. (The shortlog makes no sense here since it contains mostly the dependent cleanups that are part of the preceding branches). Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/Makefile3
-rw-r--r--arch/arm/plat-omap/common.c40
-rw-r--r--arch/arm/plat-omap/counter_32k.c3
-rw-r--r--arch/arm/plat-omap/debug-devices.c3
-rw-r--r--arch/arm/plat-omap/debug-leds.c1
-rw-r--r--arch/arm/plat-omap/devices.c92
-rw-r--r--arch/arm/plat-omap/dma.c3
-rw-r--r--arch/arm/plat-omap/fb.c2
-rw-r--r--arch/arm/plat-omap/i2c.c3
-rw-r--r--arch/arm/plat-omap/include/plat/am33xx.h25
-rw-r--r--arch/arm/plat-omap/include/plat/board.h138
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h3
-rw-r--r--arch/arm/plat-omap/include/plat/debug-devices.h9
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h2
-rw-r--r--arch/arm/plat-omap/include/plat/gpio-switch.h54
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h228
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h19
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h293
-rw-r--r--arch/arm/plat-omap/include/plat/irqs-44xx.h144
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h453
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h1
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h50
-rw-r--r--arch/arm/plat-omap/include/plat/omap1510.h50
-rw-r--r--arch/arm/plat-omap/include/plat/omap16xx.h202
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h89
-rw-r--r--arch/arm/plat-omap/include/plat/omap34xx.h101
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h62
-rw-r--r--arch/arm/plat-omap/include/plat/omap54xx.h32
-rw-r--r--arch/arm/plat-omap/include/plat/omap7xx.h107
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h1
-rw-r--r--arch/arm/plat-omap/include/plat/ti81xx.h27
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h1
-rw-r--r--arch/arm/plat-omap/sram.c1
36 files changed, 52 insertions, 2196 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba9506c..d15a4a6d6146 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
25 bool "TI OMAP2/3/4" 25 bool "TI OMAP2/3/4"
26 select CLKDEV_LOOKUP 26 select CLKDEV_LOOKUP
27 select GENERIC_IRQ_CHIP 27 select GENERIC_IRQ_CHIP
28 select SPARSE_IRQ
28 select OMAP_DM_TIMER 29 select OMAP_DM_TIMER
29 select USE_OF 30 select USE_OF
30 select PROC_DEVICETREE if PROC_FS 31 select PROC_DEVICETREE if PROC_FS
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 961bf859bc0c..a017e994e006 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,8 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ 6obj-y := common.o sram.o clock.o dma.o mux.o fb.o counter_32k.o
7 fb.o counter_32k.o
8obj-m := 7obj-m :=
9obj-n := 8obj-n :=
10obj- := 9obj- :=
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 89a3723b3538..e5778ed689d8 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -17,52 +17,12 @@
17#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
18 18
19#include <plat/common.h> 19#include <plat/common.h>
20#include <plat/board.h>
21#include <plat/vram.h> 20#include <plat/vram.h>
22#include <plat/dsp.h> 21#include <plat/dsp.h>
23#include <plat/dma.h> 22#include <plat/dma.h>
24 23
25#include <plat/omap-secure.h> 24#include <plat/omap-secure.h>
26 25
27
28#define NO_LENGTH_CHECK 0xffffffff
29
30struct omap_board_config_kernel *omap_board_config __initdata;
31int omap_board_config_size;
32
33static const void *__init get_config(u16 tag, size_t len,
34 int skip, size_t *len_out)
35{
36 struct omap_board_config_kernel *kinfo = NULL;
37 int i;
38
39 /* Try to find the config from the board-specific structures
40 * in the kernel. */
41 for (i = 0; i < omap_board_config_size; i++) {
42 if (omap_board_config[i].tag == tag) {
43 if (skip == 0) {
44 kinfo = &omap_board_config[i];
45 break;
46 } else {
47 skip--;
48 }
49 }
50 }
51 if (kinfo == NULL)
52 return NULL;
53 return kinfo->data;
54}
55
56const void *__init __omap_get_config(u16 tag, size_t len, int nr)
57{
58 return get_config(tag, len, nr, NULL);
59}
60
61const void *__init omap_get_var_config(u16 tag, size_t *len)
62{
63 return get_config(tag, NO_LENGTH_CHECK, 0, len);
64}
65
66void __init omap_reserve(void) 26void __init omap_reserve(void)
67{ 27{
68 omap_vram_reserve_sdram_memblock(); 28 omap_vram_reserve_sdram_memblock();
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index dbf1e03029a5..2e826f1faf7b 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,10 +22,7 @@
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23#include <asm/sched_clock.h> 23#include <asm/sched_clock.h>
24 24
25#include <plat/hardware.h>
26#include <plat/common.h> 25#include <plat/common.h>
27#include <plat/board.h>
28
29#include <plat/clock.h> 26#include <plat/clock.h>
30 27
31/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ 28/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index caa1f7b6cc21..c7a4c0902b38 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -17,9 +17,6 @@
17 17
18#include <mach/hardware.h> 18#include <mach/hardware.h>
19 19
20#include <plat/board.h>
21
22
23/* Many OMAP development platforms reuse the same "debug board"; these 20/* Many OMAP development platforms reuse the same "debug board"; these
24 * platforms include H2, H3, H4, and Perseus2. 21 * platforms include H2, H3, H4, and Perseus2.
25 */ 22 */
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 39407cbe34c6..195aaae65872 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -12,6 +12,7 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/leds.h> 13#include <linux/leds.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/platform_data/gpio-omap.h>
15 16
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17#include <asm/leds.h> 18#include <asm/leds.h>
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
deleted file mode 100644
index 1cba9273d2cb..000000000000
--- a/arch/arm/plat-omap/devices.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/devices.c
3 *
4 * Common platform device setup/initialization for OMAP1 and OMAP2
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/gpio.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/memblock.h>
19
20#include <mach/hardware.h>
21#include <asm/mach-types.h>
22#include <asm/mach/map.h>
23#include <asm/memblock.h>
24
25#include <plat/tc.h>
26#include <plat/board.h>
27#include <plat/mmc.h>
28#include <plat/menelaus.h>
29#include <plat/omap44xx.h>
30
31/*-------------------------------------------------------------------------*/
32
33#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
34
35#ifdef CONFIG_ARCH_OMAP2
36#define OMAP_RNG_BASE 0x480A0000
37#else
38#define OMAP_RNG_BASE 0xfffe5000
39#endif
40
41static struct resource rng_resources[] = {
42 {
43 .start = OMAP_RNG_BASE,
44 .end = OMAP_RNG_BASE + 0x4f,
45 .flags = IORESOURCE_MEM,
46 },
47};
48
49static struct platform_device omap_rng_device = {
50 .name = "omap_rng",
51 .id = -1,
52 .num_resources = ARRAY_SIZE(rng_resources),
53 .resource = rng_resources,
54};
55
56static void omap_init_rng(void)
57{
58 (void) platform_device_register(&omap_rng_device);
59}
60#else
61static inline void omap_init_rng(void) {}
62#endif
63
64/*
65 * This gets called after board-specific INIT_MACHINE, and initializes most
66 * on-chip peripherals accessible on this board (except for few like USB):
67 *
68 * (a) Does any "standard config" pin muxing needed. Board-specific
69 * code will have muxed GPIO pins and done "nonstandard" setup;
70 * that code could live in the boot loader.
71 * (b) Populating board-specific platform_data with the data drivers
72 * rely on to handle wiring variations.
73 * (c) Creating platform devices as meaningful on this board and
74 * with this kernel configuration.
75 *
76 * Claiming GPIOs, and setting their direction and initial values, is the
77 * responsibility of the device drivers. So is responding to probe().
78 *
79 * Board-specific knowledge like creating devices or pin setup is to be
80 * kept out of drivers as much as possible. In particular, pin setup
81 * may be handled by the boot loader, and drivers should expect it will
82 * normally have been done by the time they're probed.
83 */
84static int __init omap_init_devices(void)
85{
86 /* please keep these calls, and their implementations above,
87 * in alphabetical order so they're easier to sort through.
88 */
89 omap_init_rng();
90 return 0;
91}
92arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fe626761e53..6dcad5873d57 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,8 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/delay.h> 37#include <linux/delay.h>
38 38
39#include <mach/hardware.h> 39#include <plat/cpu.h>
40#include <plat/dma.h> 40#include <plat/dma.h>
41
42#include <plat/tc.h> 41#include <plat/tc.h>
43 42
44/* 43/*
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index dd6f92c99e56..bcbb9d5dc293 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -33,8 +33,6 @@
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#include <plat/board.h>
37
38#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) 36#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
39 37
40static bool omapfb_lcd_configured; 38static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc71c4d..40bc06a7ac43 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -39,6 +39,7 @@
39 39
40#define OMAP_I2C_SIZE 0x3f 40#define OMAP_I2C_SIZE 0x3f
41#define OMAP1_I2C_BASE 0xfffb3800 41#define OMAP1_I2C_BASE 0xfffb3800
42#define OMAP1_INT_I2C (32 + 4)
42 43
43static const char name[] = "omap_i2c"; 44static const char name[] = "omap_i2c";
44 45
@@ -105,7 +106,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
105 res = pdev->resource; 106 res = pdev->resource;
106 res[0].start = OMAP1_I2C_BASE; 107 res[0].start = OMAP1_I2C_BASE;
107 res[0].end = res[0].start + OMAP_I2C_SIZE; 108 res[0].end = res[0].start + OMAP_I2C_SIZE;
108 res[1].start = INT_I2C; 109 res[1].start = OMAP1_INT_I2C;
109 pdata = &i2c_pdata[bus_id - 1]; 110 pdata = &i2c_pdata[bus_id - 1];
110 111
111 /* all OMAP1 have IP version 1 register set */ 112 /* all OMAP1 have IP version 1 register set */
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
deleted file mode 100644
index 06c19bb7bca6..000000000000
--- a/arch/arm/plat-omap/include/plat/am33xx.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file contains the address info for various AM33XX modules.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ASM_ARCH_AM33XX_H
17#define __ASM_ARCH_AM33XX_H
18
19#define L4_SLOW_AM33XX_BASE 0x48000000
20
21#define AM33XX_SCM_BASE 0x44E10000
22#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
23#define AM33XX_PRCM_BASE 0x44E00000
24
25#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
deleted file mode 100644
index e62f20a5c0af..000000000000
--- a/arch/arm/plat-omap/include/plat/board.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/board.h
3 *
4 * Information structures for board-specific data
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 */
9
10#ifndef _OMAP_BOARD_H
11#define _OMAP_BOARD_H
12
13#include <linux/types.h>
14
15#include <plat/gpio-switch.h>
16
17/*
18 * OMAP35x EVM revision
19 * Run time detection of EVM revision is done by reading Ethernet
20 * PHY ID -
21 * GEN_1 = 0x01150000
22 * GEN_2 = 0x92200000
23 */
24enum {
25 OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
26 OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
27};
28
29/* Different peripheral ids */
30#define OMAP_TAG_CLOCK 0x4f01
31#define OMAP_TAG_GPIO_SWITCH 0x4f06
32#define OMAP_TAG_STI_CONSOLE 0x4f09
33#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
34
35#define OMAP_TAG_BOOT_REASON 0x4f80
36#define OMAP_TAG_FLASH_PART 0x4f81
37#define OMAP_TAG_VERSION_STR 0x4f82
38
39struct omap_clock_config {
40 /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
41 u8 system_clock_type;
42};
43
44struct omap_serial_console_config {
45 u8 console_uart;
46 u32 console_speed;
47};
48
49struct omap_sti_console_config {
50 unsigned enable:1;
51 u8 channel;
52};
53
54struct omap_camera_sensor_config {
55 u16 reset_gpio;
56 int (*power_on)(void * data);
57 int (*power_off)(void * data);
58};
59
60struct omap_lcd_config {
61 char panel_name[16];
62 char ctrl_name[16];
63 s16 nreset_gpio;
64 u8 data_lines;
65};
66
67struct device;
68struct fb_info;
69struct omap_backlight_config {
70 int default_intensity;
71 int (*set_power)(struct device *dev, int state);
72};
73
74struct omap_fbmem_config {
75 u32 start;
76 u32 size;
77};
78
79struct omap_pwm_led_platform_data {
80 const char *name;
81 int intensity_timer;
82 int blink_timer;
83 void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
84};
85
86struct omap_uart_config {
87 /* Bit field of UARTs present; bit 0 --> UART1 */
88 unsigned int enabled_uarts;
89};
90
91
92struct omap_flash_part_config {
93 char part_table[0];
94};
95
96struct omap_boot_reason_config {
97 char reason_str[12];
98};
99
100struct omap_version_config {
101 char component[12];
102 char version[12];
103};
104
105struct omap_board_config_entry {
106 u16 tag;
107 u16 len;
108 u8 data[0];
109};
110
111struct omap_board_config_kernel {
112 u16 tag;
113 const void *data;
114};
115
116extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
117
118#define omap_get_config(tag, type) \
119 ((const type *) __omap_get_config((tag), sizeof(type), 0))
120#define omap_get_nr_config(tag, type, nr) \
121 ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
122
123extern const void *__init omap_get_var_config(u16 tag, size_t *len);
124
125extern struct omap_board_config_kernel *omap_board_config;
126extern int omap_board_config_size;
127
128
129/* for TI reference platforms sharing the same debug card */
130extern int debug_card_init(u32 addr, unsigned gpio);
131
132/* OMAP3EVM revision */
133#if defined(CONFIG_MACH_OMAP3EVM)
134u8 get_omap3_evm_rev(void);
135#else
136#define get_omap3_evm_rev() (-EINVAL)
137#endif
138#endif
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index bb5d08a70dbc..67da857783ce 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,8 @@
30#ifndef __ASM_ARCH_OMAP_CPU_H 30#ifndef __ASM_ARCH_OMAP_CPU_H
31#define __ASM_ARCH_OMAP_CPU_H 31#define __ASM_ARCH_OMAP_CPU_H
32 32
33#ifndef __ASSEMBLY__
34
33#include <linux/bitops.h> 35#include <linux/bitops.h>
34#include <plat/multi.h> 36#include <plat/multi.h>
35 37
@@ -493,4 +495,5 @@ OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
493OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ) 495OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
494OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ) 496OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
495 497
498#endif /* __ASSEMBLY__ */
496#endif 499#endif
diff --git a/arch/arm/plat-omap/include/plat/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h
new file mode 100644
index 000000000000..a4edbd2f7484
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/debug-devices.h
@@ -0,0 +1,9 @@
1#ifndef _OMAP_DEBUG_DEVICES_H
2#define _OMAP_DEBUG_DEVICES_H
3
4#include <linux/types.h>
5
6/* for TI reference platforms sharing the same debug card */
7extern int debug_card_init(u32 addr, unsigned gpio);
8
9#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index c5811d4409b0..0a87b052f8f7 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -31,6 +31,8 @@
31/* Move omap4 specific defines to dma-44xx.h */ 31/* Move omap4 specific defines to dma-44xx.h */
32#include "dma-44xx.h" 32#include "dma-44xx.h"
33 33
34#define INT_DMA_LCD 25
35
34/* DMA channels for omap1 */ 36/* DMA channels for omap1 */
35#define OMAP_DMA_NO_DEVICE 0 37#define OMAP_DMA_NO_DEVICE 0
36#define OMAP_DMA_MCSI1_TX 1 38#define OMAP_DMA_MCSI1_TX 1
diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
deleted file mode 100644
index 10da0e07c0cf..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio-switch.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * GPIO switch definitions
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
12#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
13
14#include <linux/types.h>
15
16/* Cover:
17 * high -> closed
18 * low -> open
19 * Connection:
20 * high -> connected
21 * low -> disconnected
22 * Activity:
23 * high -> active
24 * low -> inactive
25 *
26 */
27#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
28#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
29#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
30#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
31#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
32
33struct omap_gpio_switch {
34 const char *name;
35 s16 gpio;
36 unsigned flags:4;
37 unsigned type:4;
38
39 /* Time in ms to debounce when transitioning from
40 * inactive state to active state. */
41 u16 debounce_rising;
42 /* Same for transition from active to inactive state. */
43 u16 debounce_falling;
44
45 /* notify board-specific code about state changes */
46 void (* notify)(void *data, int state);
47 void *notify_data;
48};
49
50/* Call at init time only */
51extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
52 int count);
53
54#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
deleted file mode 100644
index 50fb7cc000ea..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ /dev/null
@@ -1,228 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpio.h
3 *
4 * OMAP GPIO handling defines and functions
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 *
8 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_GPIO_H
27#define __ASM_ARCH_OMAP_GPIO_H
28
29#include <linux/io.h>
30#include <linux/platform_device.h>
31#include <mach/irqs.h>
32
33#define OMAP1_MPUIO_BASE 0xfffb5000
34
35/*
36 * These are the omap15xx/16xx offsets. The omap7xx offset are
37 * OMAP_MPUIO_ / 2 offsets below.
38 */
39#define OMAP_MPUIO_INPUT_LATCH 0x00
40#define OMAP_MPUIO_OUTPUT 0x04
41#define OMAP_MPUIO_IO_CNTL 0x08
42#define OMAP_MPUIO_KBR_LATCH 0x10
43#define OMAP_MPUIO_KBC 0x14
44#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
45#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
46#define OMAP_MPUIO_KBD_INT 0x20
47#define OMAP_MPUIO_GPIO_INT 0x24
48#define OMAP_MPUIO_KBD_MASKIT 0x28
49#define OMAP_MPUIO_GPIO_MASKIT 0x2c
50#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
51#define OMAP_MPUIO_LATCH 0x34
52
53#define OMAP34XX_NR_GPIOS 6
54
55/*
56 * OMAP1510 GPIO registers
57 */
58#define OMAP1510_GPIO_DATA_INPUT 0x00
59#define OMAP1510_GPIO_DATA_OUTPUT 0x04
60#define OMAP1510_GPIO_DIR_CONTROL 0x08
61#define OMAP1510_GPIO_INT_CONTROL 0x0c
62#define OMAP1510_GPIO_INT_MASK 0x10
63#define OMAP1510_GPIO_INT_STATUS 0x14
64#define OMAP1510_GPIO_PIN_CONTROL 0x18
65
66#define OMAP1510_IH_GPIO_BASE 64
67
68/*
69 * OMAP1610 specific GPIO registers
70 */
71#define OMAP1610_GPIO_REVISION 0x0000
72#define OMAP1610_GPIO_SYSCONFIG 0x0010
73#define OMAP1610_GPIO_SYSSTATUS 0x0014
74#define OMAP1610_GPIO_IRQSTATUS1 0x0018
75#define OMAP1610_GPIO_IRQENABLE1 0x001c
76#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
77#define OMAP1610_GPIO_DATAIN 0x002c
78#define OMAP1610_GPIO_DATAOUT 0x0030
79#define OMAP1610_GPIO_DIRECTION 0x0034
80#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
81#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
82#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
83#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
84#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
85#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
86#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
87#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
88
89/*
90 * OMAP7XX specific GPIO registers
91 */
92#define OMAP7XX_GPIO_DATA_INPUT 0x00
93#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
94#define OMAP7XX_GPIO_DIR_CONTROL 0x08
95#define OMAP7XX_GPIO_INT_CONTROL 0x0c
96#define OMAP7XX_GPIO_INT_MASK 0x10
97#define OMAP7XX_GPIO_INT_STATUS 0x14
98
99/*
100 * omap2+ specific GPIO registers
101 */
102#define OMAP24XX_GPIO_REVISION 0x0000
103#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
104#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
105#define OMAP24XX_GPIO_IRQENABLE2 0x002c
106#define OMAP24XX_GPIO_IRQENABLE1 0x001c
107#define OMAP24XX_GPIO_WAKE_EN 0x0020
108#define OMAP24XX_GPIO_CTRL 0x0030
109#define OMAP24XX_GPIO_OE 0x0034
110#define OMAP24XX_GPIO_DATAIN 0x0038
111#define OMAP24XX_GPIO_DATAOUT 0x003c
112#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
113#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
114#define OMAP24XX_GPIO_RISINGDETECT 0x0048
115#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
116#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
117#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
118#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
119#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
120#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
121#define OMAP24XX_GPIO_SETWKUENA 0x0084
122#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
123#define OMAP24XX_GPIO_SETDATAOUT 0x0094
124
125#define OMAP4_GPIO_REVISION 0x0000
126#define OMAP4_GPIO_EOI 0x0020
127#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
128#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
129#define OMAP4_GPIO_IRQSTATUS0 0x002c
130#define OMAP4_GPIO_IRQSTATUS1 0x0030
131#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
132#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
133#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
134#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
135#define OMAP4_GPIO_IRQWAKEN0 0x0044
136#define OMAP4_GPIO_IRQWAKEN1 0x0048
137#define OMAP4_GPIO_IRQENABLE1 0x011c
138#define OMAP4_GPIO_WAKE_EN 0x0120
139#define OMAP4_GPIO_IRQSTATUS2 0x0128
140#define OMAP4_GPIO_IRQENABLE2 0x012c
141#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138
144#define OMAP4_GPIO_DATAOUT 0x013c
145#define OMAP4_GPIO_LEVELDETECT0 0x0140
146#define OMAP4_GPIO_LEVELDETECT1 0x0144
147#define OMAP4_GPIO_RISINGDETECT 0x0148
148#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
152#define OMAP4_GPIO_SETIRQENABLE1 0x0164
153#define OMAP4_GPIO_CLEARWKUENA 0x0180
154#define OMAP4_GPIO_SETWKUENA 0x0184
155#define OMAP4_GPIO_CLEARDATAOUT 0x0190
156#define OMAP4_GPIO_SETDATAOUT 0x0194
157
158#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
159#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
160
161struct omap_gpio_dev_attr {
162 int bank_width; /* GPIO bank width */
163 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
164};
165
166struct omap_gpio_reg_offs {
167 u16 revision;
168 u16 direction;
169 u16 datain;
170 u16 dataout;
171 u16 set_dataout;
172 u16 clr_dataout;
173 u16 irqstatus;
174 u16 irqstatus2;
175 u16 irqstatus_raw0;
176 u16 irqstatus_raw1;
177 u16 irqenable;
178 u16 irqenable2;
179 u16 set_irqenable;
180 u16 clr_irqenable;
181 u16 debounce;
182 u16 debounce_en;
183 u16 ctrl;
184 u16 wkup_en;
185 u16 leveldetect0;
186 u16 leveldetect1;
187 u16 risingdetect;
188 u16 fallingdetect;
189 u16 irqctrl;
190 u16 edgectrl1;
191 u16 edgectrl2;
192 u16 pinctrl;
193
194 bool irqenable_inv;
195};
196
197struct omap_gpio_platform_data {
198 int bank_type;
199 int bank_width; /* GPIO bank width */
200 int bank_stride; /* Only needed for omap1 MPUIO */
201 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
202 bool loses_context; /* whether the bank would ever lose context */
203 bool is_mpuio; /* whether the bank is of type MPUIO */
204 u32 non_wakeup_gpios;
205
206 struct omap_gpio_reg_offs *regs;
207
208 /* Return context loss count due to PM states changing */
209 int (*get_context_loss_count)(struct device *dev);
210};
211
212extern void omap2_gpio_prepare_for_idle(int off_mode);
213extern void omap2_gpio_resume_after_idle(void);
214extern void omap_set_gpio_debounce(int gpio, int enable);
215extern void omap_set_gpio_debounce_time(int gpio, int enable);
216/*-------------------------------------------------------------------------*/
217
218/*
219 * Wrappers for "new style" GPIO calls, using the new infrastructure
220 * which lets us plug in FPGA, I2C, and other implementations.
221 *
222 * The original OMAP-specific calls should eventually be removed.
223 */
224
225#include <linux/errno.h>
226#include <asm-generic/gpio.h>
227
228#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index f37764a36072..2e6e2597178c 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -133,6 +133,25 @@ struct gpmc_timings {
133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
134}; 134};
135 135
136struct gpmc_nand_regs {
137 void __iomem *gpmc_status;
138 void __iomem *gpmc_nand_command;
139 void __iomem *gpmc_nand_address;
140 void __iomem *gpmc_nand_data;
141 void __iomem *gpmc_prefetch_config1;
142 void __iomem *gpmc_prefetch_config2;
143 void __iomem *gpmc_prefetch_control;
144 void __iomem *gpmc_prefetch_status;
145 void __iomem *gpmc_ecc_config;
146 void __iomem *gpmc_ecc_control;
147 void __iomem *gpmc_ecc_size_config;
148 void __iomem *gpmc_ecc1_result;
149 void __iomem *gpmc_bch_result0;
150};
151
152extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
153extern int gpmc_get_client_irq(unsigned irq_config);
154
136extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 155extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
137extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); 156extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
138extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); 157extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
deleted file mode 100644
index ddbde38e1e33..000000000000
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ /dev/null
@@ -1,293 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/hardware.h
3 *
4 * Hardware definitions for TI OMAP processors and boards
5 *
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
8 *
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
37#define __ASM_ARCH_OMAP_HARDWARE_H
38
39#include <asm/sizes.h>
40#ifndef __ASSEMBLER__
41#include <asm/types.h>
42#include <plat/cpu.h>
43#endif
44#include <plat/serial.h>
45
46/*
47 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors
49 * NOTE: Put all processor or board specific parts to the special header
50 * files.
51 * ---------------------------------------------------------------------------
52 */
53
54/*
55 * ----------------------------------------------------------------------------
56 * Timers
57 * ----------------------------------------------------------------------------
58 */
59#define OMAP_MPU_TIMER1_BASE (0xfffec500)
60#define OMAP_MPU_TIMER2_BASE (0xfffec600)
61#define OMAP_MPU_TIMER3_BASE (0xfffec700)
62#define MPU_TIMER_FREE (1 << 6)
63#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
64#define MPU_TIMER_AR (1 << 1)
65#define MPU_TIMER_ST (1 << 0)
66
67/*
68 * ----------------------------------------------------------------------------
69 * Clocks
70 * ----------------------------------------------------------------------------
71 */
72#define CLKGEN_REG_BASE (0xfffece00)
73#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
74#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
75#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
76#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
77#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
78#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
79#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
80#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
81
82#define CK_RATEF 1
83#define CK_IDLEF 2
84#define CK_ENABLEF 4
85#define CK_SELECTF 8
86#define SETARM_IDLE_SHIFT
87
88/* DPLL control registers */
89#define DPLL_CTL (0xfffecf00)
90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
96#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
97
98/*
99 * ---------------------------------------------------------------------------
100 * UPLD
101 * ---------------------------------------------------------------------------
102 */
103#define ULPD_REG_BASE (0xfffe0800)
104#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
105#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
106#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
107# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
108# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
109#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
110# define SOFT_UDC_REQ (1 << 4)
111# define SOFT_USB_CLK_REQ (1 << 3)
112# define SOFT_DPLL_REQ (1 << 0)
113#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
114#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
115#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
116#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
117#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
118# define DIS_MMC2_DPLL_REQ (1 << 11)
119# define DIS_MMC1_DPLL_REQ (1 << 10)
120# define DIS_UART3_DPLL_REQ (1 << 9)
121# define DIS_UART2_DPLL_REQ (1 << 8)
122# define DIS_UART1_DPLL_REQ (1 << 7)
123# define DIS_USB_HOST_DPLL_REQ (1 << 6)
124#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
125#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
126
127/*
128 * ---------------------------------------------------------------------------
129 * Watchdog timer
130 * ---------------------------------------------------------------------------
131 */
132
133/* Watchdog timer within the OMAP3.2 gigacell */
134#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
135#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
136#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
137#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
138#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
139
140/*
141 * ---------------------------------------------------------------------------
142 * Interrupts
143 * ---------------------------------------------------------------------------
144 */
145#ifdef CONFIG_ARCH_OMAP1
146
147/*
148 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
149 * or something similar.. -- PFM.
150 */
151
152#define OMAP_IH1_BASE 0xfffecb00
153#define OMAP_IH2_BASE 0xfffe0000
154
155#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
156#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
157#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
158#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
159#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
160#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
161#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
162
163#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
164#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
165#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
166#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
167#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
168#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
169#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
170
171#define IRQ_ITR_REG_OFFSET 0x00
172#define IRQ_MIR_REG_OFFSET 0x04
173#define IRQ_SIR_IRQ_REG_OFFSET 0x10
174#define IRQ_SIR_FIQ_REG_OFFSET 0x14
175#define IRQ_CONTROL_REG_OFFSET 0x18
176#define IRQ_ISR_REG_OFFSET 0x9c
177#define IRQ_ILR0_REG_OFFSET 0x1c
178#define IRQ_GMR_REG_OFFSET 0xa0
179
180#endif
181
182/*
183 * ----------------------------------------------------------------------------
184 * System control registers
185 * ----------------------------------------------------------------------------
186 */
187#define MOD_CONF_CTRL_0 0xfffe1080
188#define MOD_CONF_CTRL_1 0xfffe1110
189
190/*
191 * ----------------------------------------------------------------------------
192 * Pin multiplexing registers
193 * ----------------------------------------------------------------------------
194 */
195#define FUNC_MUX_CTRL_0 0xfffe1000
196#define FUNC_MUX_CTRL_1 0xfffe1004
197#define FUNC_MUX_CTRL_2 0xfffe1008
198#define COMP_MODE_CTRL_0 0xfffe100c
199#define FUNC_MUX_CTRL_3 0xfffe1010
200#define FUNC_MUX_CTRL_4 0xfffe1014
201#define FUNC_MUX_CTRL_5 0xfffe1018
202#define FUNC_MUX_CTRL_6 0xfffe101C
203#define FUNC_MUX_CTRL_7 0xfffe1020
204#define FUNC_MUX_CTRL_8 0xfffe1024
205#define FUNC_MUX_CTRL_9 0xfffe1028
206#define FUNC_MUX_CTRL_A 0xfffe102C
207#define FUNC_MUX_CTRL_B 0xfffe1030
208#define FUNC_MUX_CTRL_C 0xfffe1034
209#define FUNC_MUX_CTRL_D 0xfffe1038
210#define PULL_DWN_CTRL_0 0xfffe1040
211#define PULL_DWN_CTRL_1 0xfffe1044
212#define PULL_DWN_CTRL_2 0xfffe1048
213#define PULL_DWN_CTRL_3 0xfffe104c
214#define PULL_DWN_CTRL_4 0xfffe10ac
215
216/* OMAP-1610 specific multiplexing registers */
217#define FUNC_MUX_CTRL_E 0xfffe1090
218#define FUNC_MUX_CTRL_F 0xfffe1094
219#define FUNC_MUX_CTRL_10 0xfffe1098
220#define FUNC_MUX_CTRL_11 0xfffe109c
221#define FUNC_MUX_CTRL_12 0xfffe10a0
222#define PU_PD_SEL_0 0xfffe10b4
223#define PU_PD_SEL_1 0xfffe10b8
224#define PU_PD_SEL_2 0xfffe10bc
225#define PU_PD_SEL_3 0xfffe10c0
226#define PU_PD_SEL_4 0xfffe10c4
227
228/* Timer32K for 1610 and 1710*/
229#define OMAP_TIMER32K_BASE 0xFFFBC400
230
231/*
232 * ---------------------------------------------------------------------------
233 * TIPB bus interface
234 * ---------------------------------------------------------------------------
235 */
236#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
237#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
238#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
239#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
240
241/*
242 * ----------------------------------------------------------------------------
243 * MPUI interface
244 * ----------------------------------------------------------------------------
245 */
246#define MPUI_BASE (0xfffec900)
247#define MPUI_CTRL (MPUI_BASE + 0x0)
248#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
249#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
250#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
251#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
252#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
253#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
254#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
255
256/*
257 * ----------------------------------------------------------------------------
258 * LED Pulse Generator
259 * ----------------------------------------------------------------------------
260 */
261#define OMAP_LPG1_BASE 0xfffbd000
262#define OMAP_LPG2_BASE 0xfffbd800
263#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
264#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
265#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
266#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
267
268/*
269 * ----------------------------------------------------------------------------
270 * Pulse-Width Light
271 * ----------------------------------------------------------------------------
272 */
273#define OMAP_PWL_BASE 0xfffb5800
274#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
275#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
276
277/*
278 * ---------------------------------------------------------------------------
279 * Processor specific defines
280 * ---------------------------------------------------------------------------
281 */
282
283#include <plat/omap7xx.h>
284#include <plat/omap1510.h>
285#include <plat/omap16xx.h>
286#include <plat/omap24xx.h>
287#include <plat/omap34xx.h>
288#include <plat/omap44xx.h>
289#include <plat/ti81xx.h>
290#include <plat/am33xx.h>
291#include <plat/omap54xx.h>
292
293#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644
index 518322c80116..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs-44xx.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * OMAP4 Interrupt lines definitions
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Santosh Shilimkar (santosh.shilimkar@ti.com)
7 * Benoit Cousson (b-cousson@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
21#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
22
23/* OMAP44XX IRQs numbers definitions */
24#define OMAP44XX_IRQ_LOCALTIMER 29
25#define OMAP44XX_IRQ_LOCALWDT 30
26
27#define OMAP44XX_IRQ_GIC_START 32
28
29#define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START)
30#define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START)
31#define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START)
32#define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START)
33#define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START)
34#define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START)
35#define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START)
36#define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START)
37#define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START)
38#define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START)
39#define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START)
40#define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START)
41#define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START)
42#define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START)
43#define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START)
44#define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START)
45#define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START)
46#define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START)
47#define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START)
48#define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START)
49#define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START)
50#define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START)
51#define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START)
52#define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START)
53#define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START)
54#define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START)
55#define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START)
56#define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START)
57#define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START)
58#define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START)
59#define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START)
60#define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START)
61#define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START)
62#define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START)
63#define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START)
64#define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START)
65#define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START)
66#define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START)
67#define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START)
68#define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START)
69#define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START)
70#define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START)
71#define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START)
72#define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START)
73#define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START)
74#define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START)
75#define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START)
76#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START)
77#define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START)
78#define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START)
79#define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START)
80#define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START)
81#define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START)
82#define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START)
83#define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START)
84#define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START)
85#define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START)
86#define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START)
87#define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START)
88#define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START)
89#define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START)
90#define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START)
91#define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START)
92#define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START)
93#define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START)
94#define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START)
95#define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START)
96#define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START)
97#define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START)
98#define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START)
99#define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START)
100#define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START)
101#define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START)
102#define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START)
103#define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START)
104#define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START)
105#define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START)
106#define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START)
107#define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START)
108#define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START)
109#define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START)
110#define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START)
111#define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START)
112#define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START)
113#define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START)
114#define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START)
115#define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START)
116#define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START)
117#define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START)
118#define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START)
119#define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START)
120#define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START)
121#define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START)
122#define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START)
123#define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START)
124#define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START)
125#define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START)
126#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START)
127#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START)
128#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START)
129#define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START)
130#define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START)
131#define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START)
132#define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START)
133#define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START)
134#define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START)
135#define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START)
136#define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START)
137#define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START)
138#define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START)
139#define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START)
140#define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START)
141#define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START)
142#define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START)
143
144#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
deleted file mode 100644
index 37bbbbb981b2..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ /dev/null
@@ -1,453 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/irqs.h
3 *
4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
25 * are different.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
29#define __ASM_ARCH_OMAP15XX_IRQS_H
30
31/* All OMAP4 specific defines are moved to irqs-44xx.h */
32#include "irqs-44xx.h"
33
34/*
35 * IRQ numbers for interrupt handler 1
36 *
37 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
38 *
39 */
40#define INT_CAMERA 1
41#define INT_FIQ 3
42#define INT_RTDX 6
43#define INT_DSP_MMU_ABORT 7
44#define INT_HOST 8
45#define INT_ABORT 9
46#define INT_BRIDGE_PRIV 13
47#define INT_GPIO_BANK1 14
48#define INT_UART3 15
49#define INT_TIMER3 16
50#define INT_DMA_CH0_6 19
51#define INT_DMA_CH1_7 20
52#define INT_DMA_CH2_8 21
53#define INT_DMA_CH3 22
54#define INT_DMA_CH4 23
55#define INT_DMA_CH5 24
56#define INT_DMA_LCD 25
57#define INT_TIMER1 26
58#define INT_WD_TIMER 27
59#define INT_BRIDGE_PUB 28
60#define INT_TIMER2 30
61#define INT_LCD_CTRL 31
62
63/*
64 * OMAP-1510 specific IRQ numbers for interrupt handler 1
65 */
66#define INT_1510_IH2_IRQ 0
67#define INT_1510_RES2 2
68#define INT_1510_SPI_TX 4
69#define INT_1510_SPI_RX 5
70#define INT_1510_DSP_MAILBOX1 10
71#define INT_1510_DSP_MAILBOX2 11
72#define INT_1510_RES12 12
73#define INT_1510_LB_MMU 17
74#define INT_1510_RES18 18
75#define INT_1510_LOCAL_BUS 29
76
77/*
78 * OMAP-1610 specific IRQ numbers for interrupt handler 1
79 */
80#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
81#define INT_1610_IH2_FIQ 2
82#define INT_1610_McBSP2_TX 4
83#define INT_1610_McBSP2_RX 5
84#define INT_1610_DSP_MAILBOX1 10
85#define INT_1610_DSP_MAILBOX2 11
86#define INT_1610_LCD_LINE 12
87#define INT_1610_GPTIMER1 17
88#define INT_1610_GPTIMER2 18
89#define INT_1610_SSR_FIFO_0 29
90
91/*
92 * OMAP-7xx specific IRQ numbers for interrupt handler 1
93 */
94#define INT_7XX_IH2_FIQ 0
95#define INT_7XX_IH2_IRQ 1
96#define INT_7XX_USB_NON_ISO 2
97#define INT_7XX_USB_ISO 3
98#define INT_7XX_ICR 4
99#define INT_7XX_EAC 5
100#define INT_7XX_GPIO_BANK1 6
101#define INT_7XX_GPIO_BANK2 7
102#define INT_7XX_GPIO_BANK3 8
103#define INT_7XX_McBSP2TX 10
104#define INT_7XX_McBSP2RX 11
105#define INT_7XX_McBSP2RX_OVF 12
106#define INT_7XX_LCD_LINE 14
107#define INT_7XX_GSM_PROTECT 15
108#define INT_7XX_TIMER3 16
109#define INT_7XX_GPIO_BANK5 17
110#define INT_7XX_GPIO_BANK6 18
111#define INT_7XX_SPGIO_WR 29
112
113/*
114 * IRQ numbers for interrupt handler 2
115 *
116 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
117 */
118#define IH2_BASE 32
119
120#define INT_KEYBOARD (1 + IH2_BASE)
121#define INT_uWireTX (2 + IH2_BASE)
122#define INT_uWireRX (3 + IH2_BASE)
123#define INT_I2C (4 + IH2_BASE)
124#define INT_MPUIO (5 + IH2_BASE)
125#define INT_USB_HHC_1 (6 + IH2_BASE)
126#define INT_McBSP3TX (10 + IH2_BASE)
127#define INT_McBSP3RX (11 + IH2_BASE)
128#define INT_McBSP1TX (12 + IH2_BASE)
129#define INT_McBSP1RX (13 + IH2_BASE)
130#define INT_UART1 (14 + IH2_BASE)
131#define INT_UART2 (15 + IH2_BASE)
132#define INT_BT_MCSI1TX (16 + IH2_BASE)
133#define INT_BT_MCSI1RX (17 + IH2_BASE)
134#define INT_SOSSI_MATCH (19 + IH2_BASE)
135#define INT_USB_W2FC (20 + IH2_BASE)
136#define INT_1WIRE (21 + IH2_BASE)
137#define INT_OS_TIMER (22 + IH2_BASE)
138#define INT_MMC (23 + IH2_BASE)
139#define INT_GAUGE_32K (24 + IH2_BASE)
140#define INT_RTC_TIMER (25 + IH2_BASE)
141#define INT_RTC_ALARM (26 + IH2_BASE)
142#define INT_MEM_STICK (27 + IH2_BASE)
143
144/*
145 * OMAP-1510 specific IRQ numbers for interrupt handler 2
146 */
147#define INT_1510_DSP_MMU (28 + IH2_BASE)
148#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
149
150/*
151 * OMAP-1610 specific IRQ numbers for interrupt handler 2
152 */
153#define INT_1610_FAC (0 + IH2_BASE)
154#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
155#define INT_1610_USB_OTG (8 + IH2_BASE)
156#define INT_1610_SoSSI (9 + IH2_BASE)
157#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
158#define INT_1610_DSP_MMU (28 + IH2_BASE)
159#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
160#define INT_1610_STI (32 + IH2_BASE)
161#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
162#define INT_1610_GPTIMER3 (34 + IH2_BASE)
163#define INT_1610_GPTIMER4 (35 + IH2_BASE)
164#define INT_1610_GPTIMER5 (36 + IH2_BASE)
165#define INT_1610_GPTIMER6 (37 + IH2_BASE)
166#define INT_1610_GPTIMER7 (38 + IH2_BASE)
167#define INT_1610_GPTIMER8 (39 + IH2_BASE)
168#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
169#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
170#define INT_1610_MMC2 (42 + IH2_BASE)
171#define INT_1610_CF (43 + IH2_BASE)
172#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
173#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
174#define INT_1610_SPI (49 + IH2_BASE)
175#define INT_1610_DMA_CH6 (53 + IH2_BASE)
176#define INT_1610_DMA_CH7 (54 + IH2_BASE)
177#define INT_1610_DMA_CH8 (55 + IH2_BASE)
178#define INT_1610_DMA_CH9 (56 + IH2_BASE)
179#define INT_1610_DMA_CH10 (57 + IH2_BASE)
180#define INT_1610_DMA_CH11 (58 + IH2_BASE)
181#define INT_1610_DMA_CH12 (59 + IH2_BASE)
182#define INT_1610_DMA_CH13 (60 + IH2_BASE)
183#define INT_1610_DMA_CH14 (61 + IH2_BASE)
184#define INT_1610_DMA_CH15 (62 + IH2_BASE)
185#define INT_1610_NAND (63 + IH2_BASE)
186#define INT_1610_SHA1MD5 (91 + IH2_BASE)
187
188/*
189 * OMAP-7xx specific IRQ numbers for interrupt handler 2
190 */
191#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
192#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
193#define INT_7XX_CFCD (2 + IH2_BASE)
194#define INT_7XX_CFIREQ (3 + IH2_BASE)
195#define INT_7XX_I2C (4 + IH2_BASE)
196#define INT_7XX_PCC (5 + IH2_BASE)
197#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
198#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
199#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
200#define INT_7XX_VLYNQ (9 + IH2_BASE)
201#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
202#define INT_7XX_McBSP1TX (11 + IH2_BASE)
203#define INT_7XX_McBSP1RX (12 + IH2_BASE)
204#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
205#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
206#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
207#define INT_7XX_MCSI (16 + IH2_BASE)
208#define INT_7XX_uWireTX (17 + IH2_BASE)
209#define INT_7XX_uWireRX (18 + IH2_BASE)
210#define INT_7XX_SMC_CD (19 + IH2_BASE)
211#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
212#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
213#define INT_7XX_TIMER32K (22 + IH2_BASE)
214#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
215#define INT_7XX_UPLD (24 + IH2_BASE)
216#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
217#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
218#define INT_7XX_USB_GENI (29 + IH2_BASE)
219#define INT_7XX_USB_OTG (30 + IH2_BASE)
220#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
221#define INT_7XX_RNG (32 + IH2_BASE)
222#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
223#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
224#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
225#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
226#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
227#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
228#define INT_7XX_MPUIO (39 + IH2_BASE)
229#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
230#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
231#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
232#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
233#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
234#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
235#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
236#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
237#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
238#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
239#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
240#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
241#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
242#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
243#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
244#define INT_7XX_NAND (63 + IH2_BASE)
245
246#define INT_24XX_SYS_NIRQ 7
247#define INT_24XX_SDMA_IRQ0 12
248#define INT_24XX_SDMA_IRQ1 13
249#define INT_24XX_SDMA_IRQ2 14
250#define INT_24XX_SDMA_IRQ3 15
251#define INT_24XX_CAM_IRQ 24
252#define INT_24XX_DSS_IRQ 25
253#define INT_24XX_MAIL_U0_MPU 26
254#define INT_24XX_DSP_UMA 27
255#define INT_24XX_DSP_MMU 28
256#define INT_24XX_GPIO_BANK1 29
257#define INT_24XX_GPIO_BANK2 30
258#define INT_24XX_GPIO_BANK3 31
259#define INT_24XX_GPIO_BANK4 32
260#define INT_24XX_GPIO_BANK5 33
261#define INT_24XX_MAIL_U3_MPU 34
262#define INT_24XX_GPTIMER1 37
263#define INT_24XX_GPTIMER2 38
264#define INT_24XX_GPTIMER3 39
265#define INT_24XX_GPTIMER4 40
266#define INT_24XX_GPTIMER5 41
267#define INT_24XX_GPTIMER6 42
268#define INT_24XX_GPTIMER7 43
269#define INT_24XX_GPTIMER8 44
270#define INT_24XX_GPTIMER9 45
271#define INT_24XX_GPTIMER10 46
272#define INT_24XX_GPTIMER11 47
273#define INT_24XX_GPTIMER12 48
274#define INT_24XX_SHA1MD5 51
275#define INT_24XX_MCBSP4_IRQ_TX 54
276#define INT_24XX_MCBSP4_IRQ_RX 55
277#define INT_24XX_I2C1_IRQ 56
278#define INT_24XX_I2C2_IRQ 57
279#define INT_24XX_HDQ_IRQ 58
280#define INT_24XX_MCBSP1_IRQ_TX 59
281#define INT_24XX_MCBSP1_IRQ_RX 60
282#define INT_24XX_MCBSP2_IRQ_TX 62
283#define INT_24XX_MCBSP2_IRQ_RX 63
284#define INT_24XX_SPI1_IRQ 65
285#define INT_24XX_SPI2_IRQ 66
286#define INT_24XX_UART1_IRQ 72
287#define INT_24XX_UART2_IRQ 73
288#define INT_24XX_UART3_IRQ 74
289#define INT_24XX_USB_IRQ_GEN 75
290#define INT_24XX_USB_IRQ_NISO 76
291#define INT_24XX_USB_IRQ_ISO 77
292#define INT_24XX_USB_IRQ_HGEN 78
293#define INT_24XX_USB_IRQ_HSOF 79
294#define INT_24XX_USB_IRQ_OTG 80
295#define INT_24XX_MCBSP5_IRQ_TX 81
296#define INT_24XX_MCBSP5_IRQ_RX 82
297#define INT_24XX_MMC_IRQ 83
298#define INT_24XX_MMC2_IRQ 86
299#define INT_24XX_MCBSP3_IRQ_TX 89
300#define INT_24XX_MCBSP3_IRQ_RX 90
301#define INT_24XX_SPI3_IRQ 91
302
303#define INT_243X_MCBSP2_IRQ 16
304#define INT_243X_MCBSP3_IRQ 17
305#define INT_243X_MCBSP4_IRQ 18
306#define INT_243X_MCBSP5_IRQ 19
307#define INT_243X_MCBSP1_IRQ 64
308#define INT_243X_HS_USB_MC 92
309#define INT_243X_HS_USB_DMA 93
310#define INT_243X_CARKIT_IRQ 94
311
312#define INT_34XX_BENCH_MPU_EMUL 3
313#define INT_34XX_ST_MCBSP2_IRQ 4
314#define INT_34XX_ST_MCBSP3_IRQ 5
315#define INT_34XX_SSM_ABORT_IRQ 6
316#define INT_34XX_SYS_NIRQ 7
317#define INT_34XX_D2D_FW_IRQ 8
318#define INT_34XX_L3_DBG_IRQ 9
319#define INT_34XX_L3_APP_IRQ 10
320#define INT_34XX_PRCM_MPU_IRQ 11
321#define INT_34XX_MCBSP1_IRQ 16
322#define INT_34XX_MCBSP2_IRQ 17
323#define INT_34XX_GPMC_IRQ 20
324#define INT_34XX_MCBSP3_IRQ 22
325#define INT_34XX_MCBSP4_IRQ 23
326#define INT_34XX_CAM_IRQ 24
327#define INT_34XX_MCBSP5_IRQ 27
328#define INT_34XX_GPIO_BANK1 29
329#define INT_34XX_GPIO_BANK2 30
330#define INT_34XX_GPIO_BANK3 31
331#define INT_34XX_GPIO_BANK4 32
332#define INT_34XX_GPIO_BANK5 33
333#define INT_34XX_GPIO_BANK6 34
334#define INT_34XX_USIM_IRQ 35
335#define INT_34XX_WDT3_IRQ 36
336#define INT_34XX_SPI4_IRQ 48
337#define INT_34XX_SHA1MD52_IRQ 49
338#define INT_34XX_FPKA_READY_IRQ 50
339#define INT_34XX_SHA1MD51_IRQ 51
340#define INT_34XX_RNG_IRQ 52
341#define INT_34XX_I2C3_IRQ 61
342#define INT_34XX_FPKA_ERROR_IRQ 64
343#define INT_34XX_PBIAS_IRQ 75
344#define INT_34XX_OHCI_IRQ 76
345#define INT_34XX_EHCI_IRQ 77
346#define INT_34XX_TLL_IRQ 78
347#define INT_34XX_PARTHASH_IRQ 79
348#define INT_34XX_MMC3_IRQ 94
349#define INT_34XX_GPT12_IRQ 95
350
351#define INT_36XX_UART4_IRQ 80
352
353#define INT_35XX_HECC0_IRQ 24
354#define INT_35XX_HECC1_IRQ 28
355#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
356#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68
357#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
358#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
359#define INT_35XX_USBOTG_IRQ 71
360#define INT_35XX_UART4_IRQ 84
361#define INT_35XX_CCDC_VD0_IRQ 88
362#define INT_35XX_CCDC_VD1_IRQ 92
363#define INT_35XX_CCDC_VD2_IRQ 93
364
365/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
366 * 16 MPUIO lines */
367#define OMAP_MAX_GPIO_LINES 192
368#define IH_GPIO_BASE (128 + IH2_BASE)
369#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
370#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
371
372/* External FPGA handles interrupts on Innovator boards */
373#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
374#ifdef CONFIG_MACH_OMAP_INNOVATOR
375#define OMAP_FPGA_NR_IRQS 24
376#else
377#define OMAP_FPGA_NR_IRQS 0
378#endif
379#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
380
381/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
382#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
383#ifdef CONFIG_TWL4030_CORE
384#define TWL4030_BASE_NR_IRQS 8
385#define TWL4030_PWR_NR_IRQS 8
386#else
387#define TWL4030_BASE_NR_IRQS 0
388#define TWL4030_PWR_NR_IRQS 0
389#endif
390#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
391#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
392#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
393
394/* External TWL4030 gpio interrupts are optional */
395#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
396#ifdef CONFIG_GPIO_TWL4030
397#define TWL4030_GPIO_NR_IRQS 18
398#else
399#define TWL4030_GPIO_NR_IRQS 0
400#endif
401#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
402
403#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
404#ifdef CONFIG_TWL4030_CORE
405#define TWL6030_BASE_NR_IRQS 20
406#else
407#define TWL6030_BASE_NR_IRQS 0
408#endif
409#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
410
411#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
412#ifdef CONFIG_TWL6040_CODEC
413#define TWL6040_CODEC_NR_IRQS 6
414#else
415#define TWL6040_CODEC_NR_IRQS 0
416#endif
417#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
418
419/* Total number of interrupts depends on the enabled blocks above */
420#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
421#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
422#else
423#define TWL_IRQ_END TWL6040_CODEC_IRQ_END
424#endif
425
426/* GPMC related */
427#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
428#define OMAP_GPMC_NR_IRQS 8
429#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
430
431/* PRCM IRQ handler */
432#ifdef CONFIG_ARCH_OMAP2PLUS
433#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
434#define OMAP_PRCM_NR_IRQS 64
435#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
436#else
437#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
438#endif
439
440#define NR_IRQS OMAP_PRCM_IRQ_END
441
442#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
443
444#define INTCPS_NR_MIR_REGS 3
445#define INTCPS_NR_IRQS 96
446
447#include <mach/hardware.h>
448
449#ifdef CONFIG_FIQ
450#define FIQ_START 1024
451#endif
452
453#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index eb3e4d555343..8b4e4f2da2f5 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,6 @@
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/mmc/host.h> 16#include <linux/mmc/host.h>
17 17
18#include <plat/board.h>
19#include <plat/omap_hwmod.h> 18#include <plat/omap_hwmod.h>
20 19
21#define OMAP15XX_NR_MMC 1 20#define OMAP15XX_NR_MMC 1
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 67fc5060183e..1a68c1e5fe53 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -24,11 +24,10 @@ struct omap_nand_platform_data {
24 struct gpmc_timings *gpmc_t; 24 struct gpmc_timings *gpmc_t;
25 int nr_parts; 25 int nr_parts;
26 bool dev_ready; 26 bool dev_ready;
27 int gpmc_irq;
28 enum nand_io xfer_type; 27 enum nand_io xfer_type;
29 unsigned long phys_base;
30 int devsize; 28 int devsize;
31 enum omap_ecc ecc_opt; 29 enum omap_ecc ecc_opt;
30 struct gpmc_nand_regs reg;
32}; 31};
33 32
34/* minimum size for IO mapping */ 33/* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1a52725ffcf2..a531149823bb 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -18,7 +18,7 @@
18#define __OMAP_SERIAL_H__ 18#define __OMAP_SERIAL_H__
19 19
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/device.h>
22#include <linux/pm_qos.h> 22#include <linux/pm_qos.h>
23 23
24#include <plat/mux.h> 24#include <plat/mux.h>
@@ -42,10 +42,10 @@
42#define OMAP_UART_WER_MOD_WKUP 0X7F 42#define OMAP_UART_WER_MOD_WKUP 0X7F
43 43
44/* Enable XON/XOFF flow control on output */ 44/* Enable XON/XOFF flow control on output */
45#define OMAP_UART_SW_TX 0x04 45#define OMAP_UART_SW_TX 0x8
46 46
47/* Enable XON/XOFF flow control on input */ 47/* Enable XON/XOFF flow control on input */
48#define OMAP_UART_SW_RX 0x04 48#define OMAP_UART_SW_RX 0x2
49 49
50#define OMAP_UART_SYSC_RESET 0X07 50#define OMAP_UART_SYSC_RESET 0X07
51#define OMAP_UART_TCR_TRIG 0X0F 51#define OMAP_UART_TCR_TRIG 0X0F
@@ -69,11 +69,14 @@ struct omap_uart_port_info {
69 unsigned int dma_rx_timeout; 69 unsigned int dma_rx_timeout;
70 unsigned int autosuspend_timeout; 70 unsigned int autosuspend_timeout;
71 unsigned int dma_rx_poll_rate; 71 unsigned int dma_rx_poll_rate;
72 int DTR_gpio;
73 int DTR_inverted;
74 int DTR_present;
72 75
73 int (*get_context_loss_count)(struct device *); 76 int (*get_context_loss_count)(struct device *);
74 void (*set_forceidle)(struct platform_device *); 77 void (*set_forceidle)(struct device *);
75 void (*set_noidle)(struct platform_device *); 78 void (*set_noidle)(struct device *);
76 void (*enable_wakeup)(struct platform_device *, bool); 79 void (*enable_wakeup)(struct device *, bool);
77}; 80};
78 81
79struct uart_omap_dma { 82struct uart_omap_dma {
@@ -102,39 +105,4 @@ struct uart_omap_dma {
102 unsigned int rx_timeout; 105 unsigned int rx_timeout;
103}; 106};
104 107
105struct uart_omap_port {
106 struct uart_port port;
107 struct uart_omap_dma uart_dma;
108 struct platform_device *pdev;
109
110 unsigned char ier;
111 unsigned char lcr;
112 unsigned char mcr;
113 unsigned char fcr;
114 unsigned char efr;
115 unsigned char dll;
116 unsigned char dlh;
117 unsigned char mdr1;
118 unsigned char scr;
119
120 int use_dma;
121 /*
122 * Some bits in registers are cleared on a read, so they must
123 * be saved whenever the register is read but the bits will not
124 * be immediately processed.
125 */
126 unsigned int lsr_break_flag;
127 unsigned char msr_saved_flags;
128 char name[20];
129 unsigned long port_activity;
130 u32 context_loss_cnt;
131 u32 errata;
132 u8 wakeups_enabled;
133
134 struct pm_qos_request pm_qos_request;
135 u32 latency;
136 u32 calc_latency;
137 struct work_struct qos_work;
138};
139
140#endif /* __OMAP_SERIAL_H__ */ 108#endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
deleted file mode 100644
index d24004668138..000000000000
--- a/arch/arm/plat-omap/include/plat/omap1510.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap1510.h
2 *
3 * Hardware definitions for TI OMAP1510 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_H
29#define __ASM_ARCH_OMAP15XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP1510_DSP_BASE 0xE0000000
40#define OMAP1510_DSP_SIZE 0x28000
41#define OMAP1510_DSP_START 0xE0000000
42
43#define OMAP1510_DSPREG_BASE 0xE1000000
44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000
46
47#define OMAP1510_DSP_MMU_BASE (0xfffed200)
48
49#endif /* __ASM_ARCH_OMAP15XX_H */
50
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
deleted file mode 100644
index e69e1d857b45..000000000000
--- a/arch/arm/plat-omap/include/plat/omap16xx.h
+++ /dev/null
@@ -1,202 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap16xx.h
2 *
3 * Hardware definitions for TI OMAP1610/5912/1710 processors.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP16XX_H
29#define __ASM_ARCH_OMAP16XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP16XX_DSP_BASE 0xE0000000
40#define OMAP16XX_DSP_SIZE 0x28000
41#define OMAP16XX_DSP_START 0xE0000000
42
43#define OMAP16XX_DSPREG_BASE 0xE1000000
44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000
46
47#define OMAP16XX_SEC_BASE 0xFFFE4000
48#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
49#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
50#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51
52/*
53 * ---------------------------------------------------------------------------
54 * Interrupts
55 * ---------------------------------------------------------------------------
56 */
57#define OMAP_IH2_0_BASE (0xfffe0000)
58#define OMAP_IH2_1_BASE (0xfffe0100)
59#define OMAP_IH2_2_BASE (0xfffe0200)
60#define OMAP_IH2_3_BASE (0xfffe0300)
61
62#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
63#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
64#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
65#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
66#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
67#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
68#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
69
70#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
71#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
72#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
73#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
74#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
75#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
76#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
77
78#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
79#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
80#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
81#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
82#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
83#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
84#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
85
86#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
87#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
88#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
89#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
90#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
91#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
92#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
93
94/*
95 * ----------------------------------------------------------------------------
96 * Clocks
97 * ----------------------------------------------------------------------------
98 */
99#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
100
101/*
102 * ----------------------------------------------------------------------------
103 * Pin configuration registers
104 * ----------------------------------------------------------------------------
105 */
106#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
107#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
108#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
109#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
110#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
111
112/*
113 * ----------------------------------------------------------------------------
114 * System control registers
115 * ----------------------------------------------------------------------------
116 */
117#define OMAP1610_RESET_CONTROL 0xfffe1140
118
119/*
120 * ---------------------------------------------------------------------------
121 * TIPB bus interface
122 * ---------------------------------------------------------------------------
123 */
124#define TIPB_SWITCH_BASE (0xfffbc800)
125#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
126
127/* UART3 Registers Mapping through MPU bus */
128#define UART3_RHR (OMAP1_UART3_BASE + 0)
129#define UART3_THR (OMAP1_UART3_BASE + 0)
130#define UART3_DLL (OMAP1_UART3_BASE + 0)
131#define UART3_IER (OMAP1_UART3_BASE + 4)
132#define UART3_DLH (OMAP1_UART3_BASE + 4)
133#define UART3_IIR (OMAP1_UART3_BASE + 8)
134#define UART3_FCR (OMAP1_UART3_BASE + 8)
135#define UART3_EFR (OMAP1_UART3_BASE + 8)
136#define UART3_LCR (OMAP1_UART3_BASE + 0x0C)
137#define UART3_MCR (OMAP1_UART3_BASE + 0x10)
138#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10)
139#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14)
140#define UART3_LSR (OMAP1_UART3_BASE + 0x14)
141#define UART3_TCR (OMAP1_UART3_BASE + 0x18)
142#define UART3_MSR (OMAP1_UART3_BASE + 0x18)
143#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18)
144#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C)
145#define UART3_SPR (OMAP1_UART3_BASE + 0x1C)
146#define UART3_TLR (OMAP1_UART3_BASE + 0x1C)
147#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20)
148#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24)
149#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28)
150#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28)
151#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C)
152#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C)
153#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30)
154#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30)
155#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34)
156#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34)
157#define UART3_BLR (OMAP1_UART3_BASE + 0x38)
158#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C)
159#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C)
160#define UART3_SCR (OMAP1_UART3_BASE + 0x40)
161#define UART3_SSR (OMAP1_UART3_BASE + 0x44)
162#define UART3_EBLR (OMAP1_UART3_BASE + 0x48)
163#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C)
164#define UART3_MVR (OMAP1_UART3_BASE + 0x50)
165
166/*
167 * ---------------------------------------------------------------------------
168 * Watchdog timer
169 * ---------------------------------------------------------------------------
170 */
171
172/* 32-bit Watchdog timer in OMAP 16XX */
173#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
174#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
175#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
176#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
177#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
178#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
179#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
180#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
181#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
182#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
183
184#define WCLR_PRE_SHIFT 5
185#define WCLR_PTV_SHIFT 2
186
187#define WWPS_W_PEND_WSPR (1 << 4)
188#define WWPS_W_PEND_WTGR (1 << 3)
189#define WWPS_W_PEND_WLDR (1 << 2)
190#define WWPS_W_PEND_WCRR (1 << 1)
191#define WWPS_W_PEND_WCLR (1 << 0)
192
193#define WSPR_ENABLE_0 (0x0000bbbb)
194#define WSPR_ENABLE_1 (0x00004444)
195#define WSPR_DISABLE_0 (0x0000aaaa)
196#define WSPR_DISABLE_1 (0x00005555)
197
198#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
199#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
200
201#endif /* __ASM_ARCH_OMAP16XX_H */
202
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
deleted file mode 100644
index 92df9e27cc5c..000000000000
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/omap24xx.h
3 *
4 * This file contains the processor specific definitions
5 * of the TI OMAP24XX.
6 *
7 * Copyright (C) 2007 Texas Instruments.
8 * Copyright (C) 2007 Nokia Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP2_H
27#define __ASM_ARCH_OMAP2_H
28
29/*
30 * Please place only base defines here and put the rest in device
31 * specific headers. Note also that some of these defines are needed
32 * for omap1 to compile without adding ifdefs.
33 */
34
35#define L4_24XX_BASE 0x48000000
36#define L4_WK_243X_BASE 0x49000000
37#define L3_24XX_BASE 0x68000000
38
39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42
43#define OMAP242X_CTRL_BASE L4_24XX_BASE
44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
47#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
48#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
49#define OMAP2420_SMS_BASE 0x68008000
50#define OMAP2420_GPMC_BASE 0x6800a000
51
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
54#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
55#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
56
57#define OMAP243X_SMS_BASE 0x6C000000
58#define OMAP243X_SDRC_BASE 0x6D000000
59#define OMAP243X_GPMC_BASE 0x6E000000
60#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
61#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
62#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
63
64/* DSP SS */
65#define OMAP2420_DSP_BASE 0x58000000
66#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
67#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
68#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
69
70#define OMAP243X_DSP_BASE 0x5C000000
71#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
72#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
73
74/* Mailbox */
75#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
76
77/* Camera */
78#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
79
80/* Security */
81#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
82#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
83#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
84#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
87
88#endif /* __ASM_ARCH_OMAP2_H */
89
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
deleted file mode 100644
index 0d818acf3917..000000000000
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/omap34xx.h
3 *
4 * This file contains the processor specific definitions of the TI OMAP34XX.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 * Copyright (C) 2007 Nokia Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_OMAP3_H
25#define __ASM_ARCH_OMAP3_H
26
27/*
28 * Please place only base defines here and put the rest in device
29 * specific headers.
30 */
31
32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000
34#define L4_PER_34XX_BASE 0x49000000
35#define L4_EMU_34XX_BASE 0x54000000
36#define L3_34XX_BASE 0x68000000
37
38#define L4_WK_AM33XX_BASE 0x44C00000
39
40#define OMAP3430_32KSYNCT_BASE 0x48320000
41#define OMAP3430_CM_BASE 0x48004800
42#define OMAP3430_PRM_BASE 0x48306800
43#define OMAP343X_SMS_BASE 0x6C000000
44#define OMAP343X_SDRC_BASE 0x6D000000
45#define OMAP34XX_GPMC_BASE 0x6E000000
46#define OMAP343X_SCM_BASE 0x48002000
47#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
48
49#define OMAP34XX_IC_BASE 0x48200000
50
51#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
52#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
53#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
54#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
55#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
56#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
57#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
58#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
59#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
60#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
61#define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800)
62#define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970)
63#define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0)
64#define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00)
65#define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70)
66#define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0)
67
68#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
69#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
70#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
71#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
72#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
73#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
74#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
75#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
76#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
77#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
78#define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
79#define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
80#define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
81#define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
82#define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
83#define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
84
85#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
86#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
87#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
88#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
89#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
90#define OMAP34XX_SR1_BASE 0x480C9000
91#define OMAP34XX_SR2_BASE 0x480CB000
92
93#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
94
95/* Security */
96#define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000)
97#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000)
98#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000)
99
100#endif /* __ASM_ARCH_OMAP3_H */
101
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 8ad0a377a54b..20de0d5a7e77 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,6 +1,8 @@
1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H 1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H 2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
3 3
4struct omap_board_data;
5
4extern int omap4_keyboard_init(struct omap4_keypad_platform_data *, 6extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
5 struct omap_board_data *); 7 struct omap_board_data *);
6#endif 8#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
deleted file mode 100644
index c0d478e55c84..000000000000
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*:
2 * Address mappings and base address for OMAP4 interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2009 Texas Instruments
6 *
7 * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ASM_ARCH_OMAP44XX_H
14#define __ASM_ARCH_OMAP44XX_H
15
16/*
17 * Please place only base defines here and put the rest in device
18 * specific headers.
19 */
20#define L4_44XX_BASE 0x4a000000
21#define L4_WK_44XX_BASE 0x4a300000
22#define L4_PER_44XX_BASE 0x48000000
23#define L4_EMU_44XX_BASE 0x54000000
24#define L3_44XX_BASE 0x44000000
25#define OMAP44XX_EMIF1_BASE 0x4c000000
26#define OMAP44XX_EMIF2_BASE 0x4d000000
27#define OMAP44XX_DMM_BASE 0x4e000000
28#define OMAP4430_32KSYNCT_BASE 0x4a304000
29#define OMAP4430_CM1_BASE 0x4a004000
30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
31#define OMAP4430_CM2_BASE 0x4a008000
32#define OMAP4430_PRM_BASE 0x4a306000
33#define OMAP4430_PRCM_MPU_BASE 0x48243000
34#define OMAP44XX_GPMC_BASE 0x50000000
35#define OMAP443X_SCM_BASE 0x4a002000
36#define OMAP443X_CTRL_BASE 0x4a100000
37#define OMAP44XX_IC_BASE 0x48200000
38#define OMAP44XX_IVA_INTC_BASE 0x40000000
39#define IRQ_SIR_IRQ 0x0040
40#define OMAP44XX_GIC_DIST_BASE 0x48241000
41#define OMAP44XX_GIC_CPU_BASE 0x48240100
42#define OMAP44XX_SCU_BASE 0x48240000
43#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
44#define OMAP44XX_L2CACHE_BASE 0x48242000
45#define OMAP44XX_WKUPGEN_BASE 0x48281000
46#define OMAP44XX_MCPDM_BASE 0x40132000
47#define OMAP44XX_MCPDM_L3_BASE 0x49032000
48#define OMAP44XX_SAR_RAM_BASE 0x4a326000
49
50#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
51#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000)
52
53#define OMAP4_MMU1_BASE 0x55082000
54#define OMAP4_MMU2_BASE 0x4A066000
55
56#define OMAP44XX_USBTLL_BASE (L4_44XX_BASE + 0x62000)
57#define OMAP44XX_UHH_CONFIG_BASE (L4_44XX_BASE + 0x64000)
58#define OMAP44XX_HSUSB_OHCI_BASE (L4_44XX_BASE + 0x64800)
59#define OMAP44XX_HSUSB_EHCI_BASE (L4_44XX_BASE + 0x64C00)
60
61#endif /* __ASM_ARCH_OMAP44XX_H */
62
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
deleted file mode 100644
index a2582bb3cab3..000000000000
--- a/arch/arm/plat-omap/include/plat/omap54xx.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*:
2 * Address mappings and base address for OMAP5 interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2012 Texas Instruments
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ASM_SOC_OMAP54XX_H
14#define __ASM_SOC_OMAP54XX_H
15
16/*
17 * Please place only base defines here and put the rest in device
18 * specific headers.
19 */
20#define L4_54XX_BASE 0x4a000000
21#define L4_WK_54XX_BASE 0x4ae00000
22#define L4_PER_54XX_BASE 0x48000000
23#define L3_54XX_BASE 0x44000000
24#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
25#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
26#define OMAP54XX_CM_CORE_BASE 0x4a008000
27#define OMAP54XX_PRM_BASE 0x4ae06000
28#define OMAP54XX_PRCM_MPU_BASE 0x48243000
29#define OMAP54XX_SCM_BASE 0x4a002000
30#define OMAP54XX_CTRL_BASE 0x4a002800
31
32#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
deleted file mode 100644
index 48e4757e1e30..000000000000
--- a/arch/arm/plat-omap/include/plat/omap7xx.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/* arch/arm/plat-omap/include/mach/omap7xx.h
2 *
3 * Hardware definitions for TI OMAP7XX processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7 * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_OMAP7XX_H
31#define __ASM_ARCH_OMAP7XX_H
32
33/*
34 * ----------------------------------------------------------------------------
35 * Base addresses
36 * ----------------------------------------------------------------------------
37 */
38
39/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
40
41#define OMAP7XX_DSP_BASE 0xE0000000
42#define OMAP7XX_DSP_SIZE 0x50000
43#define OMAP7XX_DSP_START 0xE0000000
44
45#define OMAP7XX_DSPREG_BASE 0xE1000000
46#define OMAP7XX_DSPREG_SIZE SZ_128K
47#define OMAP7XX_DSPREG_START 0xE1000000
48
49#define OMAP7XX_SPI1_BASE 0xfffc0800
50#define OMAP7XX_SPI2_BASE 0xfffc1000
51
52/*
53 * ----------------------------------------------------------------------------
54 * OMAP7XX specific configuration registers
55 * ----------------------------------------------------------------------------
56 */
57#define OMAP7XX_CONFIG_BASE 0xfffe1000
58#define OMAP7XX_IO_CONF_0 0xfffe1070
59#define OMAP7XX_IO_CONF_1 0xfffe1074
60#define OMAP7XX_IO_CONF_2 0xfffe1078
61#define OMAP7XX_IO_CONF_3 0xfffe107c
62#define OMAP7XX_IO_CONF_4 0xfffe1080
63#define OMAP7XX_IO_CONF_5 0xfffe1084
64#define OMAP7XX_IO_CONF_6 0xfffe1088
65#define OMAP7XX_IO_CONF_7 0xfffe108c
66#define OMAP7XX_IO_CONF_8 0xfffe1090
67#define OMAP7XX_IO_CONF_9 0xfffe1094
68#define OMAP7XX_IO_CONF_10 0xfffe1098
69#define OMAP7XX_IO_CONF_11 0xfffe109c
70#define OMAP7XX_IO_CONF_12 0xfffe10a0
71#define OMAP7XX_IO_CONF_13 0xfffe10a4
72
73#define OMAP7XX_MODE_1 0xfffe1010
74#define OMAP7XX_MODE_2 0xfffe1014
75
76/* CSMI specials: in terms of base + offset */
77#define OMAP7XX_MODE2_OFFSET 0x14
78
79/*
80 * ----------------------------------------------------------------------------
81 * OMAP7XX traffic controller configuration registers
82 * ----------------------------------------------------------------------------
83 */
84#define OMAP7XX_FLASH_CFG_0 0xfffecc10
85#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
86#define OMAP7XX_FLASH_CFG_1 0xfffecc14
87#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
88
89/*
90 * ----------------------------------------------------------------------------
91 * OMAP7XX DSP control registers
92 * ----------------------------------------------------------------------------
93 */
94#define OMAP7XX_ICR_BASE 0xfffbb800
95#define OMAP7XX_DSP_M_CTL 0xfffbb804
96#define OMAP7XX_DSP_MMU_BASE 0xfffed200
97
98/*
99 * ----------------------------------------------------------------------------
100 * OMAP7XX PCC_UPLD configuration registers
101 * ----------------------------------------------------------------------------
102 */
103#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
104#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
105
106#endif /* __ASM_ARCH_OMAP7XX_H */
107
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972aff37..9b9646c3673d 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
658extern int omap2430_hwmod_init(void); 658extern int omap2430_hwmod_init(void);
659extern int omap3xxx_hwmod_init(void); 659extern int omap3xxx_hwmod_init(void);
660extern int omap44xx_hwmod_init(void); 660extern int omap44xx_hwmod_init(void);
661extern int am33xx_hwmod_init(void);
661 662
662extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 663extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
663 664
diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/plat-omap/include/plat/ti81xx.h
deleted file mode 100644
index 8f9843f78422..000000000000
--- a/arch/arm/plat-omap/include/plat/ti81xx.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This file contains the address data for various TI81XX modules.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ASM_ARCH_TI81XX_H
17#define __ASM_ARCH_TI81XX_H
18
19#define L4_SLOW_TI81XX_BASE 0x48000000
20
21#define TI81XX_SCM_BASE 0x48140000
22#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
23#define TI81XX_PRCM_BASE 0x48180000
24
25#define TI81XX_ARM_INTC_BASE 0x48200000
26
27#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 548a4c8d63df..bd20588c356b 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -5,7 +5,6 @@
5 5
6#include <linux/io.h> 6#include <linux/io.h>
7#include <linux/usb/musb.h> 7#include <linux/usb/musb.h>
8#include <plat/board.h>
9 8
10#define OMAP3_HS_USB_PORTS 3 9#define OMAP3_HS_USB_PORTS 3
11 10
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 766181cb5c95..d861aa73299d 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -26,7 +26,6 @@
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28#include <plat/sram.h> 28#include <plat/sram.h>
29#include <plat/board.h>
30#include <plat/cpu.h> 29#include <plat/cpu.h>
31 30
32#include "sram.h" 31#include "sram.h"
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-01 21:32:59 -0400