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authorKevin Hilman <khilman@linaro.org>2013-10-17 18:37:52 -0400
committerKevin Hilman <khilman@linaro.org>2013-10-17 18:37:59 -0400
commitb25a51cb16520c561ad40b0f8e5e26351dc118fc (patch)
treeb53fbbc673f15dc73df15d1e7752682982553564 /arch/arm/mach-tegra
parent751bfe3e55bbbd09c3e135cc7ea2a3b923ad01e5 (diff)
parentb6bda4e0d23815cb711c16085e03cb23c6d49f21 (diff)
Merge tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup
ARM: tegra: cleanup for 3.13 This branch mainly removes dead code and defines that were useful only when booting using board files. A few other misc cleanups are also included. This branch is based on previous pull request tegra-for-3.13-deps-for-arm-init-time-cleanup. * tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order ARM: tegra: make tegra_init_fuse() __init ARM: tegra: remove much of iomap.h ARM: tegra: move resume vector define to irammap.h ARM: tegra: delete gpio-names.h ARM: tegra: delete stale header content ARM: tegra: remove common.c Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/Kconfig2
-rw-r--r--arch/arm/mach-tegra/Makefile1
-rw-r--r--arch/arm/mach-tegra/board-paz00.c5
-rw-r--r--arch/arm/mach-tegra/board-paz00.h25
-rw-r--r--arch/arm/mach-tegra/board.h12
-rw-r--r--arch/arm/mach-tegra/common.c113
-rw-r--r--arch/arm/mach-tegra/fuse.c2
-rw-r--r--arch/arm/mach-tegra/gpio-names.h247
-rw-r--r--arch/arm/mach-tegra/iomap.h152
-rw-r--r--arch/arm/mach-tegra/irammap.h6
-rw-r--r--arch/arm/mach-tegra/pm.c8
-rw-r--r--arch/arm/mach-tegra/pm.h3
-rw-r--r--arch/arm/mach-tegra/pmc.c9
-rw-r--r--arch/arm/mach-tegra/pmc.h4
-rw-r--r--arch/arm/mach-tegra/reset.c2
-rw-r--r--arch/arm/mach-tegra/sleep-tegra20.S5
-rw-r--r--arch/arm/mach-tegra/sleep-tegra30.S5
-rw-r--r--arch/arm/mach-tegra/tegra.c67
18 files changed, 99 insertions, 569 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 0c2f44aed404..56bb6c35d958 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -51,9 +51,9 @@ config ARCH_TEGRA_3x_SOC
51 51
52config ARCH_TEGRA_114_SOC 52config ARCH_TEGRA_114_SOC
53 bool "Enable support for Tegra114 family" 53 bool "Enable support for Tegra114 family"
54 select HAVE_ARM_ARCH_TIMER
55 select ARM_ERRATA_798181 54 select ARM_ERRATA_798181
56 select ARM_L1_CACHE_SHIFT_6 55 select ARM_L1_CACHE_SHIFT_6
56 select HAVE_ARM_ARCH_TIMER
57 select PINCTRL_TEGRA114 57 select PINCTRL_TEGRA114
58 help 58 help
59 Support for NVIDIA Tegra T114 processor family, based on the 59 Support for NVIDIA Tegra T114 processor family, based on the
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e7e5f45c6558..97eb48e977e5 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,6 +1,5 @@
1asflags-y += -march=armv7-a 1asflags-y += -march=armv7-a
2 2
3obj-y += common.o
4obj-y += io.o 3obj-y += io.o
5obj-y += irq.o 4obj-y += irq.o
6obj-y += fuse.o 5obj-y += fuse.o
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 740e16f64728..06f024070dab 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -20,12 +20,11 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/rfkill-gpio.h> 21#include <linux/rfkill-gpio.h>
22#include "board.h" 22#include "board.h"
23#include "board-paz00.h"
24 23
25static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { 24static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
26 .name = "wifi_rfkill", 25 .name = "wifi_rfkill",
27 .reset_gpio = TEGRA_WIFI_RST, 26 .reset_gpio = 25, /* PD1 */
28 .shutdown_gpio = TEGRA_WIFI_PWRN, 27 .shutdown_gpio = 85, /* PK5 */
29 .type = RFKILL_TYPE_WLAN, 28 .type = RFKILL_TYPE_WLAN,
30}; 29};
31 30
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
deleted file mode 100644
index 25c08ecef52f..000000000000
--- a/arch/arm/mach-tegra/board-paz00.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * arch/arm/mach-tegra/board-paz00.h
3 *
4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef _MACH_TEGRA_BOARD_PAZ00_H
18#define _MACH_TEGRA_BOARD_PAZ00_H
19
20#include "gpio-names.h"
21
22#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5
23#define TEGRA_WIFI_RST TEGRA_GPIO_PD1
24
25#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index db6810dc0b3d..bcf5dbf69d58 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -25,20 +25,8 @@
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/reboot.h> 26#include <linux/reboot.h>
27 27
28void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
29
30void __init tegra_init_early(void);
31void __init tegra_map_common_io(void); 28void __init tegra_map_common_io(void);
32void __init tegra_init_irq(void); 29void __init tegra_init_irq(void);
33void __init tegra_dt_init_irq(void);
34
35void tegra_init_late(void);
36
37#ifdef CONFIG_DEBUG_FS
38int tegra_clk_debugfs_init(void);
39#else
40static inline int tegra_clk_debugfs_init(void) { return 0; }
41#endif
42 30
43int __init tegra_powergate_init(void); 31int __init tegra_powergate_init(void);
44#if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS) 32#if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
deleted file mode 100644
index 58dc91c56ccb..000000000000
--- a/arch/arm/mach-tegra/common.c
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * arch/arm/mach-tegra/common.c
3 *
4 * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5 * Copyright (C) 2010 Google, Inc.
6 *
7 * Author:
8 * Colin Cross <ccross@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/reboot.h>
26#include <linux/irqchip.h>
27
28#include <asm/hardware/cache-l2x0.h>
29
30#include "board.h"
31#include "common.h"
32#include "cpuidle.h"
33#include "fuse.h"
34#include "iomap.h"
35#include "irq.h"
36#include "pmc.h"
37#include "apbio.h"
38#include "sleep.h"
39#include "pm.h"
40#include "reset.h"
41
42/*
43 * Storage for debug-macro.S's state.
44 *
45 * This must be in .data not .bss so that it gets initialized each time the
46 * kernel is loaded. The data is declared here rather than debug-macro.S so
47 * that multiple inclusions of debug-macro.S point at the same data.
48 */
49u32 tegra_uart_config[4] = {
50 /* Debug UART initialization required */
51 1,
52 /* Debug UART physical address */
53 0,
54 /* Debug UART virtual address */
55 0,
56 /* Scratch space for debug macro */
57 0,
58};
59
60#ifdef CONFIG_OF
61void __init tegra_dt_init_irq(void)
62{
63 tegra_pmc_init_irq();
64 tegra_init_irq();
65 irqchip_init();
66 tegra_legacy_irq_syscore_init();
67}
68#endif
69
70void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
71{
72 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
73 u32 reg;
74
75 reg = readl_relaxed(reset);
76 reg |= 0x10;
77 writel_relaxed(reg, reset);
78}
79
80static void __init tegra_init_cache(void)
81{
82#ifdef CONFIG_CACHE_L2X0
83 int ret;
84 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
85 u32 aux_ctrl, cache_type;
86
87 cache_type = readl(p + L2X0_CACHE_TYPE);
88 aux_ctrl = (cache_type & 0x700) << (17-8);
89 aux_ctrl |= 0x7C400001;
90
91 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
92 if (!ret)
93 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
94#endif
95
96}
97
98void __init tegra_init_early(void)
99{
100 tegra_cpu_reset_handler_init();
101 tegra_apb_io_init();
102 tegra_init_fuse();
103 tegra_init_cache();
104 tegra_powergate_init();
105 tegra_hotplug_init();
106}
107
108void __init tegra_init_late(void)
109{
110 tegra_init_suspend();
111 tegra_cpuidle_init();
112 tegra_powergate_debugfs_init();
113}
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index e035cd284a6e..f3b5d0d7b620 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -112,7 +112,7 @@ u32 tegra_read_chipid(void)
112 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); 112 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
113} 113}
114 114
115void tegra_init_fuse(void) 115void __init tegra_init_fuse(void)
116{ 116{
117 u32 id; 117 u32 id;
118 118
diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h
deleted file mode 100644
index f28220a641b2..000000000000
--- a/arch/arm/mach-tegra/gpio-names.h
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/gpio-names.h
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __MACH_TEGRA_GPIO_NAMES_H
20#define __MACH_TEGRA_GPIO_NAMES_H
21
22#define TEGRA_GPIO_PA0 0
23#define TEGRA_GPIO_PA1 1
24#define TEGRA_GPIO_PA2 2
25#define TEGRA_GPIO_PA3 3
26#define TEGRA_GPIO_PA4 4
27#define TEGRA_GPIO_PA5 5
28#define TEGRA_GPIO_PA6 6
29#define TEGRA_GPIO_PA7 7
30#define TEGRA_GPIO_PB0 8
31#define TEGRA_GPIO_PB1 9
32#define TEGRA_GPIO_PB2 10
33#define TEGRA_GPIO_PB3 11
34#define TEGRA_GPIO_PB4 12
35#define TEGRA_GPIO_PB5 13
36#define TEGRA_GPIO_PB6 14
37#define TEGRA_GPIO_PB7 15
38#define TEGRA_GPIO_PC0 16
39#define TEGRA_GPIO_PC1 17
40#define TEGRA_GPIO_PC2 18
41#define TEGRA_GPIO_PC3 19
42#define TEGRA_GPIO_PC4 20
43#define TEGRA_GPIO_PC5 21
44#define TEGRA_GPIO_PC6 22
45#define TEGRA_GPIO_PC7 23
46#define TEGRA_GPIO_PD0 24
47#define TEGRA_GPIO_PD1 25
48#define TEGRA_GPIO_PD2 26
49#define TEGRA_GPIO_PD3 27
50#define TEGRA_GPIO_PD4 28
51#define TEGRA_GPIO_PD5 29
52#define TEGRA_GPIO_PD6 30
53#define TEGRA_GPIO_PD7 31
54#define TEGRA_GPIO_PE0 32
55#define TEGRA_GPIO_PE1 33
56#define TEGRA_GPIO_PE2 34
57#define TEGRA_GPIO_PE3 35
58#define TEGRA_GPIO_PE4 36
59#define TEGRA_GPIO_PE5 37
60#define TEGRA_GPIO_PE6 38
61#define TEGRA_GPIO_PE7 39
62#define TEGRA_GPIO_PF0 40
63#define TEGRA_GPIO_PF1 41
64#define TEGRA_GPIO_PF2 42
65#define TEGRA_GPIO_PF3 43
66#define TEGRA_GPIO_PF4 44
67#define TEGRA_GPIO_PF5 45
68#define TEGRA_GPIO_PF6 46
69#define TEGRA_GPIO_PF7 47
70#define TEGRA_GPIO_PG0 48
71#define TEGRA_GPIO_PG1 49
72#define TEGRA_GPIO_PG2 50
73#define TEGRA_GPIO_PG3 51
74#define TEGRA_GPIO_PG4 52
75#define TEGRA_GPIO_PG5 53
76#define TEGRA_GPIO_PG6 54
77#define TEGRA_GPIO_PG7 55
78#define TEGRA_GPIO_PH0 56
79#define TEGRA_GPIO_PH1 57
80#define TEGRA_GPIO_PH2 58
81#define TEGRA_GPIO_PH3 59
82#define TEGRA_GPIO_PH4 60
83#define TEGRA_GPIO_PH5 61
84#define TEGRA_GPIO_PH6 62
85#define TEGRA_GPIO_PH7 63
86#define TEGRA_GPIO_PI0 64
87#define TEGRA_GPIO_PI1 65
88#define TEGRA_GPIO_PI2 66
89#define TEGRA_GPIO_PI3 67
90#define TEGRA_GPIO_PI4 68
91#define TEGRA_GPIO_PI5 69
92#define TEGRA_GPIO_PI6 70
93#define TEGRA_GPIO_PI7 71
94#define TEGRA_GPIO_PJ0 72
95#define TEGRA_GPIO_PJ1 73
96#define TEGRA_GPIO_PJ2 74
97#define TEGRA_GPIO_PJ3 75
98#define TEGRA_GPIO_PJ4 76
99#define TEGRA_GPIO_PJ5 77
100#define TEGRA_GPIO_PJ6 78
101#define TEGRA_GPIO_PJ7 79
102#define TEGRA_GPIO_PK0 80
103#define TEGRA_GPIO_PK1 81
104#define TEGRA_GPIO_PK2 82
105#define TEGRA_GPIO_PK3 83
106#define TEGRA_GPIO_PK4 84
107#define TEGRA_GPIO_PK5 85
108#define TEGRA_GPIO_PK6 86
109#define TEGRA_GPIO_PK7 87
110#define TEGRA_GPIO_PL0 88
111#define TEGRA_GPIO_PL1 89
112#define TEGRA_GPIO_PL2 90
113#define TEGRA_GPIO_PL3 91
114#define TEGRA_GPIO_PL4 92
115#define TEGRA_GPIO_PL5 93
116#define TEGRA_GPIO_PL6 94
117#define TEGRA_GPIO_PL7 95
118#define TEGRA_GPIO_PM0 96
119#define TEGRA_GPIO_PM1 97
120#define TEGRA_GPIO_PM2 98
121#define TEGRA_GPIO_PM3 99
122#define TEGRA_GPIO_PM4 100
123#define TEGRA_GPIO_PM5 101
124#define TEGRA_GPIO_PM6 102
125#define TEGRA_GPIO_PM7 103
126#define TEGRA_GPIO_PN0 104
127#define TEGRA_GPIO_PN1 105
128#define TEGRA_GPIO_PN2 106
129#define TEGRA_GPIO_PN3 107
130#define TEGRA_GPIO_PN4 108
131#define TEGRA_GPIO_PN5 109
132#define TEGRA_GPIO_PN6 110
133#define TEGRA_GPIO_PN7 111
134#define TEGRA_GPIO_PO0 112
135#define TEGRA_GPIO_PO1 113
136#define TEGRA_GPIO_PO2 114
137#define TEGRA_GPIO_PO3 115
138#define TEGRA_GPIO_PO4 116
139#define TEGRA_GPIO_PO5 117
140#define TEGRA_GPIO_PO6 118
141#define TEGRA_GPIO_PO7 119
142#define TEGRA_GPIO_PP0 120
143#define TEGRA_GPIO_PP1 121
144#define TEGRA_GPIO_PP2 122
145#define TEGRA_GPIO_PP3 123
146#define TEGRA_GPIO_PP4 124
147#define TEGRA_GPIO_PP5 125
148#define TEGRA_GPIO_PP6 126
149#define TEGRA_GPIO_PP7 127
150#define TEGRA_GPIO_PQ0 128
151#define TEGRA_GPIO_PQ1 129
152#define TEGRA_GPIO_PQ2 130
153#define TEGRA_GPIO_PQ3 131
154#define TEGRA_GPIO_PQ4 132
155#define TEGRA_GPIO_PQ5 133
156#define TEGRA_GPIO_PQ6 134
157#define TEGRA_GPIO_PQ7 135
158#define TEGRA_GPIO_PR0 136
159#define TEGRA_GPIO_PR1 137
160#define TEGRA_GPIO_PR2 138
161#define TEGRA_GPIO_PR3 139
162#define TEGRA_GPIO_PR4 140
163#define TEGRA_GPIO_PR5 141
164#define TEGRA_GPIO_PR6 142
165#define TEGRA_GPIO_PR7 143
166#define TEGRA_GPIO_PS0 144
167#define TEGRA_GPIO_PS1 145
168#define TEGRA_GPIO_PS2 146
169#define TEGRA_GPIO_PS3 147
170#define TEGRA_GPIO_PS4 148
171#define TEGRA_GPIO_PS5 149
172#define TEGRA_GPIO_PS6 150
173#define TEGRA_GPIO_PS7 151
174#define TEGRA_GPIO_PT0 152
175#define TEGRA_GPIO_PT1 153
176#define TEGRA_GPIO_PT2 154
177#define TEGRA_GPIO_PT3 155
178#define TEGRA_GPIO_PT4 156
179#define TEGRA_GPIO_PT5 157
180#define TEGRA_GPIO_PT6 158
181#define TEGRA_GPIO_PT7 159
182#define TEGRA_GPIO_PU0 160
183#define TEGRA_GPIO_PU1 161
184#define TEGRA_GPIO_PU2 162
185#define TEGRA_GPIO_PU3 163
186#define TEGRA_GPIO_PU4 164
187#define TEGRA_GPIO_PU5 165
188#define TEGRA_GPIO_PU6 166
189#define TEGRA_GPIO_PU7 167
190#define TEGRA_GPIO_PV0 168
191#define TEGRA_GPIO_PV1 169
192#define TEGRA_GPIO_PV2 170
193#define TEGRA_GPIO_PV3 171
194#define TEGRA_GPIO_PV4 172
195#define TEGRA_GPIO_PV5 173
196#define TEGRA_GPIO_PV6 174
197#define TEGRA_GPIO_PV7 175
198#define TEGRA_GPIO_PW0 176
199#define TEGRA_GPIO_PW1 177
200#define TEGRA_GPIO_PW2 178
201#define TEGRA_GPIO_PW3 179
202#define TEGRA_GPIO_PW4 180
203#define TEGRA_GPIO_PW5 181
204#define TEGRA_GPIO_PW6 182
205#define TEGRA_GPIO_PW7 183
206#define TEGRA_GPIO_PX0 184
207#define TEGRA_GPIO_PX1 185
208#define TEGRA_GPIO_PX2 186
209#define TEGRA_GPIO_PX3 187
210#define TEGRA_GPIO_PX4 188
211#define TEGRA_GPIO_PX5 189
212#define TEGRA_GPIO_PX6 190
213#define TEGRA_GPIO_PX7 191
214#define TEGRA_GPIO_PY0 192
215#define TEGRA_GPIO_PY1 193
216#define TEGRA_GPIO_PY2 194
217#define TEGRA_GPIO_PY3 195
218#define TEGRA_GPIO_PY4 196
219#define TEGRA_GPIO_PY5 197
220#define TEGRA_GPIO_PY6 198
221#define TEGRA_GPIO_PY7 199
222#define TEGRA_GPIO_PZ0 200
223#define TEGRA_GPIO_PZ1 201
224#define TEGRA_GPIO_PZ2 202
225#define TEGRA_GPIO_PZ3 203
226#define TEGRA_GPIO_PZ4 204
227#define TEGRA_GPIO_PZ5 205
228#define TEGRA_GPIO_PZ6 206
229#define TEGRA_GPIO_PZ7 207
230#define TEGRA_GPIO_PAA0 208
231#define TEGRA_GPIO_PAA1 209
232#define TEGRA_GPIO_PAA2 210
233#define TEGRA_GPIO_PAA3 211
234#define TEGRA_GPIO_PAA4 212
235#define TEGRA_GPIO_PAA5 213
236#define TEGRA_GPIO_PAA6 214
237#define TEGRA_GPIO_PAA7 215
238#define TEGRA_GPIO_PBB0 216
239#define TEGRA_GPIO_PBB1 217
240#define TEGRA_GPIO_PBB2 218
241#define TEGRA_GPIO_PBB3 219
242#define TEGRA_GPIO_PBB4 220
243#define TEGRA_GPIO_PBB5 221
244#define TEGRA_GPIO_PBB6 222
245#define TEGRA_GPIO_PBB7 223
246
247#endif
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 3f5fa0749bde..cbee57fc4fd8 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -24,44 +24,12 @@
24#define TEGRA_IRAM_BASE 0x40000000 24#define TEGRA_IRAM_BASE 0x40000000
25#define TEGRA_IRAM_SIZE SZ_256K 25#define TEGRA_IRAM_SIZE SZ_256K
26 26
27#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K)
28
29#define TEGRA_HOST1X_BASE 0x50000000
30#define TEGRA_HOST1X_SIZE 0x24000
31
32#define TEGRA_ARM_PERIF_BASE 0x50040000 27#define TEGRA_ARM_PERIF_BASE 0x50040000
33#define TEGRA_ARM_PERIF_SIZE SZ_8K 28#define TEGRA_ARM_PERIF_SIZE SZ_8K
34 29
35#define TEGRA_ARM_PL310_BASE 0x50043000
36#define TEGRA_ARM_PL310_SIZE SZ_4K
37
38#define TEGRA_ARM_INT_DIST_BASE 0x50041000 30#define TEGRA_ARM_INT_DIST_BASE 0x50041000
39#define TEGRA_ARM_INT_DIST_SIZE SZ_4K 31#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
40 32
41#define TEGRA_MPE_BASE 0x54040000
42#define TEGRA_MPE_SIZE SZ_256K
43
44#define TEGRA_VI_BASE 0x54080000
45#define TEGRA_VI_SIZE SZ_256K
46
47#define TEGRA_ISP_BASE 0x54100000
48#define TEGRA_ISP_SIZE SZ_256K
49
50#define TEGRA_DISPLAY_BASE 0x54200000
51#define TEGRA_DISPLAY_SIZE SZ_256K
52
53#define TEGRA_DISPLAY2_BASE 0x54240000
54#define TEGRA_DISPLAY2_SIZE SZ_256K
55
56#define TEGRA_HDMI_BASE 0x54280000
57#define TEGRA_HDMI_SIZE SZ_256K
58
59#define TEGRA_GART_BASE 0x58000000
60#define TEGRA_GART_SIZE SZ_32M
61
62#define TEGRA_RES_SEMA_BASE 0x60001000
63#define TEGRA_RES_SEMA_SIZE SZ_4K
64
65#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 33#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
66#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 34#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
67 35
@@ -98,51 +66,15 @@
98#define TEGRA_FLOW_CTRL_BASE 0x60007000 66#define TEGRA_FLOW_CTRL_BASE 0x60007000
99#define TEGRA_FLOW_CTRL_SIZE 20 67#define TEGRA_FLOW_CTRL_SIZE 20
100 68
101#define TEGRA_AHB_DMA_BASE 0x60008000
102#define TEGRA_AHB_DMA_SIZE SZ_4K
103
104#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
105#define TEGRA_AHB_DMA_CH0_SIZE 32
106
107#define TEGRA_APB_DMA_BASE 0x6000A000
108#define TEGRA_APB_DMA_SIZE SZ_4K
109
110#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
111#define TEGRA_APB_DMA_CH0_SIZE 32
112
113#define TEGRA_AHB_GIZMO_BASE 0x6000C004
114#define TEGRA_AHB_GIZMO_SIZE 0x10C
115
116#define TEGRA_SB_BASE 0x6000C200 69#define TEGRA_SB_BASE 0x6000C200
117#define TEGRA_SB_SIZE 256 70#define TEGRA_SB_SIZE 256
118 71
119#define TEGRA_STATMON_BASE 0x6000C400
120#define TEGRA_STATMON_SIZE SZ_1K
121
122#define TEGRA_GPIO_BASE 0x6000D000
123#define TEGRA_GPIO_SIZE SZ_4K
124
125#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 72#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
126#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K 73#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
127 74
128#define TEGRA_APB_MISC_BASE 0x70000000 75#define TEGRA_APB_MISC_BASE 0x70000000
129#define TEGRA_APB_MISC_SIZE SZ_4K 76#define TEGRA_APB_MISC_SIZE SZ_4K
130 77
131#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
132#define TEGRA_APB_MISC_DAS_SIZE SZ_128
133
134#define TEGRA_AC97_BASE 0x70002000
135#define TEGRA_AC97_SIZE SZ_512
136
137#define TEGRA_SPDIF_BASE 0x70002400
138#define TEGRA_SPDIF_SIZE SZ_512
139
140#define TEGRA_I2S1_BASE 0x70002800
141#define TEGRA_I2S1_SIZE SZ_256
142
143#define TEGRA_I2S2_BASE 0x70002A00
144#define TEGRA_I2S2_SIZE SZ_256
145
146#define TEGRA_UARTA_BASE 0x70006000 78#define TEGRA_UARTA_BASE 0x70006000
147#define TEGRA_UARTA_SIZE SZ_64 79#define TEGRA_UARTA_SIZE SZ_64
148 80
@@ -158,87 +90,15 @@
158#define TEGRA_UARTE_BASE 0x70006400 90#define TEGRA_UARTE_BASE 0x70006400
159#define TEGRA_UARTE_SIZE SZ_256 91#define TEGRA_UARTE_SIZE SZ_256
160 92
161#define TEGRA_NAND_BASE 0x70008000
162#define TEGRA_NAND_SIZE SZ_256
163
164#define TEGRA_HSMMC_BASE 0x70008500
165#define TEGRA_HSMMC_SIZE SZ_256
166
167#define TEGRA_SNOR_BASE 0x70009000
168#define TEGRA_SNOR_SIZE SZ_4K
169
170#define TEGRA_PWFM_BASE 0x7000A000
171#define TEGRA_PWFM_SIZE SZ_256
172
173#define TEGRA_PWFM0_BASE 0x7000A000
174#define TEGRA_PWFM0_SIZE 4
175
176#define TEGRA_PWFM1_BASE 0x7000A010
177#define TEGRA_PWFM1_SIZE 4
178
179#define TEGRA_PWFM2_BASE 0x7000A020
180#define TEGRA_PWFM2_SIZE 4
181
182#define TEGRA_PWFM3_BASE 0x7000A030
183#define TEGRA_PWFM3_SIZE 4
184
185#define TEGRA_MIPI_BASE 0x7000B000
186#define TEGRA_MIPI_SIZE SZ_256
187
188#define TEGRA_I2C_BASE 0x7000C000
189#define TEGRA_I2C_SIZE SZ_256
190
191#define TEGRA_TWC_BASE 0x7000C100
192#define TEGRA_TWC_SIZE SZ_256
193
194#define TEGRA_SPI_BASE 0x7000C380
195#define TEGRA_SPI_SIZE 48
196
197#define TEGRA_I2C2_BASE 0x7000C400
198#define TEGRA_I2C2_SIZE SZ_256
199
200#define TEGRA_I2C3_BASE 0x7000C500
201#define TEGRA_I2C3_SIZE SZ_256
202
203#define TEGRA_OWR_BASE 0x7000C600
204#define TEGRA_OWR_SIZE 80
205
206#define TEGRA_DVC_BASE 0x7000D000
207#define TEGRA_DVC_SIZE SZ_512
208
209#define TEGRA_SPI1_BASE 0x7000D400
210#define TEGRA_SPI1_SIZE SZ_512
211
212#define TEGRA_SPI2_BASE 0x7000D600
213#define TEGRA_SPI2_SIZE SZ_512
214
215#define TEGRA_SPI3_BASE 0x7000D800
216#define TEGRA_SPI3_SIZE SZ_512
217
218#define TEGRA_SPI4_BASE 0x7000DA00
219#define TEGRA_SPI4_SIZE SZ_512
220
221#define TEGRA_RTC_BASE 0x7000E000
222#define TEGRA_RTC_SIZE SZ_256
223
224#define TEGRA_KBC_BASE 0x7000E200
225#define TEGRA_KBC_SIZE SZ_256
226
227#define TEGRA_PMC_BASE 0x7000E400 93#define TEGRA_PMC_BASE 0x7000E400
228#define TEGRA_PMC_SIZE SZ_256 94#define TEGRA_PMC_SIZE SZ_256
229 95
230#define TEGRA_MC_BASE 0x7000F000
231#define TEGRA_MC_SIZE SZ_1K
232
233#define TEGRA_EMC_BASE 0x7000F400 96#define TEGRA_EMC_BASE 0x7000F400
234#define TEGRA_EMC_SIZE SZ_1K 97#define TEGRA_EMC_SIZE SZ_1K
235 98
236#define TEGRA_FUSE_BASE 0x7000F800 99#define TEGRA_FUSE_BASE 0x7000F800
237#define TEGRA_FUSE_SIZE SZ_1K 100#define TEGRA_FUSE_SIZE SZ_1K
238 101
239#define TEGRA_KFUSE_BASE 0x7000FC00
240#define TEGRA_KFUSE_SIZE SZ_1K
241
242#define TEGRA_EMC0_BASE 0x7001A000 102#define TEGRA_EMC0_BASE 0x7001A000
243#define TEGRA_EMC0_SIZE SZ_2K 103#define TEGRA_EMC0_SIZE SZ_2K
244 104
@@ -248,18 +108,6 @@
248#define TEGRA_CSITE_BASE 0x70040000 108#define TEGRA_CSITE_BASE 0x70040000
249#define TEGRA_CSITE_SIZE SZ_256K 109#define TEGRA_CSITE_SIZE SZ_256K
250 110
251#define TEGRA_SDMMC1_BASE 0xC8000000
252#define TEGRA_SDMMC1_SIZE SZ_512
253
254#define TEGRA_SDMMC2_BASE 0xC8000200
255#define TEGRA_SDMMC2_SIZE SZ_512
256
257#define TEGRA_SDMMC3_BASE 0xC8000400
258#define TEGRA_SDMMC3_SIZE SZ_512
259
260#define TEGRA_SDMMC4_BASE 0xC8000600
261#define TEGRA_SDMMC4_SIZE SZ_512
262
263/* On TEGRA, many peripherals are very closely packed in 111/* On TEGRA, many peripherals are very closely packed in
264 * two 256MB io windows (that actually only use about 64KB 112 * two 256MB io windows (that actually only use about 64KB
265 * at the start of each). 113 * at the start of each).
diff --git a/arch/arm/mach-tegra/irammap.h b/arch/arm/mach-tegra/irammap.h
index 501952a84344..e32e1742c9a1 100644
--- a/arch/arm/mach-tegra/irammap.h
+++ b/arch/arm/mach-tegra/irammap.h
@@ -23,4 +23,10 @@
23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K 24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
25 25
26/*
27 * This area is used for LPx resume vector, only while LPx power state is
28 * active. At other times, the AVP may use this area for arbitrary purposes
29 */
30#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K)
31
26#endif 32#endif
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index ed294a04e1d3..36ed88af1cc1 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -263,10 +263,10 @@ static void tegra_suspend_enter_lp1(void)
263 tegra_pmc_suspend(); 263 tegra_pmc_suspend();
264 264
265 /* copy the reset vector & SDRAM shutdown code into IRAM */ 265 /* copy the reset vector & SDRAM shutdown code into IRAM */
266 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA), 266 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
267 iram_save_size);
268 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
269 iram_save_size); 267 iram_save_size);
268 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
269 tegra_lp1_iram.start_addr, iram_save_size);
270 270
271 *((u32 *)tegra_cpu_lp1_mask) = 1; 271 *((u32 *)tegra_cpu_lp1_mask) = 1;
272} 272}
@@ -276,7 +276,7 @@ static void tegra_suspend_exit_lp1(void)
276 tegra_pmc_resume(); 276 tegra_pmc_resume();
277 277
278 /* restore IRAM */ 278 /* restore IRAM */
279 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr, 279 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
280 iram_save_size); 280 iram_save_size);
281 281
282 *(u32 *)tegra_cpu_lp1_mask = 0; 282 *(u32 *)tegra_cpu_lp1_mask = 0;
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index fe204e5256e7..6e92a7c2ecbd 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -37,9 +37,6 @@ void tegra30_sleep_core_init(void);
37 37
38extern unsigned long l2x0_saved_regs_addr; 38extern unsigned long l2x0_saved_regs_addr;
39 39
40void save_cpu_arch_register(void);
41void restore_cpu_arch_register(void);
42
43void tegra_clear_cpu_in_lp2(void); 40void tegra_clear_cpu_in_lp2(void);
44bool tegra_set_cpu_in_lp2(void); 41bool tegra_set_cpu_in_lp2(void);
45 42
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 7916ff91f969..93a4dbcde27e 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -166,6 +166,15 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
166 return tegra_pmc_powergate_remove_clamping(id); 166 return tegra_pmc_powergate_remove_clamping(id);
167} 167}
168 168
169void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
170{
171 u32 val;
172
173 val = tegra_pmc_readl(0);
174 val |= 0x10;
175 tegra_pmc_writel(val, 0);
176}
177
169#ifdef CONFIG_PM_SLEEP 178#ifdef CONFIG_PM_SLEEP
170static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) 179static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
171{ 180{
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 4d5f8f32225c..59e19c344298 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,8 @@
18#ifndef __MACH_TEGRA_PMC_H 18#ifndef __MACH_TEGRA_PMC_H
19#define __MACH_TEGRA_PMC_H 19#define __MACH_TEGRA_PMC_H
20 20
21#include <linux/reboot.h>
22
21enum tegra_suspend_mode { 23enum tegra_suspend_mode {
22 TEGRA_SUSPEND_NONE = 0, 24 TEGRA_SUSPEND_NONE = 0,
23 TEGRA_SUSPEND_LP2, /* CPU voltage off */ 25 TEGRA_SUSPEND_LP2, /* CPU voltage off */
@@ -39,6 +41,8 @@ bool tegra_pmc_cpu_is_powered(int cpuid);
39int tegra_pmc_cpu_power_on(int cpuid); 41int tegra_pmc_cpu_power_on(int cpuid);
40int tegra_pmc_cpu_remove_clamping(int cpuid); 42int tegra_pmc_cpu_remove_clamping(int cpuid);
41 43
44void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
45
42void tegra_pmc_init_irq(void); 46void tegra_pmc_init_irq(void);
43void tegra_pmc_init(void); 47void tegra_pmc_init(void);
44 48
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index fd0bbf8a6c94..568f5bbf979d 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -82,7 +82,7 @@ void __init tegra_cpu_reset_handler_init(void)
82 82
83#ifdef CONFIG_PM_SLEEP 83#ifdef CONFIG_PM_SLEEP
84 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = 84 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
85 TEGRA_IRAM_CODE_AREA; 85 TEGRA_IRAM_LPx_RESUME_AREA;
86 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = 86 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
87 virt_to_phys((void *)tegra_resume); 87 virt_to_phys((void *)tegra_resume);
88#endif 88#endif
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 5c3bd11c9838..aaaf3abd2688 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -25,6 +25,7 @@
25#include <asm/cp15.h> 25#include <asm/cp15.h>
26#include <asm/cache.h> 26#include <asm/cache.h>
27 27
28#include "irammap.h"
28#include "sleep.h" 29#include "sleep.h"
29#include "flowctrl.h" 30#include "flowctrl.h"
30 31
@@ -235,7 +236,7 @@ ENTRY(tegra20_sleep_core_finish)
235 mov32 r0, tegra20_tear_down_core 236 mov32 r0, tegra20_tear_down_core
236 mov32 r1, tegra20_iram_start 237 mov32 r1, tegra20_iram_start
237 sub r0, r0, r1 238 sub r0, r0, r1
238 mov32 r1, TEGRA_IRAM_CODE_AREA 239 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
239 add r0, r0, r1 240 add r0, r0, r1
240 241
241 mov pc, r3 242 mov pc, r3
@@ -328,7 +329,7 @@ tegra20_iram_start:
328 * The physical address of tegra_resume expected to be stored in 329 * The physical address of tegra_resume expected to be stored in
329 * PMC_SCRATCH41. 330 * PMC_SCRATCH41.
330 * 331 *
331 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. 332 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
332 */ 333 */
333ENTRY(tegra20_lp1_reset) 334ENTRY(tegra20_lp1_reset)
334 /* 335 /*
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 63fa91b5fafb..c6fc15cb25df 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -20,6 +20,7 @@
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/cache.h> 21#include <asm/cache.h>
22 22
23#include "irammap.h"
23#include "fuse.h" 24#include "fuse.h"
24#include "sleep.h" 25#include "sleep.h"
25#include "flowctrl.h" 26#include "flowctrl.h"
@@ -262,7 +263,7 @@ ENTRY(tegra30_sleep_core_finish)
262 mov32 r0, tegra30_tear_down_core 263 mov32 r0, tegra30_tear_down_core
263 mov32 r1, tegra30_iram_start 264 mov32 r1, tegra30_iram_start
264 sub r0, r0, r1 265 sub r0, r0, r1
265 mov32 r1, TEGRA_IRAM_CODE_AREA 266 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
266 add r0, r0, r1 267 add r0, r0, r1
267 268
268 mov pc, r3 269 mov pc, r3
@@ -314,7 +315,7 @@ tegra30_iram_start:
314 * The physical address of tegra_resume expected to be stored in 315 * The physical address of tegra_resume expected to be stored in
315 * PMC_SCRATCH41. 316 * PMC_SCRATCH41.
316 * 317 *
317 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. 318 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
318 */ 319 */
319ENTRY(tegra30_lp1_reset) 320ENTRY(tegra30_lp1_reset)
320 /* 321 /*
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 2e2192807830..386115ae5c03 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -33,17 +33,78 @@
33#include <linux/sys_soc.h> 33#include <linux/sys_soc.h>
34#include <linux/usb/tegra_usb_phy.h> 34#include <linux/usb/tegra_usb_phy.h>
35#include <linux/clk/tegra.h> 35#include <linux/clk/tegra.h>
36#include <linux/irqchip.h>
36 37
38#include <asm/hardware/cache-l2x0.h>
37#include <asm/mach-types.h> 39#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 40#include <asm/mach/arch.h>
39#include <asm/mach/time.h> 41#include <asm/mach/time.h>
40#include <asm/setup.h> 42#include <asm/setup.h>
41 43
44#include "apbio.h"
42#include "board.h" 45#include "board.h"
43#include "common.h" 46#include "common.h"
47#include "cpuidle.h"
44#include "fuse.h" 48#include "fuse.h"
45#include "iomap.h" 49#include "iomap.h"
50#include "irq.h"
46#include "pmc.h" 51#include "pmc.h"
52#include "pm.h"
53#include "reset.h"
54#include "sleep.h"
55
56/*
57 * Storage for debug-macro.S's state.
58 *
59 * This must be in .data not .bss so that it gets initialized each time the
60 * kernel is loaded. The data is declared here rather than debug-macro.S so
61 * that multiple inclusions of debug-macro.S point at the same data.
62 */
63u32 tegra_uart_config[4] = {
64 /* Debug UART initialization required */
65 1,
66 /* Debug UART physical address */
67 0,
68 /* Debug UART virtual address */
69 0,
70 /* Scratch space for debug macro */
71 0,
72};
73
74static void __init tegra_init_cache(void)
75{
76#ifdef CONFIG_CACHE_L2X0
77 int ret;
78 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
79 u32 aux_ctrl, cache_type;
80
81 cache_type = readl(p + L2X0_CACHE_TYPE);
82 aux_ctrl = (cache_type & 0x700) << (17-8);
83 aux_ctrl |= 0x7C400001;
84
85 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
86 if (!ret)
87 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
88#endif
89}
90
91static void __init tegra_init_early(void)
92{
93 tegra_cpu_reset_handler_init();
94 tegra_apb_io_init();
95 tegra_init_fuse();
96 tegra_init_cache();
97 tegra_powergate_init();
98 tegra_hotplug_init();
99}
100
101static void __init tegra_dt_init_irq(void)
102{
103 tegra_pmc_init_irq();
104 tegra_init_irq();
105 irqchip_init();
106 tegra_legacy_irq_syscore_init();
107}
47 108
48static void __init tegra_dt_init(void) 109static void __init tegra_dt_init(void)
49{ 110{
@@ -99,7 +160,9 @@ static void __init tegra_dt_init_late(void)
99{ 160{
100 int i; 161 int i;
101 162
102 tegra_init_late(); 163 tegra_init_suspend();
164 tegra_cpuidle_init();
165 tegra_powergate_debugfs_init();
103 166
104 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { 167 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
105 if (of_machine_is_compatible(board_init_funcs[i].machine)) { 168 if (of_machine_is_compatible(board_init_funcs[i].machine)) {
@@ -123,6 +186,6 @@ DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
123 .init_irq = tegra_dt_init_irq, 186 .init_irq = tegra_dt_init_irq,
124 .init_machine = tegra_dt_init, 187 .init_machine = tegra_dt_init,
125 .init_late = tegra_dt_init_late, 188 .init_late = tegra_dt_init_late,
126 .restart = tegra_assert_system_reset, 189 .restart = tegra_pmc_restart,
127 .dt_compat = tegra_dt_board_compat, 190 .dt_compat = tegra_dt_board_compat,
128MACHINE_END 191MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 01:33:21 -0400