Merge tag 'renesas-clock-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

Merge "Renesas ARM Based SoC Clock Updates for v3.15" from Simon Horman:

* r7s72100 SoC (RZ/A1H)
  - Add clock for SH Ethernet
  - Add RSPI clocks

* r8a7791 (R-Car M2)
  - Add QSPI and SDHI clocks

* r8a7790 (R-Car H2)
  - Add audio clock
  - Remove legacy DT clocks
  - Correct SYS DMAC clock defines

* tag 'renesas-clock-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: Remove legacy r8a7790 DT clocks
  ARM: shmobile: Add r8a7791 legacy SDHI clocks
  ARM: shmobile: r8a7790: Correct SYS DMAC clock defines
  ARM: shmobile: r7s72100: Add clock for r7s72100-ether
  ARM: shmobile: r8a7791 clock: add QSPI clocks
  ARM: shmobile: r7s72100 clock: Add RSPI clocks for DT
  ARM: shmobile: r7s72100 clock: Add RSPI clocks
  ARM: shmobile: r8a7790: add audio clock
  ARM: shmobile: r8a7778: add audio clock in new style

Signed-off-by: Olof Johansson <olof@lixom.net>

4 files changed, 111 insertions, 16 deletions

diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index dd8ce87596de..f17a5db00221 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -22,12 +22,15 @@
 #include <mach/common.h>
 #include <mach/r7s72100.h>
 
-/* registers */
+/* Frequency Control Registers */
 #define FRQCR           0xfcfe0010
 #define FRQCR2          0xfcfe0014
+/* Standby Control Registers */
 #define STBCR3          0xfcfe0420
 #define STBCR4          0xfcfe0424
+#define STBCR7          0xfcfe0430
 #define STBCR9          0xfcfe0438
+#define STBCR10         0xfcfe043c
 
 #define PLL_RATE 30
 
@@ -145,15 +148,25 @@ struct clk div4_clks[DIV4_NR] = {
                                         | CLK_ENABLE_ON_INIT),
 };
 
-enum {  MSTP97, MSTP96, MSTP95, MSTP94,
+enum {
+        MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
+        MSTP97, MSTP96, MSTP95, MSTP94,
+        MSTP74,
         MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
-        MSTP33, MSTP_NR };
+        MSTP33, MSTP_NR
+};
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
+        [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
+        [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
+        [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
+        [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
         [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
         [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
         [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
         [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
+        [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
         [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
         [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
         [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
@@ -176,10 +189,21 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 
         /* MSTP clocks */
+        CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
+        CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
+        CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
+        CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
+        CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
+        CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
+        CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
+        CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
+        CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
+        CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
         CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
         CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
         CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
         CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
+        CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
         CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
 
         /* ICK */
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 9783945f8bc7..2009a9bc6356 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -221,6 +221,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
         CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
 
+        CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
+        CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
+        CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
+        CLKDEV_ICK_ID("clk_i", "rcar_sound", &s1_clk),
         CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
         CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
         CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 507073e9d455..02b940361a66 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -91,6 +91,15 @@ static struct clk main_clk = {
         .ops    = &followparent_clk_ops,
 };
 
+static struct clk audio_clk_a = {
+};
+
+static struct clk audio_clk_b = {
+};
+
+static struct clk audio_clk_c = {
+};
+
 /*
  * clock ratio of these clock will be updated
  * on r8a7790_clock_init()
@@ -124,6 +133,9 @@ SH_FIXED_RATIO_CLK_SET(ddr_clk,			pll3_clk,	1, 8);
 SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
 
 static struct clk *main_clks[] = {
+        &audio_clk_a,
+        &audio_clk_b,
+        &audio_clk_c,
         &extal_clk,
         &extal_div2_clk,
         &main_clk,
@@ -267,6 +279,10 @@ static struct clk mstp_clks[MSTP_NR] = {
 static struct clk_lookup lookups[] = {
 
         /* main clocks */
+        CLKDEV_CON_ID("audio_clk_a",    &audio_clk_a),
+        CLKDEV_CON_ID("audio_clk_b",    &audio_clk_b),
+        CLKDEV_CON_ID("audio_clk_c",    &audio_clk_c),
+        CLKDEV_CON_ID("audio_clk_internal",     &m2_clk),
         CLKDEV_CON_ID("extal",          &extal_clk),
         CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
         CLKDEV_CON_ID("main",           &main_clk),
@@ -312,34 +328,23 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
-        CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
         CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
-        CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
         CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
-        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
         CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
-        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
         CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
         CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
         CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
         CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
         CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
         CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
-        CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
         CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
-        CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
-        CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
         CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
@@ -357,6 +362,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
         CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
         CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
+        CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
+        CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
+        CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
+        CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
         CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
         CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
         CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index e4e4dfac85e9..3e1b6b699184 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -61,6 +61,7 @@
 
 #define MSTPSR1         IOMEM(0xe6150038)
 #define MSTPSR2         IOMEM(0xe6150040)
+#define MSTPSR3         IOMEM(0xe6150048)
 #define MSTPSR5         IOMEM(0xe615003c)
 #define MSTPSR7         IOMEM(0xe61501c4)
 #define MSTPSR8         IOMEM(0xe61509a0)
@@ -69,8 +70,8 @@
 
 #define MODEMR          0xE6160060
 #define SDCKCR          0xE6150074
-#define SD2CKCR         0xE6150078
-#define SD3CKCR         0xE615007C
+#define SD1CKCR         0xE6150078
+#define SD2CKCR         0xE615026c
 #define MMC0CKCR        0xE6150240
 #define MMC1CKCR        0xE6150244
 #define SSPCKCR         0xE6150248
@@ -101,6 +102,7 @@ static struct clk main_clk = {
  */
 SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
 SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
 
 /* fixed ratio clock */
 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
@@ -124,6 +126,7 @@ static struct clk *main_clks[] = {
         &pll3_clk,
         &hp_clk,
         &p_clk,
+        &qspi_clk,
         &rclk_clk,
         &mp_clk,
         &cp_clk,
@@ -132,15 +135,50 @@ static struct clk *main_clks[] = {
         &zs_clk,
 };
 
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum {
+        DIV4_SDH, DIV4_SD0,
+        DIV4_NR
+};
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+
+/* DIV6 clocks */
+enum {
+        DIV6_SD1, DIV6_SD2,
+        DIV6_NR
+};
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SD1]      = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
+        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+};
+
 /* MSTP */
 enum {
         MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
+        MSTP917,
         MSTP815, MSTP814,
         MSTP813,
         MSTP811, MSTP810, MSTP809,
         MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
         MSTP719, MSTP718, MSTP715, MSTP714,
         MSTP522,
+        MSTP314, MSTP312, MSTP311,
         MSTP216, MSTP207, MSTP206,
         MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
         MSTP124,
@@ -154,6 +192,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
         [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
         [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
+        [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
         [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
         [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
         [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
@@ -170,6 +209,9 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
         [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
         [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
+        [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
+        [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
+        [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
         [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
         [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
         [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
@@ -195,6 +237,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("zs",             &zs_clk),
         CLKDEV_CON_ID("hp",             &hp_clk),
         CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("qspi",           &qspi_clk),
         CLKDEV_CON_ID("rclk",           &rclk_clk),
         CLKDEV_CON_ID("mp",             &mp_clk),
         CLKDEV_CON_ID("cp",             &cp_clk),
@@ -219,7 +262,11 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
         CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
         CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+        CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
@@ -271,10 +318,21 @@ void __init r8a7791_clock_init(void)
                 break;
         }
 
+        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+        else
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));