ARM: mach-shmobile: sh7372 A4R support (v4)

This change adds support for the sh7372 A4R power domain.

The sh7372 A4R hardware power domain contains the
SH CPU Core and a set of I/O devices including
multimedia accelerators and I2C controllers.

One special case about A4R is the INTCS interrupt
controller that needs to be saved and restored to
keep working as expected. Also the LCDC hardware
blocks are in a different hardware power domain
but have their IRQs routed only through INTCS. So
as long as LCDCs are active we cannot power down
INTCS because that would risk losing interrupts.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>

1 files changed, 51 insertions, 1 deletions

diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 739315e30eb9..29cdc0522d9c 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -606,9 +606,16 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc)
         generic_handle_irq(intcs_evt2irq(evtcodeas));
 }
 
+static void __iomem *intcs_ffd2;
+static void __iomem *intcs_ffd5;
+
 void __init sh7372_init_irq(void)
 {
-        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+        void __iomem *intevtsa;
+
+        intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
+        intevtsa = intcs_ffd2 + 0x100;
+        intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
 
         register_intc_controller(&intca_desc);
         register_intc_controller(&intcs_desc);
@@ -617,3 +624,46 @@ void __init sh7372_init_irq(void)
         irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
         irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
 }
+
+static unsigned short ffd2[0x200];
+static unsigned short ffd5[0x100];
+
+void sh7372_intcs_suspend(void)
+{
+        int k;
+
+        for (k = 0x00; k <= 0x30; k += 4)
+                ffd2[k] = __raw_readw(intcs_ffd2 + k);
+
+        for (k = 0x80; k <= 0xb0; k += 4)
+                ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+        for (k = 0x180; k <= 0x188; k += 4)
+                ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+        for (k = 0x00; k <= 0x3c; k += 4)
+                ffd5[k] = __raw_readw(intcs_ffd5 + k);
+
+        for (k = 0x80; k <= 0x9c; k += 4)
+                ffd5[k] = __raw_readb(intcs_ffd5 + k);
+}
+
+void sh7372_intcs_resume(void)
+{
+        int k;
+
+        for (k = 0x00; k <= 0x30; k += 4)
+                __raw_writew(ffd2[k], intcs_ffd2 + k);
+
+        for (k = 0x80; k <= 0xb0; k += 4)
+                __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+        for (k = 0x180; k <= 0x188; k += 4)
+                __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+        for (k = 0x00; k <= 0x3c; k += 4)
+                __raw_writew(ffd5[k], intcs_ffd5 + k);
+
+        for (k = 0x80; k <= 0x9c; k += 4)
+                __raw_writeb(ffd5[k], intcs_ffd5 + k);
+}