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authorTero Kristo <t-kristo@ti.com>2013-10-11 12:15:34 -0400
committerPaul Walmsley <paul@pwsan.com>2013-10-19 12:11:52 -0400
commitc6a2d839d0dba8a06f55c7b06f8ce33bdbe4aea3 (patch)
tree29e69f442137dc6e16cb6f9a083b5b3846a7632f /arch/arm/mach-omap2/control.c
parent7a90da2ad3fdd44a6230c0e2c0a374a5cda1711c (diff)
ARM: OMAP3: CM/control: move CM scratchpad save to CM driver
OMAP3 PM code for off-mode currently saves the scratchpad contents for CM registers within OMAP control module driver. However, as we are separating CM code into its own driver, this must be moved also. This patch adds a new API for saving the CM scratchpad contents and uses this from the high level scratchpad save function. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/control.c')
-rw-r--r--arch/arm/mach-omap2/control.c43
1 files changed, 4 insertions, 39 deletions
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 31e0dfe4a4ea..a59711454543 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -46,17 +46,7 @@ struct omap3_scratchpad {
46struct omap3_scratchpad_prcm_block { 46struct omap3_scratchpad_prcm_block {
47 u32 prm_clksrc_ctrl; 47 u32 prm_clksrc_ctrl;
48 u32 prm_clksel; 48 u32 prm_clksel;
49 u32 cm_clksel_core; 49 u32 cm_contents[11];
50 u32 cm_clksel_wkup;
51 u32 cm_clken_pll;
52 u32 cm_autoidle_pll;
53 u32 cm_clksel1_pll;
54 u32 cm_clksel2_pll;
55 u32 cm_clksel3_pll;
56 u32 cm_clken_pll_mpu;
57 u32 cm_autoidle_pll_mpu;
58 u32 cm_clksel1_pll_mpu;
59 u32 cm_clksel2_pll_mpu;
60 u32 prcm_block_size; 50 u32 prcm_block_size;
61}; 51};
62 52
@@ -347,34 +337,9 @@ void omap3_save_scratchpad_contents(void)
347 prcm_block_contents.prm_clksel = 337 prcm_block_contents.prm_clksel =
348 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, 338 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
349 OMAP3_PRM_CLKSEL_OFFSET); 339 OMAP3_PRM_CLKSEL_OFFSET);
350 prcm_block_contents.cm_clksel_core = 340
351 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 341 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
352 prcm_block_contents.cm_clksel_wkup = 342
353 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
354 prcm_block_contents.cm_clken_pll =
355 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
356 /*
357 * As per erratum i671, ROM code does not respect the PER DPLL
358 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
359 * Then, in anycase, clear these bits to avoid extra latencies.
360 */
361 prcm_block_contents.cm_autoidle_pll =
362 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
363 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
364 prcm_block_contents.cm_clksel1_pll =
365 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
366 prcm_block_contents.cm_clksel2_pll =
367 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
368 prcm_block_contents.cm_clksel3_pll =
369 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
370 prcm_block_contents.cm_clken_pll_mpu =
371 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
372 prcm_block_contents.cm_autoidle_pll_mpu =
373 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
374 prcm_block_contents.cm_clksel1_pll_mpu =
375 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
376 prcm_block_contents.cm_clksel2_pll_mpu =
377 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
378 prcm_block_contents.prcm_block_size = 0x0; 343 prcm_block_contents.prcm_block_size = 0x0;
379 344
380 /* Populate the SDRC block contents */ 345 /* Populate the SDRC block contents */