diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 07:30:20 -0500 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 07:42:17 -0500 |
commit | 237c78beb8a988453bac1993d21f025d070a0d8d (patch) | |
tree | 9864f0924650770881141359a2d5bac623949789 /arch/arm/mach-imx/src.c | |
parent | 4eb821999086417ab42a15174b51497122fc406e (diff) | |
parent | 7b9dd47136c07ffd883aff6926c7b281e4c1eea4 (diff) |
Merge branch 'depends/rmk/for-linus' into samsung/dt
Conflicts:
arch/arm/mach-exynos/Makefile
arch/arm/mach-exynos/cpu.c -> common.c
arch/arm/mach-exynos/include/mach/entry-macro.S
arch/arm/mach-exynos/init.c -> common.c
arch/arm/mach-s5p64x0/init.c -> common.c
arch/arm/mach-s5pv210/init.c -> common.c
Multiple files were moved into common.c files in the rmk/for-linus
branch, so this moves over the samsung/dt changes to the new
files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/src.c')
-rw-r--r-- | arch/arm/mach-imx/src.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index a8e33681b732..4bde04f99e38 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c | |||
@@ -19,6 +19,7 @@ | |||
19 | 19 | ||
20 | #define SRC_SCR 0x000 | 20 | #define SRC_SCR 0x000 |
21 | #define SRC_GPR1 0x020 | 21 | #define SRC_GPR1 0x020 |
22 | #define BP_SRC_SCR_WARM_RESET_ENABLE 0 | ||
22 | #define BP_SRC_SCR_CORE1_RST 14 | 23 | #define BP_SRC_SCR_CORE1_RST 14 |
23 | #define BP_SRC_SCR_CORE1_ENABLE 22 | 24 | #define BP_SRC_SCR_CORE1_ENABLE 22 |
24 | 25 | ||
@@ -46,11 +47,33 @@ void imx_set_cpu_jump(int cpu, void *jump_addr) | |||
46 | src_base + SRC_GPR1 + cpu * 8); | 47 | src_base + SRC_GPR1 + cpu * 8); |
47 | } | 48 | } |
48 | 49 | ||
50 | void imx_src_prepare_restart(void) | ||
51 | { | ||
52 | u32 val; | ||
53 | |||
54 | /* clear enable bits of secondary cores */ | ||
55 | val = readl_relaxed(src_base + SRC_SCR); | ||
56 | val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); | ||
57 | writel_relaxed(val, src_base + SRC_SCR); | ||
58 | |||
59 | /* clear persistent entry register of primary core */ | ||
60 | writel_relaxed(0, src_base + SRC_GPR1); | ||
61 | } | ||
62 | |||
49 | void __init imx_src_init(void) | 63 | void __init imx_src_init(void) |
50 | { | 64 | { |
51 | struct device_node *np; | 65 | struct device_node *np; |
66 | u32 val; | ||
52 | 67 | ||
53 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); | 68 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); |
54 | src_base = of_iomap(np, 0); | 69 | src_base = of_iomap(np, 0); |
55 | WARN_ON(!src_base); | 70 | WARN_ON(!src_base); |
71 | |||
72 | /* | ||
73 | * force warm reset sources to generate cold reset | ||
74 | * for a more reliable restart | ||
75 | */ | ||
76 | val = readl_relaxed(src_base + SRC_SCR); | ||
77 | val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); | ||
78 | writel_relaxed(val, src_base + SRC_SCR); | ||
56 | } | 79 | } |