ARM: imx: Add Freescale LS1021A SMP support

Freescale LS1021A SoCs deploy two cortex-A7 processors,
this adds bring-up support for the secondary core.

Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 33 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 771bd25c1025..7f270015fe58 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -11,7 +11,10 @@
  */
 
 #include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/smp.h>
+
 #include <asm/cacheflush.h>
 #include <asm/page.h>
 #include <asm/smp_scu.h>
@@ -94,3 +97,33 @@ struct smp_operations  imx_smp_ops __initdata = {
         .cpu_kill               = imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1    0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+        return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *np;
+        void __iomem *dcfg_base;
+        unsigned long paddr;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+        dcfg_base = of_iomap(np, 0);
+        BUG_ON(!dcfg_base);
+
+        paddr = virt_to_phys(secondary_startup);
+        writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+
+        iounmap(dcfg_base);
+}
+
+struct smp_operations  ls1021a_smp_ops __initdata = {
+        .smp_prepare_cpus       = ls1021a_smp_prepare_cpus,
+        .smp_boot_secondary     = ls1021a_boot_secondary,
+};