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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-04-05 06:45:34 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-29 19:49:12 -0400
commit25a9ef63cd2beb248e51bd192df19fbe5cf20545 (patch)
tree994becfba0c4e538b21c4a8f5fadf485502e94fc /arch/arm/mach-exynos/sleep.S
parentdfbdd3d55403ebd29a355e907e53576ce57c6d96 (diff)
ARM: l2c: exynos: convert to common l2c310 early resume functionality
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-exynos/sleep.S')
-rw-r--r--arch/arm/mach-exynos/sleep.S30
1 files changed, 1 insertions, 29 deletions
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index 7e0af530511e..108a45f4bb62 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -16,8 +16,6 @@
16 */ 16 */
17 17
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <asm/asm-offsets.h>
20#include <asm/hardware/cache-l2x0.h>
21 19
22#define CPU_MASK 0xff0ffff0 20#define CPU_MASK 0xff0ffff0
23#define CPU_CORTEX_A9 0x410fc090 21#define CPU_CORTEX_A9 0x410fc090
@@ -53,33 +51,7 @@ ENTRY(exynos_cpu_resume)
53 and r0, r0, r1 51 and r0, r0, r1
54 ldr r1, =CPU_CORTEX_A9 52 ldr r1, =CPU_CORTEX_A9
55 cmp r0, r1 53 cmp r0, r1
56 bne skip_l2_resume 54 bleq l2c310_early_resume
57 adr r0, l2x0_regs_phys
58 ldr r0, [r0]
59 cmp r0, #0
60 beq skip_l2_resume
61 ldr r1, [r0, #L2X0_R_PHY_BASE]
62 ldr r2, [r1, #L2X0_CTRL]
63 tst r2, #0x1
64 bne skip_l2_resume
65 ldr r2, [r0, #L2X0_R_AUX_CTRL]
66 str r2, [r1, #L2X0_AUX_CTRL]
67 ldr r2, [r0, #L2X0_R_TAG_LATENCY]
68 str r2, [r1, #L310_TAG_LATENCY_CTRL]
69 ldr r2, [r0, #L2X0_R_DATA_LATENCY]
70 str r2, [r1, #L310_DATA_LATENCY_CTRL]
71 ldr r2, [r0, #L2X0_R_PREFETCH_CTRL]
72 str r2, [r1, #L310_PREFETCH_CTRL]
73 ldr r2, [r0, #L2X0_R_PWR_CTRL]
74 str r2, [r1, #L310_POWER_CTRL]
75 mov r2, #1
76 str r2, [r1, #L2X0_CTRL]
77skip_l2_resume:
78#endif 55#endif
79 b cpu_resume 56 b cpu_resume
80ENDPROC(exynos_cpu_resume) 57ENDPROC(exynos_cpu_resume)
81#ifdef CONFIG_CACHE_L2X0
82 .globl l2x0_regs_phys
83l2x0_regs_phys:
84 .long 0
85#endif