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authorCatalin Marinas <catalin.marinas@arm.com>2013-01-14 13:05:37 -0500
committerCatalin Marinas <catalin.marinas@arm.com>2013-03-26 12:12:02 -0400
commitc0114709ed85a5693eb74acdfa03d94f7f12e5b8 (patch)
tree372c5cee96580d73e638d25a2b169a64b82bc908 /arch/arm/mach-exynos/platsmp.c
parentaec0095653cd9812b9a15df0315364cc6d094c59 (diff)
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Tested-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Barry Song <baohua.song@csr.com>
Diffstat (limited to 'arch/arm/mach-exynos/platsmp.c')
-rw-r--r--arch/arm/mach-exynos/platsmp.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 60f7c5be057d..95e04bd5813f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,7 +20,6 @@
20#include <linux/jiffies.h> 20#include <linux/jiffies.h>
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/irqchip/arm-gic.h>
24 23
25#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
26#include <asm/smp_plat.h> 25#include <asm/smp_plat.h>
@@ -76,13 +75,6 @@ static DEFINE_SPINLOCK(boot_lock);
76static void __cpuinit exynos_secondary_init(unsigned int cpu) 75static void __cpuinit exynos_secondary_init(unsigned int cpu)
77{ 76{
78 /* 77 /*
79 * if any interrupts are already enabled for the primary
80 * core (e.g. timer irq), then they will not have been enabled
81 * for us: do so
82 */
83 gic_secondary_init(0);
84
85 /*
86 * let the primary processor know we're out of the 78 * let the primary processor know we're out of the
87 * pen, then head off into the C entry point 79 * pen, then head off into the C entry point
88 */ 80 */