diff options
author | Alexander Shiyan <shc_work@mail.ru> | 2013-05-13 13:07:28 -0400 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2013-06-11 18:47:26 -0400 |
commit | be95f7aaacd8a070c97ac5b63911e09481989956 (patch) | |
tree | 9e5f40498654d41d6c34ad7180061a025ff869c0 /arch/arm/mach-clps711x | |
parent | d29268ceb8f500be5fa4636b1335c974250c0f34 (diff) |
ARM: clps711x: autcpu12: Move remaining specific definitions to board file
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-clps711x')
-rw-r--r-- | arch/arm/mach-clps711x/board-autcpu12.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-clps711x/include/mach/autcpu12.h | 44 |
2 files changed, 8 insertions, 45 deletions
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index 91a3ab50fc20..cd503149d30b 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c | |||
@@ -42,7 +42,6 @@ | |||
42 | #include <asm/page.h> | 42 | #include <asm/page.h> |
43 | 43 | ||
44 | #include <asm/mach/map.h> | 44 | #include <asm/mach/map.h> |
45 | #include <mach/autcpu12.h> | ||
46 | 45 | ||
47 | #include "common.h" | 46 | #include "common.h" |
48 | #include "devices.h" | 47 | #include "devices.h" |
@@ -50,6 +49,14 @@ | |||
50 | /* NOR flash */ | 49 | /* NOR flash */ |
51 | #define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE) | 50 | #define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE) |
52 | 51 | ||
52 | /* Board specific hardware definitions */ | ||
53 | #define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000) | ||
54 | #define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000) | ||
55 | #define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000) | ||
56 | #define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000) | ||
57 | #define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000) | ||
58 | #define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000) | ||
59 | |||
53 | /* NVRAM */ | 60 | /* NVRAM */ |
54 | #define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000) | 61 | #define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000) |
55 | 62 | ||
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h deleted file mode 100644 index 0e00148d46a3..000000000000 --- a/arch/arm/mach-clps711x/include/mach/autcpu12.h +++ /dev/null | |||
@@ -1,44 +0,0 @@ | |||
1 | /* | ||
2 | * AUTCPU12 specific defines | ||
3 | * | ||
4 | * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #ifndef __ASM_ARCH_AUTCPU12_H | ||
21 | #define __ASM_ARCH_AUTCPU12_H | ||
22 | |||
23 | /* offset for device specific information structure */ | ||
24 | #define AUTCPU12_LCDINFO_OFFS (0x00010000) | ||
25 | |||
26 | /* Videomemory in the internal SRAM (CS 6) */ | ||
27 | #define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE | ||
28 | |||
29 | /* | ||
30 | * All special IO's are tied to CS1 | ||
31 | */ | ||
32 | #define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */ | ||
33 | |||
34 | #define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */ | ||
35 | |||
36 | #define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */ | ||
37 | |||
38 | #define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */ | ||
39 | |||
40 | #define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */ | ||
41 | |||
42 | #define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */ | ||
43 | |||
44 | #endif | ||