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authorChen-Yu Tsai <wens@csie.org>2016-09-07 23:25:35 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-09-10 05:50:43 -0400
commitbd33544e25e6c8edffb22257ab7c78ad7957c2b2 (patch)
treeef5ca51595abea3e5eb59cde121f7e30b1544870 /arch/arm/boot
parent3353bedc4d5d014b8ef43dc72a42da9a4659b2e2 (diff)
ARM: dts: sun8i: Move A23/A33 usbphy and usb_otg nodes to common dtsi
The usbphy and usb_otg nodes in the A23 and A33 dts files only differ by compatible, and for the usbphy, the size of one of its register regions. Move all the common bits to the A23/A33 common dtsi file. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi30
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi43
-rw-r--r--arch/arm/boot/dts/sun8i-a33.dtsi41
3 files changed, 50 insertions, 64 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7ea6de12040e..01d8bbf08749 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -202,6 +202,36 @@
202 #size-cells = <0>; 202 #size-cells = <0>;
203 }; 203 };
204 204
205 usb_otg: usb@01c19000 {
206 /* compatible gets set in SoC specific dtsi file */
207 reg = <0x01c19000 0x0400>;
208 clocks = <&ccu CLK_BUS_OTG>;
209 resets = <&ccu RST_BUS_OTG>;
210 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-names = "mc";
212 phys = <&usbphy 0>;
213 phy-names = "usb";
214 extcon = <&usbphy 0>;
215 status = "disabled";
216 };
217
218 usbphy: phy@01c19400 {
219 /*
220 * compatible and address regions get set in
221 * SoC specific dtsi file
222 */
223 clocks = <&ccu CLK_USB_PHY0>,
224 <&ccu CLK_USB_PHY1>;
225 clock-names = "usb0_phy",
226 "usb1_phy";
227 resets = <&ccu RST_USB_PHY0>,
228 <&ccu RST_USB_PHY1>;
229 reset-names = "usb0_reset",
230 "usb1_reset";
231 status = "disabled";
232 #phy-cells = <1>;
233 };
234
205 ehci0: usb@01c1a000 { 235 ehci0: usb@01c1a000 {
206 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 236 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
207 reg = <0x01c1a000 0x100>; 237 reg = <0x01c1a000 0x100>;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index a915feb3a494..54d045dab825 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -48,39 +48,6 @@
48 memory { 48 memory {
49 reg = <0x40000000 0x40000000>; 49 reg = <0x40000000 0x40000000>;
50 }; 50 };
51
52 soc@01c00000 {
53 usb_otg: usb@01c19000 {
54 compatible = "allwinner,sun6i-a31-musb";
55 reg = <0x01c19000 0x0400>;
56 clocks = <&ccu CLK_BUS_OTG>;
57 resets = <&ccu RST_BUS_OTG>;
58 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-names = "mc";
60 phys = <&usbphy 0>;
61 phy-names = "usb";
62 extcon = <&usbphy 0>;
63 status = "disabled";
64 };
65
66 usbphy: phy@01c19400 {
67 compatible = "allwinner,sun8i-a23-usb-phy";
68 reg = <0x01c19400 0x10>,
69 <0x01c1a800 0x4>;
70 reg-names = "phy_ctrl",
71 "pmu1";
72 clocks = <&ccu CLK_USB_PHY0>,
73 <&ccu CLK_USB_PHY1>;
74 clock-names = "usb0_phy",
75 "usb1_phy";
76 resets = <&ccu RST_USB_PHY0>,
77 <&ccu RST_USB_PHY1>;
78 reset-names = "usb0_reset",
79 "usb1_reset";
80 status = "disabled";
81 #phy-cells = <1>;
82 };
83 };
84}; 51};
85 52
86&ccu { 53&ccu {
@@ -93,3 +60,13 @@
93 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 61 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
95}; 62};
63
64&usb_otg {
65 compatible = "allwinner,sun6i-a31-musb";
66};
67
68&usbphy {
69 compatible = "allwinner,sun8i-a23-usb-phy";
70 reg = <0x01c19400 0x10>, <0x01c1a800 0x4>;
71 reg-names = "phy_ctrl", "pmu1";
72};
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 1d21d488cb3e..fd1e1cddd4a8 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -116,37 +116,6 @@
116 reset-names = "ahb"; 116 reset-names = "ahb";
117 }; 117 };
118 118
119 usb_otg: usb@01c19000 {
120 compatible = "allwinner,sun8i-a33-musb";
121 reg = <0x01c19000 0x0400>;
122 clocks = <&ccu CLK_BUS_OTG>;
123 resets = <&ccu RST_BUS_OTG>;
124 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-names = "mc";
126 phys = <&usbphy 0>;
127 phy-names = "usb";
128 extcon = <&usbphy 0>;
129 status = "disabled";
130 };
131
132 usbphy: phy@01c19400 {
133 compatible = "allwinner,sun8i-a33-usb-phy";
134 reg = <0x01c19400 0x14>,
135 <0x01c1a800 0x4>;
136 reg-names = "phy_ctrl",
137 "pmu1";
138 clocks = <&ccu CLK_USB_PHY0>,
139 <&ccu CLK_USB_PHY1>;
140 clock-names = "usb0_phy",
141 "usb1_phy";
142 resets = <&ccu RST_USB_PHY0>,
143 <&ccu RST_USB_PHY1>;
144 reset-names = "usb0_reset",
145 "usb1_reset";
146 status = "disabled";
147 #phy-cells = <1>;
148 };
149
150 fe0: display-frontend@01e00000 { 119 fe0: display-frontend@01e00000 {
151 compatible = "allwinner,sun8i-a33-display-frontend"; 120 compatible = "allwinner,sun8i-a33-display-frontend";
152 reg = <0x01e00000 0x20000>; 121 reg = <0x01e00000 0x20000>;
@@ -276,3 +245,13 @@
276 }; 245 };
277 246
278}; 247};
248
249&usb_otg {
250 compatible = "allwinner,sun8i-a33-musb";
251};
252
253&usbphy {
254 compatible = "allwinner,sun8i-a33-usb-phy";
255 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
256 reg-names = "phy_ctrl", "pmu1";
257};