diff options
author | Heiko Stuebner <heiko@sntech.de> | 2016-03-26 17:49:57 -0400 |
---|---|---|
committer | Heiko Stuebner <heiko@sntech.de> | 2016-08-08 04:56:55 -0400 |
commit | 546a3521f251462128d877e48fb3544c74976ce4 (patch) | |
tree | d334ae734bf38fd4e65c50156c95b47415b89184 /arch/arm/boot | |
parent | 4421db1c2bb92592fc090a68deb0ad422e13a939 (diff) |
ARM: dts: rockchip: move rk3288 usbphy under the GRF node
The rk3288 usbphy is completely enclosed in the general register files
and the updated binding allows it to be a subnode of the GRF now.
So move the node appropriately.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 63 |
1 files changed, 31 insertions, 32 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cd33f0170890..e5c4a11f6bc6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi | |||
@@ -832,6 +832,37 @@ | |||
832 | compatible = "rockchip,rk3288-io-voltage-domain"; | 832 | compatible = "rockchip,rk3288-io-voltage-domain"; |
833 | status = "disabled"; | 833 | status = "disabled"; |
834 | }; | 834 | }; |
835 | |||
836 | usbphy: usbphy { | ||
837 | compatible = "rockchip,rk3288-usb-phy"; | ||
838 | #address-cells = <1>; | ||
839 | #size-cells = <0>; | ||
840 | status = "disabled"; | ||
841 | |||
842 | usbphy0: usb-phy@320 { | ||
843 | #phy-cells = <0>; | ||
844 | reg = <0x320>; | ||
845 | clocks = <&cru SCLK_OTGPHY0>; | ||
846 | clock-names = "phyclk"; | ||
847 | #clock-cells = <0>; | ||
848 | }; | ||
849 | |||
850 | usbphy1: usb-phy@334 { | ||
851 | #phy-cells = <0>; | ||
852 | reg = <0x334>; | ||
853 | clocks = <&cru SCLK_OTGPHY1>; | ||
854 | clock-names = "phyclk"; | ||
855 | #clock-cells = <0>; | ||
856 | }; | ||
857 | |||
858 | usbphy2: usb-phy@348 { | ||
859 | #phy-cells = <0>; | ||
860 | reg = <0x348>; | ||
861 | clocks = <&cru SCLK_OTGPHY2>; | ||
862 | clock-names = "phyclk"; | ||
863 | #clock-cells = <0>; | ||
864 | }; | ||
865 | }; | ||
835 | }; | 866 | }; |
836 | 867 | ||
837 | wdt: watchdog@ff800000 { | 868 | wdt: watchdog@ff800000 { |
@@ -1085,38 +1116,6 @@ | |||
1085 | }; | 1116 | }; |
1086 | }; | 1117 | }; |
1087 | 1118 | ||
1088 | usbphy: phy { | ||
1089 | compatible = "rockchip,rk3288-usb-phy"; | ||
1090 | rockchip,grf = <&grf>; | ||
1091 | #address-cells = <1>; | ||
1092 | #size-cells = <0>; | ||
1093 | status = "disabled"; | ||
1094 | |||
1095 | usbphy0: usb-phy@320 { | ||
1096 | #phy-cells = <0>; | ||
1097 | reg = <0x320>; | ||
1098 | clocks = <&cru SCLK_OTGPHY0>; | ||
1099 | clock-names = "phyclk"; | ||
1100 | #clock-cells = <0>; | ||
1101 | }; | ||
1102 | |||
1103 | usbphy1: usb-phy@334 { | ||
1104 | #phy-cells = <0>; | ||
1105 | reg = <0x334>; | ||
1106 | clocks = <&cru SCLK_OTGPHY1>; | ||
1107 | clock-names = "phyclk"; | ||
1108 | #clock-cells = <0>; | ||
1109 | }; | ||
1110 | |||
1111 | usbphy2: usb-phy@348 { | ||
1112 | #phy-cells = <0>; | ||
1113 | reg = <0x348>; | ||
1114 | clocks = <&cru SCLK_OTGPHY2>; | ||
1115 | clock-names = "phyclk"; | ||
1116 | #clock-cells = <0>; | ||
1117 | }; | ||
1118 | }; | ||
1119 | |||
1120 | pinctrl: pinctrl { | 1119 | pinctrl: pinctrl { |
1121 | compatible = "rockchip,rk3288-pinctrl"; | 1120 | compatible = "rockchip,rk3288-pinctrl"; |
1122 | rockchip,grf = <&grf>; | 1121 | rockchip,grf = <&grf>; |