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authorTim Harvey <tharvey@gateworks.com>2016-06-29 09:31:03 -0400
committerShawn Guo <shawnguo@kernel.org>2016-08-08 03:23:34 -0400
commit51a012b76267f2de8a0209ffdf91f67f3fb3ff42 (patch)
treee698d6fb763aab6f447d020733213cf90aaf1d02 /arch/arm/boot
parent29b4817d4018df78086157ea3a55c1d9424a7cfc (diff)
ARM: dts: imx: ventana: Add ext watchdog reset
bc677ff42e81bbf78308a7b66cf7b63b0f5c26b0 adds a device-tree property to specify that an external watchdog reset is used to reset other portions of the board and not just the IMX6 SoC. This adds the property to the proper watchdog as well as the pinmux for the Gateworks Ventana boards that use this external watchdog reset to reset the PMIC which will reset all the PMIC power rails and not just a chip-level IMX6 reset. This helps to work around various system issues that can cause a hang when coming out of reset. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi17
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw551x.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw552x.dtsi12
6 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 9d7ab6cdc9a6..1340e2760406 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -228,6 +228,12 @@
228 status = "okay"; 228 status = "okay";
229}; 229};
230 230
231&wdog1 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_wdog>;
234 fsl,ext-reset-output;
235};
236
231&iomuxc { 237&iomuxc {
232 imx6qdl-gw51xx { 238 imx6qdl-gw51xx {
233 pinctrl_enet: enetgrp { 239 pinctrl_enet: enetgrp {
@@ -364,5 +370,11 @@
364 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 370 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
365 >; 371 >;
366 }; 372 };
373
374 pinctrl_wdog: wdoggrp {
375 fsl,pins = <
376 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
377 >;
378 };
367 }; 379 };
368}; 380};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 7191b84770b9..8bf1020affa0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -353,6 +353,12 @@
353 status = "okay"; 353 status = "okay";
354}; 354};
355 355
356&wdog1 {
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_wdog>;
359 fsl,ext-reset-output;
360};
361
356&iomuxc { 362&iomuxc {
357 imx6qdl-gw52xx { 363 imx6qdl-gw52xx {
358 pinctrl_audmux: audmuxgrp { 364 pinctrl_audmux: audmuxgrp {
@@ -549,5 +555,11 @@
549 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 555 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
550 >; 556 >;
551 }; 557 };
558
559 pinctrl_wdog: wdoggrp {
560 fsl,pins = <
561 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
562 >;
563 };
552 }; 564 };
553}; 565};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 40d06b09deba..a3dd0c41b995 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -351,6 +351,12 @@
351 status = "okay"; 351 status = "okay";
352}; 352};
353 353
354&wdog1 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_wdog>;
357 fsl,ext-reset-output;
358};
359
354&iomuxc { 360&iomuxc {
355 imx6qdl-gw53xx { 361 imx6qdl-gw53xx {
356 pinctrl_audmux: audmuxgrp { 362 pinctrl_audmux: audmuxgrp {
@@ -539,5 +545,11 @@
539 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 545 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
540 >; 546 >;
541 }; 547 };
548
549 pinctrl_wdog: wdoggrp {
550 fsl,pins = <
551 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
552 >;
553 };
542 }; 554 };
543}; 555};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index d6dbe2a88ee6..5a8dbabbd20f 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -453,6 +453,17 @@
453 status = "okay"; 453 status = "okay";
454}; 454};
455 455
456&wdog1 {
457 status = "disabled";
458};
459
460&wdog2 {
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_wdog>;
463 fsl,ext-reset-output;
464 status = "okay";
465};
466
456&iomuxc { 467&iomuxc {
457 imx6qdl-gw54xx { 468 imx6qdl-gw54xx {
458 pinctrl_audmux: audmuxgrp { 469 pinctrl_audmux: audmuxgrp {
@@ -654,5 +665,11 @@
654 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 665 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
655 >; 666 >;
656 }; 667 };
668
669 pinctrl_wdog: wdoggrp {
670 fsl,pins = <
671 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
672 >;
673 };
657 }; 674 };
658}; 675};
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 118bea524dab..4b9fef834822 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -239,6 +239,12 @@
239 status = "okay"; 239 status = "okay";
240}; 240};
241 241
242&wdog1 {
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_wdog>;
245 fsl,ext-reset-output;
246};
247
242&iomuxc { 248&iomuxc {
243 imx6qdl-gw51xx { 249 imx6qdl-gw51xx {
244 pinctrl_flexcan1: flexcan1grp { 250 pinctrl_flexcan1: flexcan1grp {
@@ -333,5 +339,11 @@
333 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 339 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
334 >; 340 >;
335 }; 341 };
342
343 pinctrl_wdog: wdoggrp {
344 fsl,pins = <
345 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
346 >;
347 };
336 }; 348 };
337}; 349};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index f27f184558fb..805e23674a94 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -197,6 +197,12 @@
197 status = "okay"; 197 status = "okay";
198}; 198};
199 199
200&wdog1 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_wdog>;
203 fsl,ext-reset-output;
204};
205
200&iomuxc { 206&iomuxc {
201 imx6qdl-gw552x { 207 imx6qdl-gw552x {
202 pinctrl_gpio_leds: gpioledsgrp { 208 pinctrl_gpio_leds: gpioledsgrp {
@@ -286,5 +292,11 @@
286 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 292 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
287 >; 293 >;
288 }; 294 };
295
296 pinctrl_wdog: wdoggrp {
297 fsl,pins = <
298 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
299 >;
300 };
289 }; 301 };
290}; 302};