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authorMaxime Ripard <maxime.ripard@free-electrons.com>2016-08-31 08:58:20 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-09-10 05:50:41 -0400
commit2c89ce4f4b19561218c1acb97172bd7ba1a6ddc2 (patch)
treed4d669ae82d36614ca762f6e6b0c6756193c9460 /arch/arm/boot
parent78a9f0dbcd6015cdd1114dc7d78554fd5bb28010 (diff)
ARM: sun8i: Convert the A23 and A33 to the CCU
Now that we have support for the CCU driver in sunxi-ng, convert the A23 and A33 DTs to that driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi257
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi51
-rw-r--r--arch/arm/boot/dts/sun8i-a33.dtsi73
3 files changed, 75 insertions, 306 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 6d6509c71009..7246663bacdd 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -46,7 +46,9 @@
46 46
47#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h>
48 48
49#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
49#include <dt-bindings/pinctrl/sun4i-a10.h> 50#include <dt-bindings/pinctrl/sun4i-a10.h>
51#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
50 52
51/ { 53/ {
52 interrupt-parent = <&gic>; 54 interrupt-parent = <&gic>;
@@ -60,7 +62,9 @@
60 compatible = "allwinner,simple-framebuffer", 62 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer"; 63 "simple-framebuffer";
62 allwinner,pipeline = "de_be0-lcd0"; 64 allwinner,pipeline = "de_be0-lcd0";
63 clocks = <&pll6 0>; 65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
64 status = "disabled"; 68 status = "disabled";
65 }; 69 };
66 }; 70 };
@@ -111,151 +115,6 @@
111 clock-frequency = <32768>; 115 clock-frequency = <32768>;
112 clock-output-names = "osc32k"; 116 clock-output-names = "osc32k";
113 }; 117 };
114
115 pll1: clk@01c20000 {
116 #clock-cells = <0>;
117 compatible = "allwinner,sun8i-a23-pll1-clk";
118 reg = <0x01c20000 0x4>;
119 clocks = <&osc24M>;
120 clock-output-names = "pll1";
121 };
122
123 /* dummy clock until actually implemented */
124 pll5: pll5_clk {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 clock-output-names = "pll5";
129 };
130
131 pll6: clk@01c20028 {
132 #clock-cells = <1>;
133 compatible = "allwinner,sun6i-a31-pll6-clk";
134 reg = <0x01c20028 0x4>;
135 clocks = <&osc24M>;
136 clock-output-names = "pll6", "pll6x2";
137 };
138
139 cpu: cpu_clk@01c20050 {
140 #clock-cells = <0>;
141 compatible = "allwinner,sun4i-a10-cpu-clk";
142 reg = <0x01c20050 0x4>;
143
144 /*
145 * PLL1 is listed twice here.
146 * While it looks suspicious, it's actually documented
147 * that way both in the datasheet and in the code from
148 * Allwinner.
149 */
150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
151 clock-output-names = "cpu";
152 };
153
154 axi: axi_clk@01c20050 {
155 #clock-cells = <0>;
156 compatible = "allwinner,sun8i-a23-axi-clk";
157 reg = <0x01c20050 0x4>;
158 clocks = <&cpu>;
159 clock-output-names = "axi";
160 };
161
162 ahb1: ahb1_clk@01c20054 {
163 #clock-cells = <0>;
164 compatible = "allwinner,sun6i-a31-ahb1-clk";
165 reg = <0x01c20054 0x4>;
166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
167 clock-output-names = "ahb1";
168 };
169
170 apb1: apb1_clk@01c20054 {
171 #clock-cells = <0>;
172 compatible = "allwinner,sun4i-a10-apb0-clk";
173 reg = <0x01c20054 0x4>;
174 clocks = <&ahb1>;
175 clock-output-names = "apb1";
176 };
177
178 apb1_gates: clk@01c20068 {
179 #clock-cells = <1>;
180 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
181 reg = <0x01c20068 0x4>;
182 clocks = <&apb1>;
183 clock-indices = <0>, <5>,
184 <12>, <13>;
185 clock-output-names = "apb1_codec", "apb1_pio",
186 "apb1_daudio0", "apb1_daudio1";
187 };
188
189 apb2: clk@01c20058 {
190 #clock-cells = <0>;
191 compatible = "allwinner,sun4i-a10-apb1-clk";
192 reg = <0x01c20058 0x4>;
193 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
194 clock-output-names = "apb2";
195 };
196
197 apb2_gates: clk@01c2006c {
198 #clock-cells = <1>;
199 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
200 reg = <0x01c2006c 0x4>;
201 clocks = <&apb2>;
202 clock-indices = <0>, <1>,
203 <2>, <16>,
204 <17>, <18>,
205 <19>, <20>;
206 clock-output-names = "apb2_i2c0", "apb2_i2c1",
207 "apb2_i2c2", "apb2_uart0",
208 "apb2_uart1", "apb2_uart2",
209 "apb2_uart3", "apb2_uart4";
210 };
211
212 mmc0_clk: clk@01c20088 {
213 #clock-cells = <1>;
214 compatible = "allwinner,sun4i-a10-mmc-clk";
215 reg = <0x01c20088 0x4>;
216 clocks = <&osc24M>, <&pll6 0>;
217 clock-output-names = "mmc0",
218 "mmc0_output",
219 "mmc0_sample";
220 };
221
222 mmc1_clk: clk@01c2008c {
223 #clock-cells = <1>;
224 compatible = "allwinner,sun4i-a10-mmc-clk";
225 reg = <0x01c2008c 0x4>;
226 clocks = <&osc24M>, <&pll6 0>;
227 clock-output-names = "mmc1",
228 "mmc1_output",
229 "mmc1_sample";
230 };
231
232 mmc2_clk: clk@01c20090 {
233 #clock-cells = <1>;
234 compatible = "allwinner,sun4i-a10-mmc-clk";
235 reg = <0x01c20090 0x4>;
236 clocks = <&osc24M>, <&pll6 0>;
237 clock-output-names = "mmc2",
238 "mmc2_output",
239 "mmc2_sample";
240 };
241
242 nand_clk: clk@01c20080 {
243 #clock-cells = <0>;
244 compatible = "allwinner,sun4i-a10-mod0-clk";
245 reg = <0x01c20080 0x4>;
246 clocks = <&osc24M>, <&pll6 1>;
247 clock-output-names = "nand";
248 };
249
250 usb_clk: clk@01c200cc {
251 #clock-cells = <1>;
252 #reset-cells = <1>;
253 compatible = "allwinner,sun8i-a23-usb-clk";
254 reg = <0x01c200cc 0x4>;
255 clocks = <&osc24M>;
256 clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
257 "usb_hsic_12M", "usb_ohci0";
258 };
259 }; 118 };
260 119
261 soc@01c00000 { 120 soc@01c00000 {
@@ -268,23 +127,23 @@
268 compatible = "allwinner,sun8i-a23-dma"; 127 compatible = "allwinner,sun8i-a23-dma";
269 reg = <0x01c02000 0x1000>; 128 reg = <0x01c02000 0x1000>;
270 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 129 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&ahb1_gates 6>; 130 clocks = <&ccu CLK_BUS_DMA>;
272 resets = <&ahb1_rst 6>; 131 resets = <&ccu RST_BUS_DMA>;
273 #dma-cells = <1>; 132 #dma-cells = <1>;
274 }; 133 };
275 134
276 mmc0: mmc@01c0f000 { 135 mmc0: mmc@01c0f000 {
277 compatible = "allwinner,sun5i-a13-mmc"; 136 compatible = "allwinner,sun5i-a13-mmc";
278 reg = <0x01c0f000 0x1000>; 137 reg = <0x01c0f000 0x1000>;
279 clocks = <&ahb1_gates 8>, 138 clocks = <&ccu CLK_BUS_MMC0>,
280 <&mmc0_clk 0>, 139 <&ccu CLK_MMC0>,
281 <&mmc0_clk 1>, 140 <&ccu CLK_MMC0_OUTPUT>,
282 <&mmc0_clk 2>; 141 <&ccu CLK_MMC0_SAMPLE>;
283 clock-names = "ahb", 142 clock-names = "ahb",
284 "mmc", 143 "mmc",
285 "output", 144 "output",
286 "sample"; 145 "sample";
287 resets = <&ahb1_rst 8>; 146 resets = <&ccu RST_BUS_MMC0>;
288 reset-names = "ahb"; 147 reset-names = "ahb";
289 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
290 status = "disabled"; 149 status = "disabled";
@@ -295,15 +154,15 @@
295 mmc1: mmc@01c10000 { 154 mmc1: mmc@01c10000 {
296 compatible = "allwinner,sun5i-a13-mmc"; 155 compatible = "allwinner,sun5i-a13-mmc";
297 reg = <0x01c10000 0x1000>; 156 reg = <0x01c10000 0x1000>;
298 clocks = <&ahb1_gates 9>, 157 clocks = <&ccu CLK_BUS_MMC1>,
299 <&mmc1_clk 0>, 158 <&ccu CLK_MMC1>,
300 <&mmc1_clk 1>, 159 <&ccu CLK_MMC1_OUTPUT>,
301 <&mmc1_clk 2>; 160 <&ccu CLK_MMC1_SAMPLE>;
302 clock-names = "ahb", 161 clock-names = "ahb",
303 "mmc", 162 "mmc",
304 "output", 163 "output",
305 "sample"; 164 "sample";
306 resets = <&ahb1_rst 9>; 165 resets = <&ccu RST_BUS_MMC1>;
307 reset-names = "ahb"; 166 reset-names = "ahb";
308 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 167 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
309 status = "disabled"; 168 status = "disabled";
@@ -314,15 +173,15 @@
314 mmc2: mmc@01c11000 { 173 mmc2: mmc@01c11000 {
315 compatible = "allwinner,sun5i-a13-mmc"; 174 compatible = "allwinner,sun5i-a13-mmc";
316 reg = <0x01c11000 0x1000>; 175 reg = <0x01c11000 0x1000>;
317 clocks = <&ahb1_gates 10>, 176 clocks = <&ccu CLK_BUS_MMC2>,
318 <&mmc2_clk 0>, 177 <&ccu CLK_MMC2>,
319 <&mmc2_clk 1>, 178 <&ccu CLK_MMC2_OUTPUT>,
320 <&mmc2_clk 2>; 179 <&ccu CLK_MMC2_SAMPLE>;
321 clock-names = "ahb", 180 clock-names = "ahb",
322 "mmc", 181 "mmc",
323 "output", 182 "output",
324 "sample"; 183 "sample";
325 resets = <&ahb1_rst 10>; 184 resets = <&ccu RST_BUS_MMC2>;
326 reset-names = "ahb"; 185 reset-names = "ahb";
327 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 186 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
328 status = "disabled"; 187 status = "disabled";
@@ -334,9 +193,9 @@
334 compatible = "allwinner,sun4i-a10-nand"; 193 compatible = "allwinner,sun4i-a10-nand";
335 reg = <0x01c03000 0x1000>; 194 reg = <0x01c03000 0x1000>;
336 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&ahb1_gates 13>, <&nand_clk>; 196 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
338 clock-names = "ahb", "mod"; 197 clock-names = "ahb", "mod";
339 resets = <&ahb1_rst 13>; 198 resets = <&ccu RST_BUS_NAND>;
340 reset-names = "ahb"; 199 reset-names = "ahb";
341 status = "disabled"; 200 status = "disabled";
342 #address-cells = <1>; 201 #address-cells = <1>;
@@ -347,8 +206,8 @@
347 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 206 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
348 reg = <0x01c1a000 0x100>; 207 reg = <0x01c1a000 0x100>;
349 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 208 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&ahb1_gates 26>; 209 clocks = <&ccu CLK_BUS_EHCI>;
351 resets = <&ahb1_rst 26>; 210 resets = <&ccu RST_BUS_EHCI>;
352 phys = <&usbphy 1>; 211 phys = <&usbphy 1>;
353 phy-names = "usb"; 212 phy-names = "usb";
354 status = "disabled"; 213 status = "disabled";
@@ -358,18 +217,26 @@
358 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; 217 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
359 reg = <0x01c1a400 0x100>; 218 reg = <0x01c1a400 0x100>;
360 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 220 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
362 resets = <&ahb1_rst 29>; 221 resets = <&ccu RST_BUS_OHCI>;
363 phys = <&usbphy 1>; 222 phys = <&usbphy 1>;
364 phy-names = "usb"; 223 phy-names = "usb";
365 status = "disabled"; 224 status = "disabled";
366 }; 225 };
367 226
227 ccu: clock@01c20000 {
228 reg = <0x01c20000 0x400>;
229 clocks = <&osc24M>, <&osc32k>;
230 clock-names = "hosc", "losc";
231 #clock-cells = <1>;
232 #reset-cells = <1>;
233 };
234
368 pio: pinctrl@01c20800 { 235 pio: pinctrl@01c20800 {
369 /* compatible gets set in SoC specific dtsi file */ 236 /* compatible gets set in SoC specific dtsi file */
370 reg = <0x01c20800 0x400>; 237 reg = <0x01c20800 0x400>;
371 /* interrupts get set in SoC specific dtsi file */ 238 /* interrupts get set in SoC specific dtsi file */
372 clocks = <&apb1_gates 5>; 239 clocks = <&ccu CLK_BUS_PIO>;
373 gpio-controller; 240 gpio-controller;
374 interrupt-controller; 241 interrupt-controller;
375 #interrupt-cells = <3>; 242 #interrupt-cells = <3>;
@@ -437,24 +304,6 @@
437 }; 304 };
438 }; 305 };
439 306
440 ahb1_rst: reset@01c202c0 {
441 #reset-cells = <1>;
442 compatible = "allwinner,sun6i-a31-clock-reset";
443 reg = <0x01c202c0 0xc>;
444 };
445
446 apb1_rst: reset@01c202d0 {
447 #reset-cells = <1>;
448 compatible = "allwinner,sun6i-a31-clock-reset";
449 reg = <0x01c202d0 0x4>;
450 };
451
452 apb2_rst: reset@01c202d8 {
453 #reset-cells = <1>;
454 compatible = "allwinner,sun6i-a31-clock-reset";
455 reg = <0x01c202d8 0x4>;
456 };
457
458 timer@01c20c00 { 307 timer@01c20c00 {
459 compatible = "allwinner,sun4i-a10-timer"; 308 compatible = "allwinner,sun4i-a10-timer";
460 reg = <0x01c20c00 0xa0>; 309 reg = <0x01c20c00 0xa0>;
@@ -490,8 +339,8 @@
490 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 339 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
491 reg-shift = <2>; 340 reg-shift = <2>;
492 reg-io-width = <4>; 341 reg-io-width = <4>;
493 clocks = <&apb2_gates 16>; 342 clocks = <&ccu CLK_BUS_UART0>;
494 resets = <&apb2_rst 16>; 343 resets = <&ccu RST_BUS_UART0>;
495 dmas = <&dma 6>, <&dma 6>; 344 dmas = <&dma 6>, <&dma 6>;
496 dma-names = "rx", "tx"; 345 dma-names = "rx", "tx";
497 status = "disabled"; 346 status = "disabled";
@@ -503,8 +352,8 @@
503 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
504 reg-shift = <2>; 353 reg-shift = <2>;
505 reg-io-width = <4>; 354 reg-io-width = <4>;
506 clocks = <&apb2_gates 17>; 355 clocks = <&ccu CLK_BUS_UART1>;
507 resets = <&apb2_rst 17>; 356 resets = <&ccu RST_BUS_UART1>;
508 dmas = <&dma 7>, <&dma 7>; 357 dmas = <&dma 7>, <&dma 7>;
509 dma-names = "rx", "tx"; 358 dma-names = "rx", "tx";
510 status = "disabled"; 359 status = "disabled";
@@ -516,8 +365,8 @@
516 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 365 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
517 reg-shift = <2>; 366 reg-shift = <2>;
518 reg-io-width = <4>; 367 reg-io-width = <4>;
519 clocks = <&apb2_gates 18>; 368 clocks = <&ccu CLK_BUS_UART2>;
520 resets = <&apb2_rst 18>; 369 resets = <&ccu RST_BUS_UART2>;
521 dmas = <&dma 8>, <&dma 8>; 370 dmas = <&dma 8>, <&dma 8>;
522 dma-names = "rx", "tx"; 371 dma-names = "rx", "tx";
523 status = "disabled"; 372 status = "disabled";
@@ -529,8 +378,8 @@
529 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 378 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
530 reg-shift = <2>; 379 reg-shift = <2>;
531 reg-io-width = <4>; 380 reg-io-width = <4>;
532 clocks = <&apb2_gates 19>; 381 clocks = <&ccu CLK_BUS_UART3>;
533 resets = <&apb2_rst 19>; 382 resets = <&ccu RST_BUS_UART3>;
534 dmas = <&dma 9>, <&dma 9>; 383 dmas = <&dma 9>, <&dma 9>;
535 dma-names = "rx", "tx"; 384 dma-names = "rx", "tx";
536 status = "disabled"; 385 status = "disabled";
@@ -542,8 +391,8 @@
542 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 391 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
543 reg-shift = <2>; 392 reg-shift = <2>;
544 reg-io-width = <4>; 393 reg-io-width = <4>;
545 clocks = <&apb2_gates 20>; 394 clocks = <&ccu CLK_BUS_UART4>;
546 resets = <&apb2_rst 20>; 395 resets = <&ccu RST_BUS_UART4>;
547 dmas = <&dma 10>, <&dma 10>; 396 dmas = <&dma 10>, <&dma 10>;
548 dma-names = "rx", "tx"; 397 dma-names = "rx", "tx";
549 status = "disabled"; 398 status = "disabled";
@@ -553,8 +402,8 @@
553 compatible = "allwinner,sun6i-a31-i2c"; 402 compatible = "allwinner,sun6i-a31-i2c";
554 reg = <0x01c2ac00 0x400>; 403 reg = <0x01c2ac00 0x400>;
555 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 404 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&apb2_gates 0>; 405 clocks = <&ccu CLK_BUS_I2C0>;
557 resets = <&apb2_rst 0>; 406 resets = <&ccu RST_BUS_I2C0>;
558 status = "disabled"; 407 status = "disabled";
559 #address-cells = <1>; 408 #address-cells = <1>;
560 #size-cells = <0>; 409 #size-cells = <0>;
@@ -564,8 +413,8 @@
564 compatible = "allwinner,sun6i-a31-i2c"; 413 compatible = "allwinner,sun6i-a31-i2c";
565 reg = <0x01c2b000 0x400>; 414 reg = <0x01c2b000 0x400>;
566 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 415 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&apb2_gates 1>; 416 clocks = <&ccu CLK_BUS_I2C1>;
568 resets = <&apb2_rst 1>; 417 resets = <&ccu RST_BUS_I2C1>;
569 status = "disabled"; 418 status = "disabled";
570 #address-cells = <1>; 419 #address-cells = <1>;
571 #size-cells = <0>; 420 #size-cells = <0>;
@@ -575,8 +424,8 @@
575 compatible = "allwinner,sun6i-a31-i2c"; 424 compatible = "allwinner,sun6i-a31-i2c";
576 reg = <0x01c2b400 0x400>; 425 reg = <0x01c2b400 0x400>;
577 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 426 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&apb2_gates 2>; 427 clocks = <&ccu CLK_BUS_I2C2>;
579 resets = <&apb2_rst 2>; 428 resets = <&ccu RST_BUS_I2C2>;
580 status = "disabled"; 429 status = "disabled";
581 #address-cells = <1>; 430 #address-cells = <1>;
582 #size-cells = <0>; 431 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 92e6616979ea..a915feb3a494 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -49,47 +49,12 @@
49 reg = <0x40000000 0x40000000>; 49 reg = <0x40000000 0x40000000>;
50 }; 50 };
51 51
52 clocks {
53 ahb1_gates: clk@01c20060 {
54 #clock-cells = <1>;
55 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
56 reg = <0x01c20060 0x8>;
57 clocks = <&ahb1>;
58 clock-indices = <1>, <6>,
59 <8>, <9>, <10>,
60 <13>, <14>,
61 <19>, <20>,
62 <21>, <24>, <26>,
63 <29>, <32>, <36>,
64 <40>, <44>, <46>,
65 <52>, <53>,
66 <54>, <57>;
67 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
68 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
69 "ahb1_nand", "ahb1_sdram",
70 "ahb1_hstimer", "ahb1_spi0",
71 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
72 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
73 "ahb1_csi", "ahb1_be", "ahb1_fe",
74 "ahb1_gpu", "ahb1_msgbox",
75 "ahb1_spinlock", "ahb1_drc";
76 };
77
78 mbus_clk: clk@01c2015c {
79 #clock-cells = <0>;
80 compatible = "allwinner,sun8i-a23-mbus-clk";
81 reg = <0x01c2015c 0x4>;
82 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
83 clock-output-names = "mbus";
84 };
85 };
86
87 soc@01c00000 { 52 soc@01c00000 {
88 usb_otg: usb@01c19000 { 53 usb_otg: usb@01c19000 {
89 compatible = "allwinner,sun6i-a31-musb"; 54 compatible = "allwinner,sun6i-a31-musb";
90 reg = <0x01c19000 0x0400>; 55 reg = <0x01c19000 0x0400>;
91 clocks = <&ahb1_gates 24>; 56 clocks = <&ccu CLK_BUS_OTG>;
92 resets = <&ahb1_rst 24>; 57 resets = <&ccu RST_BUS_OTG>;
93 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 58 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-names = "mc"; 59 interrupt-names = "mc";
95 phys = <&usbphy 0>; 60 phys = <&usbphy 0>;
@@ -104,12 +69,12 @@
104 <0x01c1a800 0x4>; 69 <0x01c1a800 0x4>;
105 reg-names = "phy_ctrl", 70 reg-names = "phy_ctrl",
106 "pmu1"; 71 "pmu1";
107 clocks = <&usb_clk 8>, 72 clocks = <&ccu CLK_USB_PHY0>,
108 <&usb_clk 9>; 73 <&ccu CLK_USB_PHY1>;
109 clock-names = "usb0_phy", 74 clock-names = "usb0_phy",
110 "usb1_phy"; 75 "usb1_phy";
111 resets = <&usb_clk 0>, 76 resets = <&ccu RST_USB_PHY0>,
112 <&usb_clk 1>; 77 <&ccu RST_USB_PHY1>;
113 reset-names = "usb0_reset", 78 reset-names = "usb0_reset",
114 "usb1_reset"; 79 "usb1_reset";
115 status = "disabled"; 80 status = "disabled";
@@ -118,6 +83,10 @@
118 }; 83 };
119}; 84};
120 85
86&ccu {
87 compatible = "allwinner,sun8i-a23-ccu";
88};
89
121&pio { 90&pio {
122 compatible = "allwinner,sun8i-a23-pinctrl"; 91 compatible = "allwinner,sun8i-a23-pinctrl";
123 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 92 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 001d8402ca18..f3d91d2c96ef 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -63,75 +63,22 @@
63 reg = <0x40000000 0x80000000>; 63 reg = <0x40000000 0x80000000>;
64 }; 64 };
65 65
66 clocks {
67 /* Dummy clock for pll11 (DDR1) until actually implemented */
68 pll11: pll11_clk {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <0>;
72 clock-output-names = "pll11";
73 };
74
75 ahb1_gates: clk@01c20060 {
76 #clock-cells = <1>;
77 compatible = "allwinner,sun8i-a33-ahb1-gates-clk";
78 reg = <0x01c20060 0x8>;
79 clocks = <&ahb1>;
80 clock-indices = <1>, <5>,
81 <6>, <8>, <9>,
82 <10>, <13>, <14>,
83 <19>, <20>,
84 <21>, <24>, <26>,
85 <29>, <32>, <36>,
86 <40>, <44>, <46>,
87 <52>, <53>,
88 <54>, <57>,
89 <58>;
90 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
91 "ahb1_dma","ahb1_mmc0", "ahb1_mmc1",
92 "ahb1_mmc2", "ahb1_nand", "ahb1_sdram",
93 "ahb1_hstimer", "ahb1_spi0",
94 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
95 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
96 "ahb1_csi", "ahb1_be", "ahb1_fe",
97 "ahb1_gpu", "ahb1_msgbox",
98 "ahb1_spinlock", "ahb1_drc",
99 "ahb1_sat";
100 };
101
102 ss_clk: clk@01c2009c {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-a10-mod0-clk";
105 reg = <0x01c2009c 0x4>;
106 clocks = <&osc24M>, <&pll6 0>;
107 clock-output-names = "ss";
108 };
109
110 mbus_clk: clk@01c2015c {
111 #clock-cells = <0>;
112 compatible = "allwinner,sun8i-a23-mbus-clk";
113 reg = <0x01c2015c 0x4>;
114 clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;
115 clock-output-names = "mbus";
116 };
117 };
118
119 soc@01c00000 { 66 soc@01c00000 {
120 crypto: crypto-engine@01c15000 { 67 crypto: crypto-engine@01c15000 {
121 compatible = "allwinner,sun4i-a10-crypto"; 68 compatible = "allwinner,sun4i-a10-crypto";
122 reg = <0x01c15000 0x1000>; 69 reg = <0x01c15000 0x1000>;
123 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 70 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&ahb1_gates 5>, <&ss_clk>; 71 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
125 clock-names = "ahb", "mod"; 72 clock-names = "ahb", "mod";
126 resets = <&ahb1_rst 5>; 73 resets = <&ccu RST_BUS_SS>;
127 reset-names = "ahb"; 74 reset-names = "ahb";
128 }; 75 };
129 76
130 usb_otg: usb@01c19000 { 77 usb_otg: usb@01c19000 {
131 compatible = "allwinner,sun8i-a33-musb"; 78 compatible = "allwinner,sun8i-a33-musb";
132 reg = <0x01c19000 0x0400>; 79 reg = <0x01c19000 0x0400>;
133 clocks = <&ahb1_gates 24>; 80 clocks = <&ccu CLK_BUS_OTG>;
134 resets = <&ahb1_rst 24>; 81 resets = <&ccu RST_BUS_OTG>;
135 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 82 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
136 interrupt-names = "mc"; 83 interrupt-names = "mc";
137 phys = <&usbphy 0>; 84 phys = <&usbphy 0>;
@@ -146,12 +93,12 @@
146 <0x01c1a800 0x4>; 93 <0x01c1a800 0x4>;
147 reg-names = "phy_ctrl", 94 reg-names = "phy_ctrl",
148 "pmu1"; 95 "pmu1";
149 clocks = <&usb_clk 8>, 96 clocks = <&ccu CLK_USB_PHY0>,
150 <&usb_clk 9>; 97 <&ccu CLK_USB_PHY1>;
151 clock-names = "usb0_phy", 98 clock-names = "usb0_phy",
152 "usb1_phy"; 99 "usb1_phy";
153 resets = <&usb_clk 0>, 100 resets = <&ccu RST_USB_PHY0>,
154 <&usb_clk 1>; 101 <&ccu RST_USB_PHY1>;
155 reset-names = "usb0_reset", 102 reset-names = "usb0_reset",
156 "usb1_reset"; 103 "usb1_reset";
157 status = "disabled"; 104 status = "disabled";
@@ -160,6 +107,10 @@
160 }; 107 };
161}; 108};
162 109
110&ccu {
111 compatible = "allwinner,sun8i-a33-ccu";
112};
113
163&pio { 114&pio {
164 compatible = "allwinner,sun8i-a33-pinctrl"; 115 compatible = "allwinner,sun8i-a33-pinctrl";
165 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 116 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 17:28:49 -0400