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authorDave Gerlach <d-gerlach@ti.com>2016-09-14 19:26:53 -0400
committerTony Lindgren <tony@atomide.com>2016-09-14 19:26:53 -0400
commit0f416d1317dd4ef9d758ddc3e13cde23aa909c2d (patch)
tree993f298ce1484264b4248b6878a10894e97d0361 /arch/arm/boot
parente3659351da0976f47b2fa1c225ddaf411b9dbb51 (diff)
Revert "ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver"
This reverts commit 4317be1162108bcdf50dc53dfb48eac94dcff25c. The original commit updated the cpufreq operating points tables for am33xx but was merged before the driver making use of the node was merged, which breaks the existing cpufreq implementation on the system, so revert the patch until the ti-cpufreq driver is merged. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi88
1 files changed, 13 insertions, 75 deletions
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 98748c61ed99..9e214bfd32d2 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -45,9 +45,19 @@
45 device_type = "cpu"; 45 device_type = "cpu";
46 reg = <0>; 46 reg = <0>;
47 47
48 operating-points-v2 = <&cpu0_opp_table>; 48 /*
49 ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>; 49 * To consider voltage drop between PMIC and SoC,
50 ti,syscon-rev = <&scm_conf 0x600>; 50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
51 61
52 clocks = <&dpll_mpu_ck>; 62 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu"; 63 clock-names = "cpu";
@@ -56,78 +66,6 @@
56 }; 66 };
57 }; 67 };
58 68
59 cpu0_opp_table: opp_table0 {
60 compatible = "operating-points-v2";
61
62 /*
63 * The three following nodes are marked with opp-suspend
64 * because the can not be enabled simultaneously on a
65 * single SoC.
66 */
67 opp50@300000000 {
68 opp-hz = /bits/ 64 <300000000>;
69 opp-microvolt = <950000 931000 969000>;
70 opp-supported-hw = <0x06 0x0010>;
71 opp-suspend;
72 };
73
74 opp100@275000000 {
75 opp-hz = /bits/ 64 <275000000>;
76 opp-microvolt = <1100000 1078000 1122000>;
77 opp-supported-hw = <0x01 0x00FF>;
78 opp-suspend;
79 };
80
81 opp100@300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 opp-microvolt = <1100000 1078000 1122000>;
84 opp-supported-hw = <0x06 0x0020>;
85 opp-suspend;
86 };
87
88 opp100@500000000 {
89 opp-hz = /bits/ 64 <500000000>;
90 opp-microvolt = <1100000 1078000 1122000>;
91 opp-supported-hw = <0x01 0xFFFF>;
92 };
93
94 opp100@600000000 {
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <1100000 1078000 1122000>;
97 opp-supported-hw = <0x06 0x0040>;
98 };
99
100 opp120@600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <1200000 1176000 1224000>;
103 opp-supported-hw = <0x01 0xFFFF>;
104 };
105
106 opp120@720000000 {
107 opp-hz = /bits/ 64 <720000000>;
108 opp-microvolt = <1200000 1176000 1224000>;
109 opp-supported-hw = <0x06 0x0080>;
110 };
111
112 oppturbo@720000000 {
113 opp-hz = /bits/ 64 <720000000>;
114 opp-microvolt = <1260000 1234800 1285200>;
115 opp-supported-hw = <0x01 0xFFFF>;
116 };
117
118 oppturbo@800000000 {
119 opp-hz = /bits/ 64 <800000000>;
120 opp-microvolt = <1260000 1234800 1285200>;
121 opp-supported-hw = <0x06 0x0100>;
122 };
123
124 oppnitro@1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1325000 1298500 1351500>;
127 opp-supported-hw = <0x04 0x0200>;
128 };
129 };
130
131 pmu { 69 pmu {
132 compatible = "arm,cortex-a8-pmu"; 70 compatible = "arm,cortex-a8-pmu";
133 interrupts = <3>; 71 interrupts = <3>;