diff options
| author | Gabriel Fernandez <gabriel.fernandez@linaro.org> | 2015-06-23 10:09:00 -0400 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2015-07-22 05:41:33 -0400 |
| commit | 5eb26c60590983e11f567916a83d1f0a70986553 (patch) | |
| tree | 4c3073dc88c4bfc9fcf1982cee21513ca636fbc0 /arch/arm/boot/dts/stih410-clock.dtsi | |
| parent | 0a8c739c066254195b86bc8387fe16e5f72a5bdd (diff) | |
ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih410-clock.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih410-clock.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 6b5803a30096..d1f2acafc9b6 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi | |||
| @@ -137,7 +137,7 @@ | |||
| 137 | 137 | ||
| 138 | clk_s_c0_pll0: clk-s-c0-pll0 { | 138 | clk_s_c0_pll0: clk-s-c0-pll0 { |
| 139 | #clock-cells = <1>; | 139 | #clock-cells = <1>; |
| 140 | compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; | 140 | compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; |
| 141 | 141 | ||
| 142 | clocks = <&clk_sysin>; | 142 | clocks = <&clk_sysin>; |
| 143 | 143 | ||
| @@ -146,7 +146,7 @@ | |||
| 146 | 146 | ||
| 147 | clk_s_c0_pll1: clk-s-c0-pll1 { | 147 | clk_s_c0_pll1: clk-s-c0-pll1 { |
| 148 | #clock-cells = <1>; | 148 | #clock-cells = <1>; |
| 149 | compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; | 149 | compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; |
| 150 | 150 | ||
| 151 | clocks = <&clk_sysin>; | 151 | clocks = <&clk_sysin>; |
| 152 | 152 | ||