ARM: mvebu: update Armada XP DT for dynamic frequency scaling

In order to support dynamic frequency scaling:

 * the cpuclk Device Tree node needs to be updated to describe a
   second set of registers describing the PMU DFS registers.

 * the clock-latency property of the CPUs must be filled, otherwise
   the ondemand and conservative cpufreq governors refuse to work. The
   latency is high because the cost of a frequency transition is quite
   high on those CPUs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 6da84bf40aaf..2c7b1fef4703 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -37,6 +37,7 @@
                         compatible = "marvell,sheeva-v7";
                         reg = <0>;
                         clocks = <&cpuclk 0>;
+                        clock-latency = <1000000>;
                 };
 
                 cpu@1 {
@@ -44,6 +45,7 @@
                         compatible = "marvell,sheeva-v7";
                         reg = <1>;
                         clocks = <&cpuclk 1>;
+                        clock-latency = <1000000>;
                 };
 
                 cpu@2 {
@@ -51,6 +53,7 @@
                         compatible = "marvell,sheeva-v7";
                         reg = <2>;
                         clocks = <&cpuclk 2>;
+                        clock-latency = <1000000>;
                 };
 
                 cpu@3 {
@@ -58,6 +61,7 @@
                         compatible = "marvell,sheeva-v7";
                         reg = <3>;
                         clocks = <&cpuclk 3>;
+                        clock-latency = <1000000>;
                 };
         };