ARCv2: IOC: use @ioc_enable not @ioc_exist where intended

if user disables IOC from debugger at startup (by clearing @ioc_enable),
@ioc_exists is cleared too. This means boot prints don't capture the
fact that IOC was present but disabled which could be misleading.

So invert how we use @ioc_enable and @ioc_exists and make it more
canonical. @ioc_exists represent whether hardware is present or not and
stays same whether enabled or not. @ioc_enable is still user driven,
but will be auto-disabled if IOC hardware is not present, i.e. if
@ioc_exist=0. This is opposite to what we were doing before, but much
clearer.

This means @ioc_enable is now the "exported" toggle in rest of code such
as dma mapping API.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

3 files changed, 9 insertions, 7 deletions

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index fb781e34f322..b3410ff6a62d 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -53,7 +53,7 @@ extern void arc_cache_init(void);
 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
 extern void read_decode_cache_bcr(void);
 
-extern int ioc_exists;
+extern int ioc_enable;
 extern unsigned long perip_base, perip_end;
 
 #endif  /* !__ASSEMBLY__ */
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 97dddbefb86a..518ff76771f3 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -22,8 +22,8 @@
 #include <asm/setup.h>
 
 static int l2_line_sz;
-int ioc_exists;
-volatile int slc_enable = 1, ioc_enable = 1;
+static int ioc_exists;
+int slc_enable = 1, ioc_enable = 1;
 unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
 unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
 
@@ -113,8 +113,10 @@ static void read_decode_cache_bcr_arcv2(int cpu)
         }
 
         READ_BCR(ARC_REG_CLUSTER_BCR, cbcr);
-        if (cbcr.c && ioc_enable)
+        if (cbcr.c)
                 ioc_exists = 1;
+        else
+                ioc_enable = 0;
 
         /* HS 2.0 didn't have AUX_VOL */
         if (cpuinfo_arc700[cpu].core.family > 0x51) {
@@ -1002,7 +1004,7 @@ void arc_cache_init(void)
                         read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE);
         }
 
-        if (is_isa_arcv2() && ioc_exists) {
+        if (is_isa_arcv2() && ioc_enable) {
                 /* IO coherency base - 0x8z */
                 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
                 /* IO coherency aperture size - 512Mb: 0x8z-0xAz */
diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c
index 20afc65e22dc..60aab5a7522b 100644
--- a/arch/arc/mm/dma.c
+++ b/arch/arc/mm/dma.c
@@ -45,7 +45,7 @@ static void *arc_dma_alloc(struct device *dev, size_t size,
          *   -For coherent data, Read/Write to buffers terminate early in cache
          *   (vs. always going to memory - thus are faster)
          */
-        if ((is_isa_arcv2() && ioc_exists) ||
+        if ((is_isa_arcv2() && ioc_enable) ||
             (attrs & DMA_ATTR_NON_CONSISTENT))
                 need_coh = 0;
 
@@ -97,7 +97,7 @@ static void arc_dma_free(struct device *dev, size_t size, void *vaddr,
         int is_non_coh = 1;
 
         is_non_coh = (attrs & DMA_ATTR_NON_CONSISTENT) ||
-                        (is_isa_arcv2() && ioc_exists);
+                        (is_isa_arcv2() && ioc_enable);
 
         if (PageHighMem(page) || !is_non_coh)
                 iounmap((void __force __iomem *)vaddr);