Merge tag 'hisi-soc-dt-for-4.9' of git://github.com/hisilicon/linux-hisi into next/dt64

Pull "ARM64: DT: Hisilicon SoC DT updates for 4.9" from Wei Xu:

- Set UART1 clock frequency to 150MHz for higher baud rates on hikey
- Add display subsystem, HDMI and cma nodes on hikey to support display
- Add syscon-reboot-mode support on hikey
- Add pstore support on hikey
- Add resets and sd-uhs-sdr property dwmmc ndoe on hikey
- Remove hip05_hns.dtsi since it can not be built without mbigenv1
- Update system controller bingding document for hip05 and hip06
- Add xge and sas support on hip06

* tag 'hisi-soc-dt-for-4.9' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hi6220: add sd-uhs- properties into dwmmc_1
  arm64: dts: hi6220: add resets property into dwmmc nodes
  arm64: dts: hikey: extend default cma size to 128MB
  arm64: dts: hip06: Append sas node
  arm64: dts: hip06: Append hns node
  dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support
  arm64: dts: hip05: kill hip05_hns.dtsi
  arm64: dts: hikey: Add pstore support for HiKey
  arm64: dts: hikey: Add hikey support for syscon-reboot-mode
  arm64: dts: Add HDMI node for hi6220-hikey
  arm64: dts: Add display subsystem DT nodes for hi6220-hikey
  arm64: dts: set UART1 clock frequency to 150MHz

1 files changed, 28 insertions, 11 deletions

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 83fe816ae050..3f81575aa6be 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -175,38 +175,55 @@ Example:
         };
 
 -----------------------------------------------------------------------
-Hisilicon HiP05 PCIe-SAS system controller
+Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
 
 Required properties:
 - compatible : "hisilicon,pcie-sas-subctrl", "syscon";
 - reg : Register address and size
 
-The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
-HiP05 Soc to implement some basic configurations.
+The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
 
 Example:
-        /* for HiP05 PCIe-SAS system */
-        pcie_sas: system_controller@0xb0000000 {
+        /* for HiP05 PCIe-SAS sub system */
+        pcie_sas: system_controller@b0000000 {
                 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
                 reg = <0xb0000000 0x10000>;
         };
 
-Hisilicon HiP05 PERISUB system controller
+Hisilicon HiP05/HiP06 PERI sub system controller
 
 Required properties:
-- compatible : "hisilicon,hip05-perisubc", "syscon";
+- compatible : "hisilicon,peri-subctrl", "syscon";
 - reg : Register address and size
 
-The HiP05 PERISUB system controller is shared by peripheral controllers in
-HiP05 Soc to implement some basic configurations. The peripheral
+The PERI sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
 controllers include mdio, ddr, iic, uart, timer and so on.
 
 Example:
-        /* for HiP05 perisub-ctrl-c system */
+        /* for HiP05 sub peri system */
         peri_c_subctrl: syscon@80000000 {
-                compatible = "hisilicon,hip05-perisubc", "syscon";
+                compatible = "hisilicon,peri-subctrl", "syscon";
                 reg = <0x0 0x80000000 0x0 0x10000>;
         };
+
+Hisilicon HiP05/HiP06 DSA sub system controller
+
+Required properties:
+- compatible : "hisilicon,dsa-subctrl", "syscon";
+- reg : Register address and size
+
+The DSA sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
+
+Example:
+        /* for HiP05 dsa sub system */
+        pcie_sas: system_controller@a0000000 {
+                compatible = "hisilicon,dsa-subctrl", "syscon";
+                reg = <0xa0000000 0x10000>;
+        };
+
 -----------------------------------------------------------------------
 Hisilicon CPU controller