diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2015-01-02 02:39:22 -0500 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2015-02-04 05:32:04 -0500 |
| commit | 6761a8f60633fc40d062436abb1e3c4877329968 (patch) | |
| tree | eff7ae7d34ad9d6adbb1100b1a074fa4ff69c52a /Documentation/devicetree/bindings/video | |
| parent | 472da57b1c6f26aa508e4b4dfaf4f8c562bfdbfb (diff) | |
Doc/DT: Add DT binding doc for DRA7xx DSS
Add device tree binding documentation for DRA7xx display subsystem.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
Diffstat (limited to 'Documentation/devicetree/bindings/video')
| -rw-r--r-- | Documentation/devicetree/bindings/video/ti,dra7-dss.txt | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/video/ti,dra7-dss.txt b/Documentation/devicetree/bindings/video/ti,dra7-dss.txt new file mode 100644 index 000000000000..f33a05137b0e --- /dev/null +++ b/Documentation/devicetree/bindings/video/ti,dra7-dss.txt | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | Texas Instruments DRA7x Display Subsystem | ||
| 2 | ========================================= | ||
| 3 | |||
| 4 | See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic | ||
| 5 | description about OMAP Display Subsystem bindings. | ||
| 6 | |||
| 7 | DSS Core | ||
| 8 | -------- | ||
| 9 | |||
| 10 | Required properties: | ||
| 11 | - compatible: "ti,dra7-dss" | ||
| 12 | - reg: address and length of the register spaces for 'dss' | ||
| 13 | - ti,hwmods: "dss_core" | ||
| 14 | - clocks: handle to fclk | ||
| 15 | - clock-names: "fck" | ||
| 16 | - syscon: phandle to control module core syscon node | ||
| 17 | |||
| 18 | Optional properties: | ||
| 19 | |||
| 20 | Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties | ||
| 21 | can be used to describe the video PLLs: | ||
| 22 | |||
| 23 | - reg: address and length of the register spaces for 'pll1_clkctrl', | ||
| 24 | 'pll1', 'pll2_clkctrl', 'pll2' | ||
| 25 | - clocks: handle to video1 pll clock and video2 pll clock | ||
| 26 | - clock-names: "video1_clk" and "video2_clk" | ||
| 27 | |||
| 28 | Required nodes: | ||
| 29 | - DISPC | ||
| 30 | |||
| 31 | Optional nodes: | ||
| 32 | - DSS Submodules: HDMI | ||
| 33 | - Video port for DPI output | ||
| 34 | |||
| 35 | DPI Endpoint required properties: | ||
| 36 | - data-lines: number of lines used | ||
| 37 | |||
| 38 | |||
| 39 | DISPC | ||
| 40 | ----- | ||
| 41 | |||
| 42 | Required properties: | ||
| 43 | - compatible: "ti,dra7-dispc" | ||
| 44 | - reg: address and length of the register space | ||
| 45 | - ti,hwmods: "dss_dispc" | ||
| 46 | - interrupts: the DISPC interrupt | ||
| 47 | - clocks: handle to fclk | ||
| 48 | - clock-names: "fck" | ||
| 49 | |||
| 50 | HDMI | ||
| 51 | ---- | ||
| 52 | |||
| 53 | Required properties: | ||
| 54 | - compatible: "ti,dra7-hdmi" | ||
| 55 | - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', | ||
| 56 | 'core' | ||
| 57 | - reg-names: "wp", "pll", "phy", "core" | ||
| 58 | - interrupts: the HDMI interrupt line | ||
| 59 | - ti,hwmods: "dss_hdmi" | ||
| 60 | - vdda-supply: vdda power supply | ||
| 61 | - clocks: handles to fclk and pll clock | ||
| 62 | - clock-names: "fck", "sys_clk" | ||
| 63 | |||
| 64 | Optional nodes: | ||
| 65 | - Video port for HDMI output | ||
| 66 | |||
| 67 | HDMI Endpoint optional properties: | ||
| 68 | - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, | ||
| 69 | D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) | ||