diff options
| author | Hyungwon Hwang <human.hwang@samsung.com> | 2015-06-12 08:59:03 -0400 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2015-06-22 07:05:00 -0400 |
| commit | 26269af95af83145a3bccca41344c66502fdded9 (patch) | |
| tree | 10d7d375f751e2a61cc1a9c0a51c4d6c07cb7ee0 /Documentation/devicetree/bindings/video | |
| parent | 77bbd8914a91fab25f567772db60e2d1372de8c6 (diff) | |
drm/exynos: dsi: rename pll_clk to sclk_clk
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly. But for the backward
compatibility, the old clock name "pll_clk" is also OK.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'Documentation/devicetree/bindings/video')
| -rw-r--r-- | Documentation/devicetree/bindings/video/exynos_dsim.txt | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 802aa7ef64e5..44659dd62b80 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt | |||
| @@ -10,13 +10,14 @@ Required properties: | |||
| 10 | - interrupts: should contain DSI interrupt | 10 | - interrupts: should contain DSI interrupt |
| 11 | - clocks: list of clock specifiers, must contain an entry for each required | 11 | - clocks: list of clock specifiers, must contain an entry for each required |
| 12 | entry in clock-names | 12 | entry in clock-names |
| 13 | - clock-names: should include "bus_clk"and "pll_clk" entries | 13 | - clock-names: should include "bus_clk"and "sclk_mipi" entries |
| 14 | the use of "pll_clk" is deprecated | ||
| 14 | - phys: list of phy specifiers, must contain an entry for each required | 15 | - phys: list of phy specifiers, must contain an entry for each required |
| 15 | entry in phy-names | 16 | entry in phy-names |
| 16 | - phy-names: should include "dsim" entry | 17 | - phy-names: should include "dsim" entry |
| 17 | - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) | 18 | - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) |
| 18 | - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) | 19 | - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) |
| 19 | - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock | 20 | - samsung,pll-clock-frequency: specifies frequency of the oscillator clock |
| 20 | - #address-cells, #size-cells: should be set respectively to <1> and <0> | 21 | - #address-cells, #size-cells: should be set respectively to <1> and <0> |
| 21 | according to DSI host bindings (see MIPI DSI bindings [1]) | 22 | according to DSI host bindings (see MIPI DSI bindings [1]) |
| 22 | 23 | ||
| @@ -48,7 +49,7 @@ Example: | |||
| 48 | reg = <0x11C80000 0x10000>; | 49 | reg = <0x11C80000 0x10000>; |
| 49 | interrupts = <0 79 0>; | 50 | interrupts = <0 79 0>; |
| 50 | clocks = <&clock 286>, <&clock 143>; | 51 | clocks = <&clock 286>, <&clock 143>; |
| 51 | clock-names = "bus_clk", "pll_clk"; | 52 | clock-names = "bus_clk", "sclk_mipi"; |
| 52 | phys = <&mipi_phy 1>; | 53 | phys = <&mipi_phy 1>; |
| 53 | phy-names = "dsim"; | 54 | phy-names = "dsim"; |
| 54 | vddcore-supply = <&vusb_reg>; | 55 | vddcore-supply = <&vusb_reg>; |