Merge tag 'char-misc-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver updates from Greg KH:
 "Here is the big char/misc driver update for 4.4-rc1.  Lots of
  different driver and subsystem updates, hwtracing being the largest
  with the addition of some new platforms that are now supported.  Full
  details in the shortlog.

  All of these have been in linux-next for a long time with no reported
  issues"

* tag 'char-misc-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (181 commits)
  fpga: socfpga: Fix check of return value of devm_request_irq
  lkdtm: fix ACCESS_USERSPACE test
  mcb: Destroy IDA on module unload
  mcb: Do not return zero on error path in mcb_pci_probe()
  mei: bus: set the device name before running fixup
  mei: bus: use correct lock ordering
  mei: Fix debugfs filename in error output
  char: ipmi: ipmi_ssif: Replace timeval with timespec64
  fpga: zynq-fpga: Fix issue with drvdata being overwritten.
  fpga manager: remove unnecessary null pointer checks
  fpga manager: ensure lifetime with of_fpga_mgr_get
  fpga: zynq-fpga: Change fw format to handle bin instead of bit.
  fpga: zynq-fpga: Fix unbalanced clock handling
  misc: sram: partition base address belongs to __iomem space
  coresight: etm3x: adding documentation for sysFS's cpu interface
  vme: 8-bit status/id takes 256 values, not 255
  fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
  ARM: zynq: dt: Updated devicetree for Zynq 7000 platform.
  ARM: dt: fpga: Added binding docs for Xilinx Zynq FPGA manager.
  ver_linux: proc/modules, limit text processing to 'sed'
  ...

1 files changed, 76 insertions, 7 deletions

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
index d72ca1736ba4..924265a1295d 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
@@ -8,13 +8,6 @@ Description:	(RW) Enable/disable tracing on this specific trace entiry.
                 of coresight components linking the source to the sink is
                 configured and managed automatically by the coresight framework.
 
-What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/status
-Date:           November 2014
-KernelVersion:  3.19
-Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
-Description:    (R) List various control and status registers.  The specific
-                layout and content is driver specific.
-
 What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
 Date:           November 2014
 KernelVersion:  3.19
@@ -251,3 +244,79 @@ Date:		November 2014
 KernelVersion:  3.19
 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:    (RW) Define the event that controls the trigger.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu
+Date:           October 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Holds the cpu number this tracer is affined to.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Configuration Code register
+                (0x004).  The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccer
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Configuration Code Extension
+                register (0x1e8).  The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmscr
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM System Configuration
+                register (0x014).  The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmidr
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM ID register (0x1e4).  The
+                value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmcr
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Main Control register (0x000).
+                The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtraceidr
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Trace ID register (0x200).
+                The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmteevr
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Trace Enable Event register
+                (0x020). The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtsscr
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Trace Start/Stop Conrol
+                register (0x018). The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Enable Conrol #1
+                register (0x024). The value is read directly from the HW.
+
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2
+Date:           September 2015
+KernelVersion:  4.4
+Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:    (RO) Print the content of the ETM Enable Conrol #2
+                register (0x01c). The value is read directly from the HW.