diff options
author | Elaine Zhang <zhangqing@rock-chips.com> | 2016-03-09 16:24:38 -0500 |
---|---|---|
committer | Heiko Stuebner <heiko@sntech.de> | 2016-03-28 07:16:45 -0400 |
commit | fd8b62cc38b356bcdf20ac8f1a647db7b11240cf (patch) | |
tree | aed133fcbe83b1c74e6a66a06ba0aabd97c38769 | |
parent | e6e270aecbb0ed605b7267fdf6f828945014de24 (diff) |
soc: rockchip: power-domain: Modify power domain driver for rk3399
This driver is modified to support RK3399 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[small indentation fixups]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r-- | drivers/soc/rockchip/pm_domains.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index c179de3cd514..2116131528f7 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/mfd/syscon.h> | 19 | #include <linux/mfd/syscon.h> |
20 | #include <dt-bindings/power/rk3288-power.h> | 20 | #include <dt-bindings/power/rk3288-power.h> |
21 | #include <dt-bindings/power/rk3368-power.h> | 21 | #include <dt-bindings/power/rk3368-power.h> |
22 | #include <dt-bindings/power/rk3399-power.h> | ||
22 | 23 | ||
23 | struct rockchip_domain_info { | 24 | struct rockchip_domain_info { |
24 | int pwr_mask; | 25 | int pwr_mask; |
@@ -79,6 +80,9 @@ struct rockchip_pmu { | |||
79 | #define DOMAIN_RK3368(pwr, status, req) \ | 80 | #define DOMAIN_RK3368(pwr, status, req) \ |
80 | DOMAIN(pwr, status, req, (req) + 16, req) | 81 | DOMAIN(pwr, status, req, (req) + 16, req) |
81 | 82 | ||
83 | #define DOMAIN_RK3399(pwr, status, req) \ | ||
84 | DOMAIN(pwr, status, req, req, req) | ||
85 | |||
82 | static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) | 86 | static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) |
83 | { | 87 | { |
84 | struct rockchip_pmu *pmu = pd->pmu; | 88 | struct rockchip_pmu *pmu = pd->pmu; |
@@ -530,6 +534,36 @@ static const struct rockchip_domain_info rk3368_pm_domains[] = { | |||
530 | [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2), | 534 | [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2), |
531 | }; | 535 | }; |
532 | 536 | ||
537 | static const struct rockchip_domain_info rk3399_pm_domains[] = { | ||
538 | [RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1), | ||
539 | [RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1), | ||
540 | [RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1), | ||
541 | [RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15), | ||
542 | [RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16), | ||
543 | [RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1), | ||
544 | [RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2), | ||
545 | [RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14), | ||
546 | [RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17), | ||
547 | [RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0), | ||
548 | [RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3), | ||
549 | [RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4), | ||
550 | [RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5), | ||
551 | [RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6), | ||
552 | [RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1), | ||
553 | [RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7), | ||
554 | [RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8), | ||
555 | [RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9), | ||
556 | [RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10), | ||
557 | [RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11), | ||
558 | [RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23), | ||
559 | [RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24), | ||
560 | [RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12), | ||
561 | [RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22), | ||
562 | [RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27), | ||
563 | [RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28), | ||
564 | [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29), | ||
565 | }; | ||
566 | |||
533 | static const struct rockchip_pmu_info rk3288_pmu = { | 567 | static const struct rockchip_pmu_info rk3288_pmu = { |
534 | .pwr_offset = 0x08, | 568 | .pwr_offset = 0x08, |
535 | .status_offset = 0x0c, | 569 | .status_offset = 0x0c, |
@@ -564,6 +598,23 @@ static const struct rockchip_pmu_info rk3368_pmu = { | |||
564 | .domain_info = rk3368_pm_domains, | 598 | .domain_info = rk3368_pm_domains, |
565 | }; | 599 | }; |
566 | 600 | ||
601 | static const struct rockchip_pmu_info rk3399_pmu = { | ||
602 | .pwr_offset = 0x14, | ||
603 | .status_offset = 0x18, | ||
604 | .req_offset = 0x60, | ||
605 | .idle_offset = 0x64, | ||
606 | .ack_offset = 0x68, | ||
607 | |||
608 | .core_pwrcnt_offset = 0x9c, | ||
609 | .gpu_pwrcnt_offset = 0xa4, | ||
610 | |||
611 | .core_power_transition_time = 24, | ||
612 | .gpu_power_transition_time = 24, | ||
613 | |||
614 | .num_domains = ARRAY_SIZE(rk3399_pm_domains), | ||
615 | .domain_info = rk3399_pm_domains, | ||
616 | }; | ||
617 | |||
567 | static const struct of_device_id rockchip_pm_domain_dt_match[] = { | 618 | static const struct of_device_id rockchip_pm_domain_dt_match[] = { |
568 | { | 619 | { |
569 | .compatible = "rockchip,rk3288-power-controller", | 620 | .compatible = "rockchip,rk3288-power-controller", |
@@ -573,6 +624,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { | |||
573 | .compatible = "rockchip,rk3368-power-controller", | 624 | .compatible = "rockchip,rk3368-power-controller", |
574 | .data = (void *)&rk3368_pmu, | 625 | .data = (void *)&rk3368_pmu, |
575 | }, | 626 | }, |
627 | { | ||
628 | .compatible = "rockchip,rk3399-power-controller", | ||
629 | .data = (void *)&rk3399_pmu, | ||
630 | }, | ||
576 | { /* sentinel */ }, | 631 | { /* sentinel */ }, |
577 | }; | 632 | }; |
578 | 633 | ||